sound/firewire/dice.c

   1 /*
   2  * TC Applied Technologies Digital Interface Communications Engine driver
   3  *
   4  * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
   5  * Licensed under the terms of the GNU General Public License, version 2.
   6  */
   7
   8 #include <linux/delay.h>
   9 #include <linux/device.h>
  10 #include <linux/firewire.h>
  11 #include <linux/firewire-constants.h>
  12 #include <linux/module.h>
  13 #include <linux/mod_devicetable.h>
  14 #include <linux/mutex.h>
  15 #include <linux/slab.h>
  16 #include <sound/control.h>
  17 #include <sound/core.h>
  18 #include <sound/hwdep.h>
  19 #include <sound/initval.h>
  20 #include <sound/pcm.h>
  21 #include <sound/pcm_params.h>
  22 #include "amdtp.h"
  23 #include "iso-resources.h"
  24 #include "lib.h"
  25
  26 #define DICE_PRIVATE_SPACE              0xffffe0000000uLL
  27
  28 /* offset from DICE_PRIVATE_SPACE; offsets and sizes in quadlets */
  29 #define DICE_GLOBAL_OFFSET              0x00
  30 #define DICE_GLOBAL_SIZE                0x04
  31 #define DICE_TX_OFFSET                  0x08
  32 #define DICE_TX_SIZE                    0x0c
  33 #define DICE_RX_OFFSET                  0x10
  34 #define DICE_RX_SIZE                    0x14
  35
  36 /* pointed to by DICE_GLOBAL_OFFSET */
  37 #define GLOBAL_OWNER                    0x000
  38 #define  OWNER_NO_OWNER                 0xffff000000000000uLL
  39 #define  OWNER_NODE_SHIFT               48
  40 #define GLOBAL_NOTIFICATION             0x008
  41 #define  NOTIFY_RX_CFG_CHG              0x00000001
  42 #define  NOTIFY_TX_CFG_CHG              0x00000002
  43 #define  NOTIFY_DUP_ISOC                0x00000004
  44 #define  NOTIFY_BW_ERR                  0x00000008
  45 #define  NOTIFY_LOCK_CHG                0x00000010
  46 #define  NOTIFY_CLOCK_ACCEPTED          0x00000020
  47 #define  NOTIFY_INTERFACE_CHG           0x00000040
  48 #define  NOTIFY_MESSAGE                 0x00100000
  49 #define GLOBAL_NICK_NAME                0x00c
  50 #define  NICK_NAME_SIZE                 64
  51 #define GLOBAL_CLOCK_SELECT             0x04c
  52 #define  CLOCK_SOURCE_MASK              0x000000ff
  53 #define  CLOCK_SOURCE_AES1              0x00000000
  54 #define  CLOCK_SOURCE_AES2              0x00000001
  55 #define  CLOCK_SOURCE_AES3              0x00000002
  56 #define  CLOCK_SOURCE_AES4              0x00000003
  57 #define  CLOCK_SOURCE_AES_ANY           0x00000004
  58 #define  CLOCK_SOURCE_ADAT              0x00000005
  59 #define  CLOCK_SOURCE_TDIF              0x00000006
  60 #define  CLOCK_SOURCE_WC                0x00000007
  61 #define  CLOCK_SOURCE_ARX1              0x00000008
  62 #define  CLOCK_SOURCE_ARX2              0x00000009
  63 #define  CLOCK_SOURCE_ARX3              0x0000000a
  64 #define  CLOCK_SOURCE_ARX4              0x0000000b
  65 #define  CLOCK_SOURCE_INTERNAL          0x0000000c
  66 #define  CLOCK_RATE_MASK                0x0000ff00
  67 #define  CLOCK_RATE_32000               0x00000000
  68 #define  CLOCK_RATE_44100               0x00000100
  69 #define  CLOCK_RATE_48000               0x00000200
  70 #define  CLOCK_RATE_88200               0x00000300
  71 #define  CLOCK_RATE_96000               0x00000400
  72 #define  CLOCK_RATE_176400              0x00000500
  73 #define  CLOCK_RATE_192000              0x00000600
  74 #define  CLOCK_RATE_ANY_LOW             0x00000700
  75 #define  CLOCK_RATE_ANY_MID             0x00000800
  76 #define  CLOCK_RATE_ANY_HIGH            0x00000900
  77 #define  CLOCK_RATE_NONE                0x00000a00
  78 #define  CLOCK_RATE_SHIFT               8
  79 #define GLOBAL_ENABLE                   0x050
  80 #define  ENABLE                         0x00000001
  81 #define GLOBAL_STATUS                   0x054
  82 #define  STATUS_SOURCE_LOCKED           0x00000001
  83 #define  STATUS_RATE_CONFLICT           0x00000002
  84 #define  STATUS_NOMINAL_RATE_MASK       0x0000ff00
  85 #define GLOBAL_EXTENDED_STATUS          0x058
  86 #define  EXT_STATUS_AES1_LOCKED         0x00000001
  87 #define  EXT_STATUS_AES2_LOCKED         0x00000002
  88 #define  EXT_STATUS_AES3_LOCKED         0x00000004
  89 #define  EXT_STATUS_AES4_LOCKED         0x00000008
  90 #define  EXT_STATUS_ADAT_LOCKED         0x00000010
  91 #define  EXT_STATUS_TDIF_LOCKED         0x00000020
  92 #define  EXT_STATUS_ARX1_LOCKED         0x00000040
  93 #define  EXT_STATUS_ARX2_LOCKED         0x00000080
  94 #define  EXT_STATUS_ARX3_LOCKED         0x00000100
  95 #define  EXT_STATUS_ARX4_LOCKED         0x00000200
  96 #define  EXT_STATUS_WC_LOCKED           0x00000400
  97 #define  EXT_STATUS_AES1_SLIP           0x00010000
  98 #define  EXT_STATUS_AES2_SLIP           0x00020000
  99 #define  EXT_STATUS_AES3_SLIP           0x00040000
 100 #define  EXT_STATUS_AES4_SLIP           0x00080000
 101 #define  EXT_STATUS_ADAT_SLIP           0x00100000
 102 #define  EXT_STATUS_TDIF_SLIP           0x00200000
 103 #define  EXT_STATUS_ARX1_SLIP           0x00400000
 104 #define  EXT_STATUS_ARX2_SLIP           0x00800000
 105 #define  EXT_STATUS_ARX3_SLIP           0x01000000
 106 #define  EXT_STATUS_ARX4_SLIP           0x02000000
 107 #define  EXT_STATUS_WC_SLIP             0x04000000
 108 #define GLOBAL_SAMPLE_RATE              0x05c
 109 #define GLOBAL_VERSION                  0x060
 110 #define GLOBAL_CLOCK_CAPABILITIES       0x064
 111 #define  CLOCK_CAP_RATE_32000           0x00000001
 112 #define  CLOCK_CAP_RATE_44100           0x00000002
 113 #define  CLOCK_CAP_RATE_48000           0x00000004
 114 #define  CLOCK_CAP_RATE_88200           0x00000008
 115 #define  CLOCK_CAP_RATE_96000           0x00000010
 116 #define  CLOCK_CAP_RATE_176400          0x00000020
 117 #define  CLOCK_CAP_RATE_192000          0x00000040
 118 #define  CLOCK_CAP_SOURCE_AES1          0x00010000
 119 #define  CLOCK_CAP_SOURCE_AES2          0x00020000
 120 #define  CLOCK_CAP_SOURCE_AES3          0x00040000
 121 #define  CLOCK_CAP_SOURCE_AES4          0x00080000
 122 #define  CLOCK_CAP_SOURCE_AES_ANY       0x00100000
 123 #define  CLOCK_CAP_SOURCE_ADAT          0x00200000
 124 #define  CLOCK_CAP_SOURCE_TDIF          0x00400000
 125 #define  CLOCK_CAP_SOURCE_WC            0x00800000
 126 #define  CLOCK_CAP_SOURCE_ARX1          0x01000000
 127 #define  CLOCK_CAP_SOURCE_ARX2          0x02000000
 128 #define  CLOCK_CAP_SOURCE_ARX3          0x04000000
 129 #define  CLOCK_CAP_SOURCE_ARX4          0x08000000
 130 #define  CLOCK_CAP_SOURCE_INTERNAL      0x10000000
 131 #define GLOBAL_CLOCK_SOURCE_NAMES       0x068
 132 #define  CLOCK_SOURCE_NAMES_SIZE        256
 133
 134 /* pointed to by DICE_TX_OFFSET */
 135 #define TX_NUMBER                       0x000
 136 #define TX_SIZE                         0x004
 137 /* repeated TX_NUMBER times, offset by TX_SIZE quadlets */
 138 #define TX_ISOCHRONOUS                  0x008
 139 #define TX_NUMBER_AUDIO                 0x00c
 140 #define TX_NUMBER_MIDI                  0x010
 141 #define TX_SPEED                        0x014
 142 #define TX_NAMES                        0x018
 143 #define  TX_NAMES_SIZE                  256
 144 #define TX_AC3_CAPABILITIES             0x118
 145 #define TX_AC3_ENABLE                   0x11c
 146
 147 /* pointed to by DICE_RX_OFFSET */
 148 #define RX_NUMBER                       0x000
 149 #define RX_SIZE                         0x004
 150 /* repeated RX_NUMBER times, offset by RX_SIZE quadlets */
 151 #define RX_ISOCHRONOUS                  0x008
 152 #define RX_SEQ_START                    0x00c
 153 #define RX_NUMBER_AUDIO                 0x010
 154 #define RX_NUMBER_MIDI                  0x014
 155 #define RX_NAMES                        0x018
 156 #define  RX_NAMES_SIZE                  256
 157 #define RX_AC3_CAPABILITIES             0x118
 158 #define RX_AC3_ENABLE                   0x11c
 159
 160
 161 #define FIRMWARE_LOAD_SPACE             0xffffe0100000uLL
 162
 163 /* offset from FIRMWARE_LOAD_SPACE */
 164 #define FIRMWARE_VERSION                0x000
 165 #define FIRMWARE_OPCODE                 0x004
 166 #define  OPCODE_MASK                    0x00000fff
 167 #define  OPCODE_GET_IMAGE_DESC          0x00000000
 168 #define  OPCODE_DELETE_IMAGE            0x00000001
 169 #define  OPCODE_CREATE_IMAGE            0x00000002
 170 #define  OPCODE_UPLOAD                  0x00000003
 171 #define  OPCODE_UPLOAD_STAT             0x00000004
 172 #define  OPCODE_RESET_IMAGE             0x00000005
 173 #define  OPCODE_TEST_ACTION             0x00000006
 174 #define  OPCODE_GET_RUNNING_IMAGE_VINFO 0x0000000a
 175 #define  OPCODE_EXECUTE                 0x80000000
 176 #define FIRMWARE_RETURN_STATUS          0x008
 177 #define FIRMWARE_PROGRESS               0x00c
 178 #define  PROGRESS_CURR_MASK             0x00000fff
 179 #define  PROGRESS_MAX_MASK              0x00fff000
 180 #define  PROGRESS_TOUT_MASK             0x0f000000
 181 #define  PROGRESS_FLAG                  0x80000000
 182 #define FIRMWARE_CAPABILITIES           0x010
 183 #define  FL_CAP_AUTOERASE               0x00000001
 184 #define  FL_CAP_PROGRESS                0x00000002
 185 #define FIRMWARE_DATA                   0x02c
 186 #define  TEST_CMD_POKE                  0x00000001
 187 #define  TEST_CMD_PEEK                  0x00000002
 188 #define  CMD_GET_AVS_CNT                0x00000003
 189 #define  CMD_CLR_AVS_CNT                0x00000004
 190 #define  CMD_SET_MODE                   0x00000005
 191 #define  CMD_SET_MIDIBP                 0x00000006
 192 #define  CMD_GET_AVSPHASE               0x00000007
 193 #define  CMD_ENABLE_BNC_SYNC            0x00000008
 194 #define  CMD_PULSE_BNC_SYNC             0x00000009
 195 #define  CMD_EMUL_SLOW_CMD              0x0000000a
 196 #define FIRMWARE_TEST_DELAY             0xfd8
 197 #define FIRMWARE_TEST_BUF               0xfdc
 198
 199
 200 /* EAP */
 201 #define EAP_PRIVATE_SPACE               0xffffe0200000uLL
 202
 203 #define EAP_CAPABILITY_OFFSET           0x000
 204 #define EAP_CAPABILITY_SIZE             0x004
 205 /* ... */
 206
 207 #define EAP_ROUTER_CAPS                 0x000
 208 #define  ROUTER_EXPOSED                 0x00000001
 209 #define  ROUTER_READ_ONLY               0x00000002
 210 #define  ROUTER_FLASH                   0x00000004
 211 #define  MAX_ROUTES_MASK                0xffff0000
 212 #define EAP_MIXER_CAPS                  0x004
 213 #define  MIXER_EXPOSED                  0x00000001
 214 #define  MIXER_READ_ONLY                0x00000002
 215 #define  MIXER_FLASH                    0x00000004
 216 #define  MIXER_IN_DEV_MASK              0x000000f0
 217 #define  MIXER_OUT_DEV_MASK             0x00000f00
 218 #define  MIXER_INPUTS_MASK              0x00ff0000
 219 #define  MIXER_OUTPUTS_MASK             0xff000000
 220 #define EAP_GENERAL_CAPS                0x008
 221 #define  GENERAL_STREAM_CONFIG          0x00000001
 222 #define  GENERAL_FLASH                  0x00000002
 223 #define  GENERAL_PEAK                   0x00000004
 224 #define  GENERAL_MAX_TX_STREAMS_MASK    0x000000f0
 225 #define  GENERAL_MAX_RX_STREAMS_MASK    0x00000f00
 226 #define  GENERAL_STREAM_CONFIG_FLASH    0x00001000
 227 #define  GENERAL_CHIP_MASK              0x00ff0000
 228 #define  GENERAL_CHIP_DICE_II           0x00000000
 229 #define  GENERAL_CHIP_DICE_MINI         0x00010000
 230 #define  GENERAL_CHIP_DICE_JR           0x00020000
 231
 232
 233 struct dice {
 234         struct snd_card *card;
 235         struct fw_unit *unit;
 236         struct mutex mutex;
 237         unsigned int global_offset;
 238         unsigned int rx_offset;
 239         struct fw_address_handler notification_handler;
 240         int owner_generation;
 241         bool global_enabled;
 242         bool stream_running;
 243         struct snd_pcm_substream *pcm;
 244         struct fw_iso_resources resources;
 245         struct amdtp_out_stream stream;
 246 };
 247
 248 MODULE_DESCRIPTION("DICE driver");
 249 MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
 250 MODULE_LICENSE("GPL v2");
 251
 252 static const unsigned int dice_rates[] = {
 253         [0] =  32000,
 254         [1] =  44100,
 255         [2] =  48000,
 256         [3] =  88200,
 257         [4] =  96000,
 258         [5] = 176400,
 259         [6] = 192000,
 260 };
 261
 262 static inline u64 global_address(struct dice *dice, unsigned int offset)
 263 {
 264         return DICE_PRIVATE_SPACE + dice->global_offset + offset;
 265 }
 266
 267 // TODO: rx index
 268 static inline u64 rx_address(struct dice *dice, unsigned int offset)
 269 {
 270         return DICE_PRIVATE_SPACE + dice->rx_offset + offset;
 271 }
 272
 273 static int dice_owner_set(struct dice *dice)
 274 {
 275         struct fw_device *device = fw_parent_device(dice->unit);
 276         __be64 *buffer;
 277         int rcode, err, errors = 0;
 278
 279         buffer = kmalloc(2 * 8, GFP_KERNEL);
 280         if (!buffer)
 281                 return -ENOMEM;
 282
 283         for (;;) {
 284                 buffer[0] = cpu_to_be64(OWNER_NO_OWNER);
 285                 buffer[1] = cpu_to_be64(
 286                         ((u64)device->card->node_id << OWNER_NODE_SHIFT) |
 287                         dice->notification_handler.offset);
 288
 289                 dice->owner_generation = device->generation;
 290                 smp_rmb(); /* node_id vs. generation */
 291                 rcode = fw_run_transaction(device->card,
 292                                            TCODE_LOCK_COMPARE_SWAP,
 293                                            device->node_id,
 294                                            dice->owner_generation,
 295                                            device->max_speed,
 296                                            global_address(dice, GLOBAL_OWNER),
 297                                            buffer, 2 * 8);
 298
 299                 if (rcode == RCODE_COMPLETE) {
 300                         if (buffer[0] == cpu_to_be64(OWNER_NO_OWNER)) {
 301                                 err = 0;
 302                         } else {
 303                                 dev_err(&dice->unit->device,
 304                                         "device is already in use\n");
 305                                 err = -EBUSY;
 306                         }
 307                         break;
 308                 }
 309                 if (rcode_is_permanent_error(rcode) || ++errors >= 3) {
 310                         dev_err(&dice->unit->device,
 311                                 "setting device owner failed: %s\n",
 312                                 fw_rcode_string(rcode));
 313                         err = -EIO;
 314                         break;
 315                 }
 316                 msleep(20);
 317         }
 318
 319         kfree(buffer);
 320
 321         return err;
 322 }
 323
 324 static int dice_owner_update(struct dice *dice)
 325 {
 326         struct fw_device *device = fw_parent_device(dice->unit);
 327         __be64 *buffer;
 328         int rcode, err, errors = 0;
 329
 330         if (dice->owner_generation == -1)
 331                 return 0;
 332
 333         buffer = kmalloc(2 * 8, GFP_KERNEL);
 334         if (!buffer)
 335                 return -ENOMEM;
 336
 337         for (;;) {
 338                 buffer[0] = cpu_to_be64(OWNER_NO_OWNER);
 339                 buffer[1] = cpu_to_be64(
 340                         ((u64)device->card->node_id << OWNER_NODE_SHIFT) |
 341                         dice->notification_handler.offset);
 342
 343                 dice->owner_generation = device->generation;
 344                 smp_rmb(); /* node_id vs. generation */
 345                 rcode = fw_run_transaction(device->card,
 346                                            TCODE_LOCK_COMPARE_SWAP,
 347                                            device->node_id,
 348                                            dice->owner_generation,
 349                                            device->max_speed,
 350                                            global_address(dice, GLOBAL_OWNER),
 351                                            buffer, 2 * 8);
 352
 353                 if (rcode == RCODE_COMPLETE) {
 354                         if (buffer[0] == cpu_to_be64(OWNER_NO_OWNER)) {
 355                                 err = 0;
 356                         } else {
 357                                 dev_err(&dice->unit->device,
 358                                         "device is already in use\n");
 359                                 err = -EBUSY;
 360                         }
 361                         break;
 362                 }
 363                 if (rcode == RCODE_GENERATION) {
 364                         err = 0; /* try again later */
 365                         break;
 366                 }
 367                 if (rcode_is_permanent_error(rcode) || ++errors >= 3) {
 368                         dev_err(&dice->unit->device,
 369                                 "setting device owner failed: %s\n",
 370                                 fw_rcode_string(rcode));
 371                         err = -EIO;
 372                         break;
 373                 }
 374                 msleep(20);
 375         }
 376
 377         kfree(buffer);
 378
 379         if (err < 0)
 380                 dice->owner_generation = -1;
 381
 382         return err;
 383 }
 384
 385 static void dice_owner_clear(struct dice *dice)
 386 {
 387         struct fw_device *device = fw_parent_device(dice->unit);
 388         __be64 *buffer;
 389         int rcode, errors = 0;
 390
 391         buffer = kmalloc(2 * 8, GFP_KERNEL);
 392         if (!buffer)
 393                 return;
 394
 395         for (;;) {
 396                 buffer[0] = cpu_to_be64(
 397                         ((u64)device->card->node_id << OWNER_NODE_SHIFT) |
 398                         dice->notification_handler.offset);
 399                 buffer[1] = cpu_to_be64(OWNER_NO_OWNER);
 400
 401                 rcode = fw_run_transaction(device->card,
 402                                            TCODE_LOCK_COMPARE_SWAP,
 403                                            device->node_id,
 404                                            dice->owner_generation,
 405                                            device->max_speed,
 406                                            global_address(dice, GLOBAL_OWNER),
 407                                            buffer, 2 * 8);
 408
 409                 if (rcode == RCODE_COMPLETE)
 410                         break;
 411                 if (rcode == RCODE_GENERATION)
 412                         break;
 413                 if (rcode_is_permanent_error(rcode) || ++errors >= 3) {
 414                         dev_err(&dice->unit->device,
 415                                 "clearing device owner failed: %s\n",
 416                                 fw_rcode_string(rcode));
 417                         break;
 418                 }
 419                 msleep(20);
 420         }
 421
 422         kfree(buffer);
 423
 424         dice->owner_generation = -1;
 425 }
 426
 427 static int dice_enable_set(struct dice *dice)
 428 {
 429         struct fw_device *device = fw_parent_device(dice->unit);
 430         __be32 value;
 431         int rcode, err, errors = 0;
 432
 433         value = cpu_to_be32(ENABLE);
 434         for (;;) {
 435                 rcode = fw_run_transaction(device->card,
 436                                            TCODE_WRITE_QUADLET_REQUEST,
 437                                            device->node_id,
 438                                            dice->owner_generation,
 439                                            device->max_speed,
 440                                            global_address(dice, GLOBAL_ENABLE),
 441                                            &value, 4);
 442                 if (rcode == RCODE_COMPLETE) {
 443                         dice->global_enabled = true;
 444                         err = 0;
 445                         break;
 446                 }
 447                 if (rcode == RCODE_GENERATION) {
 448                         err = -EAGAIN;
 449                         break;
 450                 }
 451                 if (rcode_is_permanent_error(rcode) || ++errors >= 3) {
 452                         dev_err(&dice->unit->device,
 453                                 "device enabling failed: %s\n",
 454                                 fw_rcode_string(rcode));
 455                         err = -EIO;
 456                         break;
 457                 }
 458                 msleep(20);
 459         }
 460
 461         return err;
 462 }
 463
 464 static void dice_enable_clear(struct dice *dice)
 465 {
 466         struct fw_device *device = fw_parent_device(dice->unit);
 467         __be32 value;
 468         int rcode, errors = 0;
 469
 470         value = 0;
 471         for (;;) {
 472                 rcode = fw_run_transaction(device->card,
 473                                            TCODE_WRITE_QUADLET_REQUEST,
 474                                            device->node_id,
 475                                            dice->owner_generation,
 476                                            device->max_speed,
 477                                            global_address(dice, GLOBAL_ENABLE),
 478                                            &value, 4);
 479                 if (rcode == RCODE_COMPLETE ||
 480                     rcode == RCODE_GENERATION)
 481                         break;
 482                 if (rcode_is_permanent_error(rcode) || ++errors >= 3) {
 483                         dev_err(&dice->unit->device,
 484                                 "device disabling failed: %s\n",
 485                                 fw_rcode_string(rcode));
 486                         break;
 487                 }
 488                 msleep(20);
 489         }
 490         dice->global_enabled = false;
 491 }
 492
 493 static void dice_notification(struct fw_card *card, struct fw_request *request,
 494                               int tcode, int destination, int source,
 495                               int generation, unsigned long long offset,
 496                               void *data, size_t length, void *callback_data)
 497 {
 498         struct dice *dice = callback_data;
 499
 500         if (tcode != TCODE_WRITE_QUADLET_REQUEST) {
 501                 fw_send_response(card, request, RCODE_TYPE_ERROR);
 502                 return;
 503         }
 504         if ((offset & 3) != 0) {
 505                 fw_send_response(card, request, RCODE_ADDRESS_ERROR);
 506                 return;
 507         }
 508         dev_dbg(&dice->unit->device,
 509                 "notification: %08x\n", be32_to_cpup(data));
 510         fw_send_response(card, request, RCODE_COMPLETE);
 511 }
 512
 513 static int dice_open(struct snd_pcm_substream *substream)
 514 {
 515         static const struct snd_pcm_hardware hardware = {
 516                 .info = SNDRV_PCM_INFO_MMAP |
 517                         SNDRV_PCM_INFO_MMAP_VALID |
 518                         SNDRV_PCM_INFO_BATCH |
 519                         SNDRV_PCM_INFO_INTERLEAVED |
 520                         SNDRV_PCM_INFO_BLOCK_TRANSFER,
 521                 .formats = AMDTP_OUT_PCM_FORMAT_BITS,
 522                 .buffer_bytes_max = 16 * 1024 * 1024,
 523                 .period_bytes_min = 1,
 524                 .period_bytes_max = UINT_MAX,
 525                 .periods_min = 1,
 526                 .periods_max = UINT_MAX,
 527         };
 528         struct dice *dice = substream->private_data;
 529         struct snd_pcm_runtime *runtime = substream->runtime;
 530         __be32 clock_sel, number_audio, number_midi;
 531         unsigned int rate;
 532         int err;
 533
 534         err = snd_fw_transaction(dice->unit, TCODE_READ_QUADLET_REQUEST,
 535                                  global_address(dice, GLOBAL_CLOCK_SELECT),
 536                                  &clock_sel, 4);
 537         if (err < 0)
 538                 return err;
 539         rate = (be32_to_cpu(clock_sel) & CLOCK_RATE_MASK) >> CLOCK_RATE_SHIFT;
 540         if (rate >= ARRAY_SIZE(dice_rates))
 541                 return -ENXIO;
 542         rate = dice_rates[rate];
 543
 544         err = snd_fw_transaction(dice->unit, TCODE_READ_QUADLET_REQUEST,
 545                                  rx_address(dice, RX_NUMBER_AUDIO),
 546                                  &number_audio, 4);
 547         if (err < 0)
 548                 return err;
 549         err = snd_fw_transaction(dice->unit, TCODE_READ_QUADLET_REQUEST,
 550                                  rx_address(dice, RX_NUMBER_MIDI),
 551                                  &number_midi, 4);
 552         if (err < 0)
 553                 return err;
 554
 555         runtime->hw = hardware;
 556
 557         runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
 558         snd_pcm_limit_hw_rates(runtime);
 559
 560         runtime->hw.channels_min = be32_to_cpu(number_audio);
 561         runtime->hw.channels_max = be32_to_cpu(number_audio);
 562
 563         amdtp_out_stream_set_rate(&dice->stream, rate);
 564         amdtp_out_stream_set_pcm(&dice->stream, be32_to_cpu(number_audio));
 565         amdtp_out_stream_set_midi(&dice->stream, be32_to_cpu(number_midi));
 566
 567         err = snd_pcm_hw_constraint_minmax(runtime,
 568                                            SNDRV_PCM_HW_PARAM_PERIOD_TIME,
 569                                            5000, 8192000);
 570         if (err < 0)
 571                 return err;
 572
 573         err = snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
 574         if (err < 0)
 575                 return err;
 576
 577         return 0;
 578 }
 579
 580 static int dice_close(struct snd_pcm_substream *substream)
 581 {
 582         return 0;
 583 }
 584
 585 static int dice_stream_start_packets(struct dice *dice)
 586 {
 587         int err;
 588
 589         if (dice->stream_running)
 590                 return 0;
 591
 592         err = amdtp_out_stream_start(&dice->stream, dice->resources.channel,
 593                                      fw_parent_device(dice->unit)->max_speed);
 594         if (err < 0)
 595                 return err;
 596
 597         err = dice_enable_set(dice);
 598         if (err < 0) {
 599                 amdtp_out_stream_stop(&dice->stream);
 600                 return err;
 601         }
 602
 603         dice->stream_running = true;
 604
 605         return 0;
 606 }
 607
 608 static int dice_stream_start(struct dice *dice)
 609 {
 610         __be32 channel;
 611         int err;
 612
 613         if (!dice->resources.allocated) {
 614                 err = fw_iso_resources_allocate(&dice->resources,
 615                                 amdtp_out_stream_get_max_payload(&dice->stream),
 616                                 fw_parent_device(dice->unit)->max_speed);
 617                 if (err < 0)
 618                         goto error;
 619
 620                 channel = cpu_to_be32(dice->resources.channel);
 621                 err = snd_fw_transaction(dice->unit,
 622                                          TCODE_WRITE_QUADLET_REQUEST,
 623                                          rx_address(dice, RX_ISOCHRONOUS),
 624                                          &channel, 4);
 625                 if (err < 0)
 626                         goto err_resources;
 627         }
 628
 629         err = dice_stream_start_packets(dice);
 630         if (err < 0)
 631                 goto err_rx_channel;
 632
 633         return 0;
 634
 635 err_rx_channel:
 636         channel = cpu_to_be32((u32)-1);
 637         snd_fw_transaction(dice->unit, TCODE_WRITE_QUADLET_REQUEST,
 638                            rx_address(dice, RX_ISOCHRONOUS), &channel, 4);
 639 err_resources:
 640         fw_iso_resources_free(&dice->resources);
 641 error:
 642         return err;
 643 }
 644
 645 static void dice_stream_stop_packets(struct dice *dice)
 646 {
 647         if (!dice->stream_running)
 648                 return;
 649
 650         dice_enable_clear(dice);
 651
 652         amdtp_out_stream_stop(&dice->stream);
 653
 654         dice->stream_running = false;
 655 }
 656
 657 static void dice_stream_stop(struct dice *dice)
 658 {
 659         __be32 channel;
 660
 661         dice_stream_stop_packets(dice);
 662
 663         if (!dice->resources.allocated)
 664                 return;
 665
 666         channel = cpu_to_be32((u32)-1);
 667         snd_fw_transaction(dice->unit, TCODE_WRITE_QUADLET_REQUEST,
 668                            rx_address(dice, RX_ISOCHRONOUS), &channel, 4);
 669
 670         fw_iso_resources_free(&dice->resources);
 671 }
 672
 673 static int dice_hw_params(struct snd_pcm_substream *substream,
 674                           struct snd_pcm_hw_params *hw_params)
 675 {
 676         struct dice *dice = substream->private_data;
 677         int err;
 678
 679         mutex_lock(&dice->mutex);
 680         dice_stream_stop(dice);
 681         mutex_unlock(&dice->mutex);
 682
 683         err = snd_pcm_lib_alloc_vmalloc_buffer(substream,
 684                                                params_buffer_bytes(hw_params));
 685         if (err < 0)
 686                 goto error;
 687
 688         amdtp_out_stream_set_pcm_format(&dice->stream,
 689                                         params_format(hw_params));
 690
 691         return 0;
 692
 693 error:
 694         return err;
 695 }
 696
 697 static int dice_hw_free(struct snd_pcm_substream *substream)
 698 {
 699         struct dice *dice = substream->private_data;
 700
 701         mutex_lock(&dice->mutex);
 702         dice_stream_stop(dice);
 703         mutex_unlock(&dice->mutex);
 704
 705         return snd_pcm_lib_free_vmalloc_buffer(substream);
 706 }
 707
 708 static int dice_prepare(struct snd_pcm_substream *substream)
 709 {
 710         struct dice *dice = substream->private_data;
 711         int err;
 712
 713         mutex_lock(&dice->mutex);
 714
 715         if (amdtp_out_streaming_error(&dice->stream))
 716                 dice_stream_stop_packets(dice);
 717
 718         err = dice_stream_start(dice);
 719         if (err < 0) {
 720                 mutex_unlock(&dice->mutex);
 721                 return err;
 722         }
 723
 724         mutex_unlock(&dice->mutex);
 725
 726         amdtp_out_stream_pcm_prepare(&dice->stream);
 727
 728         return 0;
 729 }
 730
 731 static int dice_trigger(struct snd_pcm_substream *substream, int cmd)
 732 {
 733         struct dice *dice = substream->private_data;
 734         struct snd_pcm_substream *pcm;
 735
 736         switch (cmd) {
 737         case SNDRV_PCM_TRIGGER_START:
 738                 pcm = substream;
 739                 break;
 740         case SNDRV_PCM_TRIGGER_STOP:
 741                 pcm = NULL;
 742                 break;
 743         default:
 744                 return -EINVAL;
 745         }
 746         amdtp_out_stream_pcm_trigger(&dice->stream, pcm);
 747
 748         return 0;
 749 }
 750
 751 static snd_pcm_uframes_t dice_pointer(struct snd_pcm_substream *substream)
 752 {
 753         struct dice *dice = substream->private_data;
 754
 755         return amdtp_out_stream_pcm_pointer(&dice->stream);
 756 }
 757
 758 static int dice_create_pcm(struct dice *dice)
 759 {
 760         static struct snd_pcm_ops ops = {
 761                 .open      = dice_open,
 762                 .close     = dice_close,
 763                 .ioctl     = snd_pcm_lib_ioctl,
 764                 .hw_params = dice_hw_params,
 765                 .hw_free   = dice_hw_free,
 766                 .prepare   = dice_prepare,
 767                 .trigger   = dice_trigger,
 768                 .pointer   = dice_pointer,
 769                 .page      = snd_pcm_lib_get_vmalloc_page,
 770                 .mmap      = snd_pcm_lib_mmap_vmalloc,
 771         };
 772         struct snd_pcm *pcm;
 773         int err;
 774
 775         err = snd_pcm_new(dice->card, "DICE", 0, 1, 0, &pcm);
 776         if (err < 0)
 777                 return err;
 778         pcm->private_data = dice;
 779         strcpy(pcm->name, dice->card->shortname);
 780         dice->pcm = pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
 781         dice->pcm->ops = &ops;
 782
 783         return 0;
 784 }
 785
 786 // TODO: implement these
 787
 788 static long dice_hwdep_read(struct snd_hwdep *hwdep, char __user *buf,
 789                             long count, loff_t *offset)
 790 {
 791         return -EIO;
 792 }
 793
 794 static int dice_hwdep_open(struct snd_hwdep *hwdep, struct file *file)
 795 {
 796         return -EIO;
 797 }
 798
 799 static int dice_hwdep_release(struct snd_hwdep *hwdep, struct file *file)
 800 {
 801         return 0;
 802 }
 803
 804 static unsigned int dice_hwdep_poll(struct snd_hwdep *hwdep, struct file *file,
 805                                     poll_table *wait)
 806 {
 807         return POLLERR | POLLHUP;
 808 }
 809
 810 static int dice_hwdep_ioctl(struct snd_hwdep *hwdep, struct file *file,
 811                             unsigned int cmd, unsigned long arg)
 812 {
 813         return -EIO;
 814 }
 815
 816 static int dice_create_hwdep(struct dice *dice)
 817 {
 818         static const struct snd_hwdep_ops ops = {
 819                 .read         = dice_hwdep_read,
 820                 .open         = dice_hwdep_open,
 821                 .release      = dice_hwdep_release,
 822                 .poll         = dice_hwdep_poll,
 823                 .ioctl        = dice_hwdep_ioctl,
 824                 .ioctl_compat = dice_hwdep_ioctl,
 825         };
 826         struct snd_hwdep *hwdep;
 827         int err;
 828
 829         err = snd_hwdep_new(dice->card, "DICE", 0, &hwdep);
 830         if (err < 0)
 831                 return err;
 832         strcpy(hwdep->name, "DICE");
 833         hwdep->iface = SNDRV_HWDEP_IFACE_FW_DICE;
 834         hwdep->ops = ops;
 835         hwdep->private_data = dice;
 836         hwdep->exclusive = true;
 837
 838         return 0;
 839 }
 840
 841 static void dice_card_free(struct snd_card *card)
 842 {
 843         struct dice *dice = card->private_data;
 844
 845         amdtp_out_stream_destroy(&dice->stream);
 846         fw_core_remove_address_handler(&dice->notification_handler);
 847         mutex_destroy(&dice->mutex);
 848 }
 849
 850 static int dice_init_offsets(struct dice *dice)
 851 {
 852         __be32 pointers[6];
 853         unsigned int global_size, rx_size;
 854         int err;
 855
 856         err = snd_fw_transaction(dice->unit, TCODE_READ_BLOCK_REQUEST,
 857                                  DICE_PRIVATE_SPACE, &pointers, 6 * 4);
 858         if (err < 0)
 859                 return err;
 860
 861         dice->global_offset = be32_to_cpu(pointers[0]) * 4;
 862         global_size = be32_to_cpu(pointers[1]);
 863         dice->rx_offset = be32_to_cpu(pointers[4]) * 4;
 864         rx_size = be32_to_cpu(pointers[5]);
 865
 866         /* some sanity checks to ensure that we actually have a DICE */
 867         if (dice->global_offset < 10 * 4 || global_size < 0x168 / 4 ||
 868             dice->rx_offset < 10 * 4 || rx_size < 0x120 / 4) {
 869                 dev_err(&dice->unit->device, "invalid register pointers\n");
 870                 return -ENXIO;
 871         }
 872
 873         return 0;
 874 }
 875
 876 static void dice_card_strings(struct dice *dice)
 877 {
 878         struct snd_card *card = dice->card;
 879         struct fw_device *dev = fw_parent_device(dice->unit);
 880         char vendor[32], model[32];
 881         unsigned int i;
 882         int err;
 883
 884         strcpy(card->driver, "DICE");
 885
 886         strcpy(card->shortname, "DICE");
 887         BUILD_BUG_ON(NICK_NAME_SIZE < sizeof(card->shortname));
 888         err = snd_fw_transaction(dice->unit, TCODE_READ_BLOCK_REQUEST,
 889                                  global_address(dice, GLOBAL_NICK_NAME),
 890                                  card->shortname, sizeof(card->shortname));
 891         if (err >= 0) {
 892                 /* DICE strings are returned in "always-wrong" endianness */
 893                 BUILD_BUG_ON(sizeof(card->shortname) % 4 != 0);
 894                 for (i = 0; i < sizeof(card->shortname); i += 4)
 895                         swab32s((u32 *)&card->shortname[i]);
 896                 card->shortname[sizeof(card->shortname) - 1] = '\0';
 897         }
 898
 899         strcpy(vendor, "?");
 900         fw_csr_string(dev->config_rom + 5, CSR_VENDOR, vendor, sizeof(vendor));
 901         strcpy(model, "?");
 902         fw_csr_string(dice->unit->directory, CSR_MODEL, model, sizeof(model));
 903         snprintf(card->longname, sizeof(card->longname),
 904                  "%s %s, GUID %08x%08x at %s, S%d",
 905                  vendor, model, dev->config_rom[3], dev->config_rom[4],
 906                  dev_name(&dice->unit->device), 100 << dev->max_speed);
 907
 908         strcpy(card->mixername, "DICE");
 909 }
 910
 911 static int dice_probe(struct fw_unit *unit, const struct ieee1394_device_id *id)
 912 {
 913         struct snd_card *card;
 914         struct dice *dice;
 915         __be32 clock_sel;
 916         int err;
 917
 918         err = snd_card_create(-1, NULL, THIS_MODULE, sizeof(*dice), &card);
 919         if (err < 0)
 920                 return err;
 921         snd_card_set_dev(card, &unit->device);
 922
 923         dice = card->private_data;
 924         dice->card = card;
 925         mutex_init(&dice->mutex);
 926         dice->unit = unit;
 927
 928         err = dice_init_offsets(dice);
 929         if (err < 0)
 930                 goto err_mutex;
 931
 932         dice->notification_handler.length = 4;
 933         dice->notification_handler.address_callback = dice_notification;
 934         dice->notification_handler.callback_data = dice;
 935         err = fw_core_add_address_handler(&dice->notification_handler,
 936                                           &fw_high_memory_region);
 937         if (err < 0)
 938                 goto err_mutex;
 939
 940         err = fw_iso_resources_init(&dice->resources, unit);
 941         if (err < 0)
 942                 goto err_notification_handler;
 943         dice->resources.channels_mask = 0x00000000ffffffffuLL;
 944
 945         err = amdtp_out_stream_init(&dice->stream, unit, CIP_BLOCKING);
 946         if (err < 0)
 947                 goto err_resources;
 948
 949         err = dice_owner_set(dice);
 950         if (err < 0)
 951                 goto err_stream;
 952
 953         card->private_free = dice_card_free;
 954
 955         dice_card_strings(dice);
 956
 957         err = snd_fw_transaction(unit, TCODE_READ_QUADLET_REQUEST,
 958                                  global_address(dice, GLOBAL_CLOCK_SELECT),
 959                                  &clock_sel, 4);
 960         if (err < 0)
 961                 goto error;
 962         clock_sel &= cpu_to_be32(~CLOCK_SOURCE_MASK);
 963         clock_sel |= cpu_to_be32(CLOCK_SOURCE_ARX1);
 964         err = snd_fw_transaction(unit, TCODE_WRITE_QUADLET_REQUEST,
 965                                  global_address(dice, GLOBAL_CLOCK_SELECT),
 966                                  &clock_sel, 4);
 967         if (err < 0)
 968                 goto error;
 969
 970         err = dice_create_pcm(dice);
 971         if (err < 0)
 972                 goto error;
 973
 974         err = dice_create_hwdep(dice);
 975         if (err < 0)
 976                 goto error;
 977
 978         err = snd_card_register(card);
 979         if (err < 0)
 980                 goto error;
 981
 982         dev_set_drvdata(&unit->device, dice);
 983
 984         return 0;
 985
 986 err_stream:
 987         amdtp_out_stream_destroy(&dice->stream);
 988 err_resources:
 989         fw_iso_resources_destroy(&dice->resources);
 990 err_notification_handler:
 991         fw_core_remove_address_handler(&dice->notification_handler);
 992 err_mutex:
 993         mutex_destroy(&dice->mutex);
 994 error:
 995         snd_card_free(card);
 996         return err;
 997 }
 998
 999 static void dice_remove(struct fw_unit *unit)
1000 {
1001         struct dice *dice = dev_get_drvdata(&unit->device);
1002
1003         mutex_lock(&dice->mutex);
1004
1005         amdtp_out_stream_pcm_abort(&dice->stream);
1006
1007         snd_card_disconnect(dice->card);
1008
1009         dice_stream_stop(dice);
1010         dice_owner_clear(dice);
1011
1012         mutex_unlock(&dice->mutex);
1013
1014         snd_card_free_when_closed(dice->card);
1015 }
1016
1017 static void dice_bus_reset(struct fw_unit *unit)
1018 {
1019         struct dice *dice = dev_get_drvdata(&unit->device);
1020
1021         mutex_lock(&dice->mutex);
1022
1023         /*
1024          * On a bus reset, the DICE firmware disables streaming and then goes
1025          * off contemplating its own navel for hundreds of milliseconds before
1026          * it can react to any of our attempts to reenable streaming.  This
1027          * means that we lose synchronization anyway, so we force our streams
1028          * to stop so that the application can restart them in an orderly
1029          * manner.
1030          */
1031         amdtp_out_stream_pcm_abort(&dice->stream);
1032         dice_stream_stop_packets(dice);
1033
1034         dice_owner_update(dice);
1035
1036         fw_iso_resources_update(&dice->resources);
1037
1038         mutex_unlock(&dice->mutex);
1039 }
1040
1041 #define TC_OUI          0x000166
1042 #define DICE_INTERFACE  0x000001
1043
1044 static const struct ieee1394_device_id dice_id_table[] = {
1045         {
1046                 .match_flags  = IEEE1394_MATCH_SPECIFIER_ID |
1047                                 IEEE1394_MATCH_VERSION,
1048                 .specifier_id = TC_OUI,
1049                 .version      = DICE_INTERFACE,
1050         },
1051         { }
1052 };
1053 MODULE_DEVICE_TABLE(ieee1394, dice_id_table);
1054
1055 static struct fw_driver dice_driver = {
1056         .driver   = {
1057                 .owner  = THIS_MODULE,
1058                 .name   = KBUILD_MODNAME,
1059                 .bus    = &fw_bus_type,
1060         },
1061         .probe    = dice_probe,
1062         .update   = dice_bus_reset,
1063         .remove   = dice_remove,
1064         .id_table = dice_id_table,
1065 };
1066
1067 static int __init alsa_dice_init(void)
1068 {
1069         return driver_register(&dice_driver.driver);
1070 }
1071
1072 static void __exit alsa_dice_exit(void)
1073 {
1074         driver_unregister(&dice_driver.driver);
1075 }
1076
1077 module_init(alsa_dice_init);
1078 module_exit(alsa_dice_exit);