2 * Based on sound/arm/pxa2xx-ac97.c and sound/soc/pxa/pxa2xx-ac97.c
5 * Author: Nicolas Pitre
6 * Created: Dec 02, 2004
7 * Copyright: MontaVista Software Inc.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/kernel.h>
15 #include <linux/platform_device.h>
16 #include <linux/interrupt.h>
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/module.h>
21 #include <sound/ac97_codec.h>
22 #include <sound/pxa2xx-lib.h>
25 #include <mach/regs-ac97.h>
26 #include <mach/audio.h>
28 static DEFINE_MUTEX(car_mutex);
29 static DECLARE_WAIT_QUEUE_HEAD(gsr_wq);
30 static volatile long gsr_bits;
31 static struct clk *ac97_clk;
32 static struct clk *ac97conf_clk;
33 static int reset_gpio;
35 extern void pxa27x_assert_ac97reset(int reset_gpio, int on);
40 * o Slot 12 read from modem space will hang controller.
41 * o CDONE, SDONE interrupt fails after any slot 12 IO.
43 * We therefore have an hybrid approach for waiting on SDONE (interrupt or
44 * 1 jiffy timeout if interrupt never comes).
47 unsigned short pxa2xx_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
49 unsigned short val = -1;
50 volatile u32 *reg_addr;
52 mutex_lock(&car_mutex);
54 /* set up primary or secondary codec space */
55 if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS)
56 reg_addr = ac97->num ? &SMC_REG_BASE : &PMC_REG_BASE;
58 reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE;
59 reg_addr += (reg >> 1);
61 /* start read access across the ac97 link */
62 GSR = GSR_CDONE | GSR_SDONE;
65 if (reg == AC97_GPIO_STATUS)
67 if (wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1) <= 0 &&
68 !((GSR | gsr_bits) & GSR_SDONE)) {
69 printk(KERN_ERR "%s: read error (ac97_reg=%d GSR=%#lx)\n",
70 __func__, reg, GSR | gsr_bits);
76 GSR = GSR_CDONE | GSR_SDONE;
79 /* but we've just started another cycle... */
80 wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1);
82 out: mutex_unlock(&car_mutex);
85 EXPORT_SYMBOL_GPL(pxa2xx_ac97_read);
87 void pxa2xx_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
90 volatile u32 *reg_addr;
92 mutex_lock(&car_mutex);
94 /* set up primary or secondary codec space */
95 if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS)
96 reg_addr = ac97->num ? &SMC_REG_BASE : &PMC_REG_BASE;
98 reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE;
99 reg_addr += (reg >> 1);
101 GSR = GSR_CDONE | GSR_SDONE;
104 if (wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_CDONE, 1) <= 0 &&
105 !((GSR | gsr_bits) & GSR_CDONE))
106 printk(KERN_ERR "%s: write error (ac97_reg=%d GSR=%#lx)\n",
107 __func__, reg, GSR | gsr_bits);
109 mutex_unlock(&car_mutex);
111 EXPORT_SYMBOL_GPL(pxa2xx_ac97_write);
114 static inline void pxa_ac97_warm_pxa25x(void)
118 GCR |= GCR_WARM_RST | GCR_PRIRDY_IEN | GCR_SECRDY_IEN;
119 wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR | GSR_SCR), 1);
122 static inline void pxa_ac97_cold_pxa25x(void)
124 GCR &= GCR_COLD_RST; /* clear everything but nCRST */
125 GCR &= ~GCR_COLD_RST; /* then assert nCRST */
130 GCR |= GCR_CDONE_IE|GCR_SDONE_IE;
131 wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR | GSR_SCR), 1);
136 static inline void pxa_ac97_warm_pxa27x(void)
140 /* warm reset broken on Bulverde, so manually keep AC97 reset high */
141 pxa27x_assert_ac97reset(reset_gpio, 1);
144 pxa27x_assert_ac97reset(reset_gpio, 0);
148 static inline void pxa_ac97_cold_pxa27x(void)
150 GCR &= GCR_COLD_RST; /* clear everything but nCRST */
151 GCR &= ~GCR_COLD_RST; /* then assert nCRST */
155 /* PXA27x Developers Manual section 13.5.2.2.1 */
156 clk_enable(ac97conf_clk);
158 clk_disable(ac97conf_clk);
165 static inline void pxa_ac97_warm_pxa3xx(void)
171 /* Can't use interrupts */
173 while (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR)) && timeout--)
177 static inline void pxa_ac97_cold_pxa3xx(void)
181 /* Hold CLKBPB for 100us */
187 GCR &= GCR_COLD_RST; /* clear everything but nCRST */
188 GCR &= ~GCR_COLD_RST; /* then assert nCRST */
192 /* Can't use interrupts on PXA3xx */
193 GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);
195 GCR = GCR_WARM_RST | GCR_COLD_RST;
196 while (!(GSR & (GSR_PCR | GSR_SCR)) && timeout--)
201 bool pxa2xx_ac97_try_warm_reset(struct snd_ac97 *ac97)
207 pxa_ac97_warm_pxa25x();
212 pxa_ac97_warm_pxa27x();
217 pxa_ac97_warm_pxa3xx();
221 gsr = GSR | gsr_bits;
222 if (!(gsr & (GSR_PCR | GSR_SCR))) {
223 printk(KERN_INFO "%s: warm reset timeout (GSR=%#lx)\n",
231 EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_warm_reset);
233 bool pxa2xx_ac97_try_cold_reset(struct snd_ac97 *ac97)
239 pxa_ac97_cold_pxa25x();
244 pxa_ac97_cold_pxa27x();
249 pxa_ac97_cold_pxa3xx();
254 gsr = GSR | gsr_bits;
255 if (!(gsr & (GSR_PCR | GSR_SCR))) {
256 printk(KERN_INFO "%s: cold reset timeout (GSR=%#lx)\n",
264 EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_cold_reset);
267 void pxa2xx_ac97_finish_reset(struct snd_ac97 *ac97)
269 GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);
270 GCR |= GCR_SDONE_IE|GCR_CDONE_IE;
272 EXPORT_SYMBOL_GPL(pxa2xx_ac97_finish_reset);
274 static irqreturn_t pxa2xx_ac97_irq(int irq, void *dev_id)
284 /* Although we don't use those we still need to clear them
285 since they tend to spuriously trigger when MMC is used
286 (hardware bug? go figure)... */
287 if (cpu_is_pxa27x()) {
300 int pxa2xx_ac97_hw_suspend(void)
302 GCR |= GCR_ACLINK_OFF;
303 clk_disable(ac97_clk);
306 EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_suspend);
308 int pxa2xx_ac97_hw_resume(void)
310 clk_enable(ac97_clk);
313 EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_resume);
316 int __devinit pxa2xx_ac97_hw_probe(struct platform_device *dev)
319 pxa2xx_audio_ops_t *pdata = dev->dev.platform_data;
322 switch (pdata->reset_gpio) {
325 reset_gpio = pdata->reset_gpio;
333 dev_err(&dev->dev, "Invalid reset GPIO %d\n",
341 if (cpu_is_pxa27x()) {
342 /* Use GPIO 113 as AC97 Reset on Bulverde */
343 pxa27x_assert_ac97reset(reset_gpio, 0);
344 ac97conf_clk = clk_get(&dev->dev, "AC97CONFCLK");
345 if (IS_ERR(ac97conf_clk)) {
346 ret = PTR_ERR(ac97conf_clk);
352 ac97_clk = clk_get(&dev->dev, "AC97CLK");
353 if (IS_ERR(ac97_clk)) {
354 ret = PTR_ERR(ac97_clk);
359 ret = clk_enable(ac97_clk);
363 ret = request_irq(IRQ_AC97, pxa2xx_ac97_irq, 0, "AC97", NULL);
370 GCR |= GCR_ACLINK_OFF;
376 clk_put(ac97conf_clk);
382 EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_probe);
384 void pxa2xx_ac97_hw_remove(struct platform_device *dev)
386 GCR |= GCR_ACLINK_OFF;
387 free_irq(IRQ_AC97, NULL);
389 clk_put(ac97conf_clk);
392 clk_disable(ac97_clk);
396 EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_remove);
398 MODULE_AUTHOR("Nicolas Pitre");
399 MODULE_DESCRIPTION("Intel/Marvell PXA sound library");
400 MODULE_LICENSE("GPL");