2 * Library implementing the most common irq chip callback functions
4 * Copyright (C) 2011, Thomas Gleixner
8 #include <linux/slab.h>
9 #include <linux/interrupt.h>
10 #include <linux/kernel_stat.h>
11 #include <linux/syscore_ops.h>
13 #include "internals.h"
15 static LIST_HEAD(gc_list);
16 static DEFINE_RAW_SPINLOCK(gc_lock);
18 static inline struct irq_chip_regs *cur_regs(struct irq_data *d)
20 return &container_of(d->chip, struct irq_chip_type, chip)->regs;
24 * irq_gc_noop - NOOP function
27 void irq_gc_noop(struct irq_data *d)
32 * irq_gc_mask_disable_reg - Mask chip via disable register
35 * Chip has separate enable/disable registers instead of a single mask
38 void irq_gc_mask_disable_reg(struct irq_data *d)
40 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
41 u32 mask = 1 << (d->irq - gc->irq_base);
44 irq_reg_writel(mask, gc->reg_base + cur_regs(d)->disable);
45 gc->mask_cache &= ~mask;
50 * irq_gc_mask_set_mask_bit - Mask chip via setting bit in mask register
53 * Chip has a single mask register. Values of this register are cached
54 * and protected by gc->lock
56 void irq_gc_mask_set_bit(struct irq_data *d)
58 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
59 u32 mask = 1 << (d->irq - gc->irq_base);
62 gc->mask_cache |= mask;
63 irq_reg_writel(gc->mask_cache, gc->reg_base + cur_regs(d)->mask);
68 * irq_gc_mask_set_mask_bit - Mask chip via clearing bit in mask register
71 * Chip has a single mask register. Values of this register are cached
72 * and protected by gc->lock
74 void irq_gc_mask_clr_bit(struct irq_data *d)
76 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
77 u32 mask = 1 << (d->irq - gc->irq_base);
80 gc->mask_cache &= ~mask;
81 irq_reg_writel(gc->mask_cache, gc->reg_base + cur_regs(d)->mask);
86 * irq_gc_unmask_enable_reg - Unmask chip via enable register
89 * Chip has separate enable/disable registers instead of a single mask
92 void irq_gc_unmask_enable_reg(struct irq_data *d)
94 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
95 u32 mask = 1 << (d->irq - gc->irq_base);
98 irq_reg_writel(mask, gc->reg_base + cur_regs(d)->enable);
99 gc->mask_cache |= mask;
104 * irq_gc_ack_set_bit - Ack pending interrupt via setting bit
107 void irq_gc_ack_set_bit(struct irq_data *d)
109 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
110 u32 mask = 1 << (d->irq - gc->irq_base);
113 irq_reg_writel(mask, gc->reg_base + cur_regs(d)->ack);
118 * irq_gc_ack_clr_bit - Ack pending interrupt via clearing bit
121 void irq_gc_ack_clr_bit(struct irq_data *d)
123 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
124 u32 mask = ~(1 << (d->irq - gc->irq_base));
127 irq_reg_writel(mask, gc->reg_base + cur_regs(d)->ack);
132 * irq_gc_mask_disable_reg_and_ack- Mask and ack pending interrupt
135 void irq_gc_mask_disable_reg_and_ack(struct irq_data *d)
137 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
138 u32 mask = 1 << (d->irq - gc->irq_base);
141 irq_reg_writel(mask, gc->reg_base + cur_regs(d)->mask);
142 irq_reg_writel(mask, gc->reg_base + cur_regs(d)->ack);
147 * irq_gc_eoi - EOI interrupt
150 void irq_gc_eoi(struct irq_data *d)
152 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
153 u32 mask = 1 << (d->irq - gc->irq_base);
156 irq_reg_writel(mask, gc->reg_base + cur_regs(d)->eoi);
161 * irq_gc_set_wake - Set/clr wake bit for an interrupt
164 * For chips where the wake from suspend functionality is not
165 * configured in a separate register and the wakeup active state is
166 * just stored in a bitmask.
168 int irq_gc_set_wake(struct irq_data *d, unsigned int on)
170 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
171 u32 mask = 1 << (d->irq - gc->irq_base);
173 if (!(mask & gc->wake_enabled))
178 gc->wake_active |= mask;
180 gc->wake_active &= ~mask;
186 * irq_alloc_generic_chip - Allocate a generic chip and initialize it
187 * @name: Name of the irq chip
188 * @num_ct: Number of irq_chip_type instances associated with this
189 * @irq_base: Interrupt base nr for this chip
190 * @reg_base: Register base address (virtual)
191 * @handler: Default flow handler associated with this chip
193 * Returns an initialized irq_chip_generic structure. The chip defaults
194 * to the primary (index 0) irq_chip_type and @handler
196 struct irq_chip_generic *
197 irq_alloc_generic_chip(const char *name, int num_ct, unsigned int irq_base,
198 void __iomem *reg_base, irq_flow_handler_t handler)
200 struct irq_chip_generic *gc;
201 unsigned long sz = sizeof(*gc) + num_ct * sizeof(struct irq_chip_type);
203 gc = kzalloc(sz, GFP_KERNEL);
205 raw_spin_lock_init(&gc->lock);
207 gc->irq_base = irq_base;
208 gc->reg_base = reg_base;
209 gc->chip_types->chip.name = name;
210 gc->chip_types->handler = handler;
216 * Separate lockdep class for interrupt chip which can nest irq_desc
219 static struct lock_class_key irq_nested_lock_class;
222 * irq_setup_generic_chip - Setup a range of interrupts with a generic chip
223 * @gc: Generic irq chip holding all data
224 * @msk: Bitmask holding the irqs to initialize relative to gc->irq_base
225 * @flags: Flags for initialization
226 * @clr: IRQ_* bits to clear
227 * @set: IRQ_* bits to set
229 * Set up max. 32 interrupts starting from gc->irq_base. Note, this
230 * initializes all interrupts to the primary irq_chip_type and its
231 * associated handler.
233 void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk,
234 enum irq_gc_flags flags, unsigned int clr,
237 struct irq_chip_type *ct = gc->chip_types;
240 raw_spin_lock(&gc_lock);
241 list_add_tail(&gc->list, &gc_list);
242 raw_spin_unlock(&gc_lock);
244 /* Init mask cache ? */
245 if (flags & IRQ_GC_INIT_MASK_CACHE)
246 gc->mask_cache = irq_reg_readl(gc->reg_base + ct->regs.mask);
248 for (i = gc->irq_base; msk; msk >>= 1, i++) {
252 if (flags & IRQ_GC_INIT_NESTED_LOCK)
253 irq_set_lockdep_class(i, &irq_nested_lock_class);
255 irq_set_chip_and_handler(i, &ct->chip, ct->handler);
256 irq_set_chip_data(i, gc);
257 irq_modify_status(i, clr, set);
259 gc->irq_cnt = i - gc->irq_base;
263 * irq_setup_alt_chip - Switch to alternative chip
264 * @d: irq_data for this interrupt
265 * @type Flow type to be initialized
267 * Only to be called from chip->irq_set_type() callbacks.
269 int irq_setup_alt_chip(struct irq_data *d, unsigned int type)
271 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
272 struct irq_chip_type *ct = gc->chip_types;
275 for (i = 0; i < gc->num_ct; i++, ct++) {
276 if (ct->type & type) {
278 irq_data_to_desc(d)->handle_irq = ct->handler;
286 * irq_remove_generic_chip - Remove a chip
287 * @gc: Generic irq chip holding all data
288 * @msk: Bitmask holding the irqs to initialize relative to gc->irq_base
289 * @clr: IRQ_* bits to clear
290 * @set: IRQ_* bits to set
292 * Remove up to 32 interrupts starting from gc->irq_base.
294 void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk,
295 unsigned int clr, unsigned int set)
297 unsigned int i = gc->irq_base;
299 raw_spin_lock(&gc_lock);
301 raw_spin_unlock(&gc_lock);
303 for (; msk; msk >>= 1, i++) {
307 /* Remove handler first. That will mask the irq line */
308 irq_set_handler(i, NULL);
309 irq_set_chip(i, &no_irq_chip);
310 irq_set_chip_data(i, NULL);
311 irq_modify_status(i, clr, set);
316 static int irq_gc_suspend(void)
318 struct irq_chip_generic *gc;
320 list_for_each_entry(gc, &gc_list, list) {
321 struct irq_chip_type *ct = gc->chip_types;
323 if (ct->chip.irq_suspend)
324 ct->chip.irq_suspend(irq_get_irq_data(gc->irq_base));
329 static void irq_gc_resume(void)
331 struct irq_chip_generic *gc;
333 list_for_each_entry(gc, &gc_list, list) {
334 struct irq_chip_type *ct = gc->chip_types;
336 if (ct->chip.irq_resume)
337 ct->chip.irq_resume(irq_get_irq_data(gc->irq_base));
341 #define irq_gc_suspend NULL
342 #define irq_gc_resume NULL
345 static void irq_gc_shutdown(void)
347 struct irq_chip_generic *gc;
349 list_for_each_entry(gc, &gc_list, list) {
350 struct irq_chip_type *ct = gc->chip_types;
352 if (ct->chip.irq_pm_shutdown)
353 ct->chip.irq_pm_shutdown(irq_get_irq_data(gc->irq_base));
357 static struct syscore_ops irq_gc_syscore_ops = {
358 .suspend = irq_gc_suspend,
359 .resume = irq_gc_resume,
360 .shutdown = irq_gc_shutdown,
363 static int __init irq_gc_init_ops(void)
365 register_syscore_ops(&irq_gc_syscore_ops);
368 device_initcall(irq_gc_init_ops);