2 * SAS structures and definitions header file
4 * Copyright (C) 2005 Adaptec, Inc. All rights reserved.
5 * Copyright (C) 2005 Luben Tuikov <luben_tuikov@adaptec.com>
7 * This file is licensed under GPLv2.
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
29 #include <linux/types.h>
30 #include <asm/byteorder.h>
32 #define SAS_ADDR_SIZE 8
33 #define HASHED_SAS_ADDR_SIZE 3
34 #define SAS_ADDR(_sa) ((unsigned long long) be64_to_cpu(*(__be64 *)(_sa)))
36 #define SMP_REQUEST 0x40
37 #define SMP_RESPONSE 0x41
40 #define SSP_XFER_RDY 0x05
41 #define SSP_COMMAND 0x06
42 #define SSP_RESPONSE 0x07
45 #define SMP_REPORT_GENERAL 0x00
46 #define SMP_REPORT_MANUF_INFO 0x01
47 #define SMP_READ_GPIO_REG 0x02
48 #define SMP_DISCOVER 0x10
49 #define SMP_REPORT_PHY_ERR_LOG 0x11
50 #define SMP_REPORT_PHY_SATA 0x12
51 #define SMP_REPORT_ROUTE_INFO 0x13
52 #define SMP_WRITE_GPIO_REG 0x82
53 #define SMP_CONF_ROUTE_INFO 0x90
54 #define SMP_PHY_CONTROL 0x91
55 #define SMP_PHY_TEST_FUNCTION 0x92
57 #define SMP_RESP_FUNC_ACC 0x00
58 #define SMP_RESP_FUNC_UNK 0x01
59 #define SMP_RESP_FUNC_FAILED 0x02
60 #define SMP_RESP_INV_FRM_LEN 0x03
61 #define SMP_RESP_NO_PHY 0x10
62 #define SMP_RESP_NO_INDEX 0x11
63 #define SMP_RESP_PHY_NO_SATA 0x12
64 #define SMP_RESP_PHY_UNK_OP 0x13
65 #define SMP_RESP_PHY_UNK_TESTF 0x14
66 #define SMP_RESP_PHY_TEST_INPROG 0x15
67 #define SMP_RESP_PHY_VACANT 0x16
70 #define TMF_ABORT_TASK 0x01
71 #define TMF_ABORT_TASK_SET 0x02
72 #define TMF_CLEAR_TASK_SET 0x04
73 #define TMF_LU_RESET 0x08
74 #define TMF_CLEAR_ACA 0x40
75 #define TMF_QUERY_TASK 0x80
77 /* SAS TMF responses */
78 #define TMF_RESP_FUNC_COMPLETE 0x00
79 #define TMF_RESP_INVALID_FRAME 0x02
80 #define TMF_RESP_FUNC_ESUPP 0x04
81 #define TMF_RESP_FUNC_FAILED 0x05
82 #define TMF_RESP_FUNC_SUCC 0x08
83 #define TMF_RESP_NO_LUN 0x09
84 #define TMF_RESP_OVERLAPPED_TAG 0x0A
92 /* See sas_discover.c if you plan on changing these.
95 NO_DEVICE = 0, /* protocol */
96 SAS_END_DEV = 1, /* protocol */
97 EDGE_DEV = 2, /* protocol */
98 FANOUT_DEV = 3, /* protocol */
106 SAS_PROTOCOL_SATA = 0x01,
107 SAS_PROTOCOL_SMP = 0x02,
108 SAS_PROTOCOL_STP = 0x04,
109 SAS_PROTOCOL_SSP = 0x08,
110 SAS_PROTOCOL_ALL = 0x0E,
111 SAS_PROTOCOL_STP_ALL = SAS_PROTOCOL_STP|SAS_PROTOCOL_SATA,
114 /* From the spec; local phys only */
117 PHY_FUNC_LINK_RESET, /* Enables the phy */
120 PHY_FUNC_CLEAR_ERROR_LOG = 5,
121 PHY_FUNC_CLEAR_AFFIL,
122 PHY_FUNC_TX_SATA_PS_SIGNAL,
123 PHY_FUNC_RELEASE_SPINUP_HOLD = 0x10, /* LOCAL PORT ONLY! */
124 PHY_FUNC_SET_LINK_RATE,
128 /* SAS LLDD would need to report only _very_few_ of those, like BROADCAST.
129 * Most of those are here for completeness.
132 SAS_PRIM_AIP_NORMAL = 1,
139 SAS_PRIM_AIP_RWP = 8,
142 SAS_PRIM_BC_RCH0 = 10,
143 SAS_PRIM_BC_RCH1 = 11,
150 SAS_PRIM_NOTIFY_ENSP= 17,
151 SAS_PRIM_NOTIFY_R0 = 18,
152 SAS_PRIM_NOTIFY_R1 = 19,
153 SAS_PRIM_NOTIFY_R2 = 20,
155 SAS_PRIM_CLOSE_CLAF = 21,
156 SAS_PRIM_CLOSE_NORM = 22,
157 SAS_PRIM_CLOSE_R0 = 23,
158 SAS_PRIM_CLOSE_R1 = 24,
160 SAS_PRIM_OPEN_RTRY = 25,
161 SAS_PRIM_OPEN_RJCT = 26,
162 SAS_PRIM_OPEN_ACPT = 27,
168 SATA_PRIM_PMNAK = 34,
169 SATA_PRIM_PMACK = 35,
170 SATA_PRIM_PMREQ_S = 36,
171 SATA_PRIM_PMREQ_P = 37,
172 SATA_SATA_R_ERR = 38,
175 enum sas_open_rej_reason {
177 SAS_OREJ_UNKNOWN = 0,
178 SAS_OREJ_BAD_DEST = 1,
179 SAS_OREJ_CONN_RATE = 2,
181 SAS_OREJ_RESV_AB0 = 4,
182 SAS_OREJ_RESV_AB1 = 5,
183 SAS_OREJ_RESV_AB2 = 6,
184 SAS_OREJ_RESV_AB3 = 7,
185 SAS_OREJ_WRONG_DEST= 8,
186 SAS_OREJ_STP_NORES = 9,
189 SAS_OREJ_NO_DEST = 10,
190 SAS_OREJ_PATH_BLOCKED = 11,
191 SAS_OREJ_RSVD_CONT0 = 12,
192 SAS_OREJ_RSVD_CONT1 = 13,
193 SAS_OREJ_RSVD_INIT0 = 14,
194 SAS_OREJ_RSVD_INIT1 = 15,
195 SAS_OREJ_RSVD_STOP0 = 16,
196 SAS_OREJ_RSVD_STOP1 = 17,
197 SAS_OREJ_RSVD_RETRY = 18,
200 enum sas_gpio_reg_type {
201 SAS_GPIO_REG_CFG = 0,
203 SAS_GPIO_REG_RX_GP = 2,
205 SAS_GPIO_REG_TX_GP = 4,
208 struct dev_to_host_fis {
209 u8 fis_type; /* 0x34 */
215 union { u8 lbam; u8 byte_count_low; };
216 union { u8 lbah; u8 byte_count_high; };
224 union { u8 sector_count; u8 interrupt_reason; };
230 } __attribute__ ((packed));
232 struct host_to_dev_fis {
233 u8 fis_type; /* 0x27 */
239 union { u8 lbam; u8 byte_count_low; };
240 union { u8 lbah; u8 byte_count_high; };
248 union { u8 sector_count; u8 interrupt_reason; };
254 } __attribute__ ((packed));
256 /* Prefer to have code clarity over header file clarity.
258 #ifdef __LITTLE_ENDIAN_BITFIELD
259 struct sas_identify_frame {
296 u8 sas_addr[SAS_ADDR_SIZE];
304 } __attribute__ ((packed));
306 struct ssp_frame_hdr {
308 u8 hashed_dest_addr[HASHED_SAS_ADDR_SIZE];
310 u8 hashed_src_addr[HASHED_SAS_ADDR_SIZE];
313 u8 changing_data_ptr:1;
315 u8 retry_data_frames:1;
325 } __attribute__ ((packed));
327 struct ssp_response_iu {
337 __be32 sense_data_len;
338 __be32 response_data_len;
342 } __attribute__ ((packed));
344 /* ---------- SMP ---------- */
346 struct report_general_resp {
348 __be16 route_indexes;
352 u8 conf_route_table:1;
355 u8 orej_retry_supp:1;
363 u8 enclosure_logical_id[8];
366 } __attribute__ ((packed));
368 struct discover_resp {
375 u8 attached_dev_type:3;
381 u8 attached_sata_host:1;
385 u8 attached_sata_dev:1;
388 u8 attached_sata_ps:1;
391 u8 attached_sas_addr[8];
415 } __attribute__ ((packed));
417 struct report_phy_sata_resp {
431 struct dev_to_host_fis fis;
435 u8 affil_stp_ini_addr[8];
438 } __attribute__ ((packed));
446 struct report_general_resp rg;
447 struct discover_resp disc;
448 struct report_phy_sata_resp rps;
450 } __attribute__ ((packed));
452 #elif defined(__BIG_ENDIAN_BITFIELD)
453 struct sas_identify_frame {
490 u8 sas_addr[SAS_ADDR_SIZE];
498 } __attribute__ ((packed));
500 struct ssp_frame_hdr {
502 u8 hashed_dest_addr[HASHED_SAS_ADDR_SIZE];
504 u8 hashed_src_addr[HASHED_SAS_ADDR_SIZE];
508 u8 retry_data_frames:1;
510 u8 changing_data_ptr:1;
519 } __attribute__ ((packed));
521 struct ssp_response_iu {
531 __be32 sense_data_len;
532 __be32 response_data_len;
536 } __attribute__ ((packed));
538 /* ---------- SMP ---------- */
540 struct report_general_resp {
542 __be16 route_indexes;
550 u8 orej_retry_supp:1;
553 u8 conf_route_table:1;
557 u8 enclosure_logical_id[8];
560 } __attribute__ ((packed));
562 struct discover_resp {
569 u8 attached_dev_type:3;
577 u8 attached_sata_host:1;
579 u8 attached_sata_ps:1;
582 u8 attached_sata_dev:1;
585 u8 attached_sas_addr[8];
609 } __attribute__ ((packed));
611 struct report_phy_sata_resp {
625 struct dev_to_host_fis fis;
629 u8 affil_stp_ini_addr[8];
632 } __attribute__ ((packed));
640 struct report_general_resp rg;
641 struct discover_resp disc;
642 struct report_phy_sata_resp rps;
644 } __attribute__ ((packed));
647 #error "Bitfield order not defined!"