4 * TI OMAP3 ISP - Platform data
6 * Copyright (C) 2011 Nokia Corporation
8 * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
9 * Sakari Ailus <sakari.ailus@iki.fi>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
26 #ifndef __MEDIA_OMAP3ISP_H__
27 #define __MEDIA_OMAP3ISP_H__
29 struct i2c_board_info;
32 enum isp_interface_type {
33 ISP_INTERFACE_PARALLEL,
34 ISP_INTERFACE_CSI2A_PHY2,
35 ISP_INTERFACE_CCP2B_PHY1,
36 ISP_INTERFACE_CCP2B_PHY2,
37 ISP_INTERFACE_CSI2C_PHY1,
41 ISP_BRIDGE_DISABLE = 0,
42 ISP_BRIDGE_LITTLE_ENDIAN = 2,
43 ISP_BRIDGE_BIG_ENDIAN = 3,
54 * struct isp_parallel_platform_data - Parallel interface platform data
55 * @data_lane_shift: Data lane shifter
56 * ISP_LANE_SHIFT_0 - CAMEXT[13:0] -> CAM[13:0]
57 * ISP_LANE_SHIFT_2 - CAMEXT[13:2] -> CAM[11:0]
58 * ISP_LANE_SHIFT_4 - CAMEXT[13:4] -> CAM[9:0]
59 * ISP_LANE_SHIFT_6 - CAMEXT[13:6] -> CAM[7:0]
60 * @clk_pol: Pixel clock polarity
61 * 0 - Non Inverted, 1 - Inverted
62 * @hs_pol: Horizontal synchronization polarity
63 * 0 - Active high, 1 - Active low
64 * @vs_pol: Vertical synchronization polarity
65 * 0 - Active high, 1 - Active low
66 * @bridge: CCDC Bridge input control
67 * ISP_BRIDGE_DISABLE - Disable
68 * ISP_BRIDGE_LITTLE_ENDIAN - Little endian
69 * ISP_BRIDGE_BIG_ENDIAN - Big endian
71 struct isp_parallel_platform_data {
72 unsigned int data_lane_shift:2;
73 unsigned int clk_pol:1;
74 unsigned int hs_pol:1;
75 unsigned int vs_pol:1;
76 unsigned int bridge:2;
80 ISP_CCP2_PHY_DATA_CLOCK = 0,
81 ISP_CCP2_PHY_DATA_STROBE = 1,
85 ISP_CCP2_MODE_MIPI = 0,
86 ISP_CCP2_MODE_CCP2 = 1,
90 * struct isp_ccp2_platform_data - CCP2 interface platform data
91 * @strobe_clk_pol: Strobe/clock polarity
92 * 0 - Non Inverted, 1 - Inverted
93 * @crc: Enable the cyclic redundancy check
94 * @ccp2_mode: Enable CCP2 compatibility mode
95 * ISP_CCP2_MODE_MIPI - MIPI-CSI1 mode
96 * ISP_CCP2_MODE_CCP2 - CCP2 mode
97 * @phy_layer: Physical layer selection
98 * ISP_CCP2_PHY_DATA_CLOCK - Data/clock physical layer
99 * ISP_CCP2_PHY_DATA_STROBE - Data/strobe physical layer
100 * @vpclk_div: Video port output clock control
102 struct isp_ccp2_platform_data {
103 unsigned int strobe_clk_pol:1;
105 unsigned int ccp2_mode:1;
106 unsigned int phy_layer:1;
107 unsigned int vpclk_div:2;
111 * struct isp_csi2_platform_data - CSI2 interface platform data
112 * @crc: Enable the cyclic redundancy check
113 * @vpclk_div: Video port output clock control
115 struct isp_csi2_platform_data {
117 unsigned vpclk_div:2;
120 struct isp_subdev_i2c_board_info {
121 struct i2c_board_info *board_info;
125 struct isp_v4l2_subdevs_group {
126 struct isp_subdev_i2c_board_info *subdevs;
127 enum isp_interface_type interface;
129 struct isp_parallel_platform_data parallel;
130 struct isp_ccp2_platform_data ccp2;
131 struct isp_csi2_platform_data csi2;
132 } bus; /* gcc < 4.6.0 chokes on anonymous union initializers */
135 struct isp_platform_data {
136 struct isp_v4l2_subdevs_group *subdevs;
137 void (*set_constraints)(struct isp_device *isp, bool enable);
140 #endif /* __MEDIA_OMAP3ISP_H__ */