1 #ifndef DW_SPI_HEADER_H
2 #define DW_SPI_HEADER_H
5 /* Bit fields in CTRLR0 */
6 #define SPI_DFS_OFFSET 0
8 #define SPI_FRF_OFFSET 4
9 #define SPI_FRF_SPI 0x0
10 #define SPI_FRF_SSP 0x1
11 #define SPI_FRF_MICROWIRE 0x2
12 #define SPI_FRF_RESV 0x3
14 #define SPI_MODE_OFFSET 6
15 #define SPI_SCPH_OFFSET 6
16 #define SPI_SCOL_OFFSET 7
18 #define SPI_TMOD_OFFSET 8
19 #define SPI_TMOD_MASK (0x3 << SPI_TMOD_OFFSET)
20 #define SPI_TMOD_TR 0x0 /* xmit & recv */
21 #define SPI_TMOD_TO 0x1 /* xmit only */
22 #define SPI_TMOD_RO 0x2 /* recv only */
23 #define SPI_TMOD_EPROMREAD 0x3 /* eeprom read mode */
25 #define SPI_SLVOE_OFFSET 10
26 #define SPI_SRL_OFFSET 11
27 #define SPI_CFS_OFFSET 12
29 /* Bit fields in SR, 7 bits */
30 #define SR_MASK 0x7f /* cover 7 bits */
31 #define SR_BUSY (1 << 0)
32 #define SR_TF_NOT_FULL (1 << 1)
33 #define SR_TF_EMPT (1 << 2)
34 #define SR_RF_NOT_EMPT (1 << 3)
35 #define SR_RF_FULL (1 << 4)
36 #define SR_TX_ERR (1 << 5)
37 #define SR_DCOL (1 << 6)
39 /* Bit fields in ISR, IMR, RISR, 7 bits */
40 #define SPI_INT_TXEI (1 << 0)
41 #define SPI_INT_TXOI (1 << 1)
42 #define SPI_INT_RXUI (1 << 2)
43 #define SPI_INT_RXOI (1 << 3)
44 #define SPI_INT_RXFI (1 << 4)
45 #define SPI_INT_MSTI (1 << 5)
47 /* TX RX interrupt level threshhold, max can be 256 */
48 #define SPI_INT_THRESHOLD 32
81 u32 dr; /* Currently oper as 32 bits,
82 though only low 16 bits matters */
86 struct spi_master *master;
87 struct spi_device *cur_dev;
88 struct device *parent_dev;
89 enum dw_ssi_type type;
95 u32 fifo_len; /* depth of the FIFO buffer */
96 u32 max_freq; /* max bus freq supported */
99 u16 num_cs; /* supported slave numbers */
101 /* Driver message queue */
102 struct workqueue_struct *workqueue;
103 struct work_struct pump_messages;
105 struct list_head queue;
109 /* Message Transfer pump */
110 struct tasklet_struct pump_transfers;
112 /* Current message transfer state info */
113 struct spi_message *cur_msg;
114 struct spi_transfer *cur_transfer;
115 struct chip_data *cur_chip;
116 struct chip_data *prev_chip;
127 u8 n_bytes; /* current is a 1/2 bytes op */
128 u8 max_bits_per_word; /* maxim is 16b */
131 int (*write)(struct dw_spi *dws);
132 int (*read)(struct dw_spi *dws);
133 irqreturn_t (*transfer_handler)(struct dw_spi *dws);
134 void (*cs_control)(u32 command);
138 struct dma_chan *txchan;
139 struct dma_chan *rxchan;
144 struct device *dma_dev;
147 /* Bus interface info */
149 #ifdef CONFIG_DEBUG_FS
150 struct dentry *debugfs;
154 #define dw_readl(dw, name) \
155 __raw_readl(&(((struct dw_spi_reg *)dw->regs)->name))
156 #define dw_writel(dw, name, val) \
157 __raw_writel((val), &(((struct dw_spi_reg *)dw->regs)->name))
158 #define dw_readw(dw, name) \
159 __raw_readw(&(((struct dw_spi_reg *)dw->regs)->name))
160 #define dw_writew(dw, name, val) \
161 __raw_writew((val), &(((struct dw_spi_reg *)dw->regs)->name))
163 static inline void spi_enable_chip(struct dw_spi *dws, int enable)
165 dw_writel(dws, ssienr, (enable ? 1 : 0));
168 static inline void spi_set_clk(struct dw_spi *dws, u16 div)
170 dw_writel(dws, baudr, div);
173 static inline void spi_chip_sel(struct dw_spi *dws, u16 cs)
175 if (cs > dws->num_cs)
181 dw_writel(dws, ser, 1 << cs);
184 /* Disable IRQ bits */
185 static inline void spi_mask_intr(struct dw_spi *dws, u32 mask)
189 new_mask = dw_readl(dws, imr) & ~mask;
190 dw_writel(dws, imr, new_mask);
193 /* Enable IRQ bits */
194 static inline void spi_umask_intr(struct dw_spi *dws, u32 mask)
198 new_mask = dw_readl(dws, imr) | mask;
199 dw_writel(dws, imr, new_mask);
203 * Each SPI slave device to work with dw_api controller should
204 * has such a structure claiming its working mode (PIO/DMA etc),
205 * which can be save in the "controller_data" member of the
209 u8 poll_mode; /* 0 for contoller polling mode */
210 u8 type; /* SPI/SSP/Micrwire */
212 void (*cs_control)(u32 command);
215 extern int dw_spi_add_host(struct dw_spi *dws);
216 extern void dw_spi_remove_host(struct dw_spi *dws);
217 extern int dw_spi_suspend_host(struct dw_spi *dws);
218 extern int dw_spi_resume_host(struct dw_spi *dws);
219 #endif /* DW_SPI_HEADER_H */