2 * include/linux/serial_reg.h
4 * Copyright (C) 1992, 1994 by Theodore Ts'o.
6 * Redistribution of this file is permitted under the terms of the GNU
9 * These are the UART port assignments, expressed as offsets from the base
10 * register. These assignments should hold for any serial port based on
11 * a 8250, 16450, or 16550(A).
14 #ifndef _LINUX_SERIAL_REG_H
15 #define _LINUX_SERIAL_REG_H
20 #define UART_RX 0 /* In: Receive buffer */
21 #define UART_TX 0 /* Out: Transmit buffer */
23 #define UART_IER 1 /* Out: Interrupt Enable Register */
24 #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
25 #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
26 #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
27 #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
29 * Sleep mode for ST16650 and TI16750. For the ST16650, EFR[4]=1
31 #define UART_IERX_SLEEP 0x10 /* Enable sleep mode */
33 #define UART_IIR 2 /* In: Interrupt ID Register */
34 #define UART_IIR_NO_INT 0x01 /* No interrupts pending */
35 #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
36 #define UART_IIR_MSI 0x00 /* Modem status interrupt */
37 #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
38 #define UART_IIR_RDI 0x04 /* Receiver data interrupt */
39 #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
41 #define UART_IIR_BUSY 0x07 /* DesignWare APB Busy Detect */
43 #define UART_FCR 2 /* Out: FIFO Control Register */
44 #define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */
45 #define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
46 #define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
47 #define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
49 * Note: The FIFO trigger levels are chip specific:
50 * RX:76 = 00 01 10 11 TX:54 = 00 01 10 11
51 * PC16550D: 1 4 8 14 xx xx xx xx
52 * TI16C550A: 1 4 8 14 xx xx xx xx
53 * TI16C550C: 1 4 8 14 xx xx xx xx
54 * ST16C550: 1 4 8 14 xx xx xx xx
55 * ST16C650: 8 16 24 28 16 8 24 30 PORT_16650V2
56 * NS16C552: 1 4 8 14 xx xx xx xx
57 * ST16C654: 8 16 56 60 8 16 32 56 PORT_16654
58 * TI16C750: 1 16 32 56 xx xx xx xx PORT_16750
59 * TI16C752: 8 16 56 60 8 16 32 56
61 #define UART_FCR_R_TRIG_00 0x00
62 #define UART_FCR_R_TRIG_01 0x40
63 #define UART_FCR_R_TRIG_10 0x80
64 #define UART_FCR_R_TRIG_11 0xc0
65 #define UART_FCR_T_TRIG_00 0x00
66 #define UART_FCR_T_TRIG_01 0x10
67 #define UART_FCR_T_TRIG_10 0x20
68 #define UART_FCR_T_TRIG_11 0x30
70 #define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
71 #define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */
72 #define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */
73 #define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */
74 #define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */
75 /* 16650 definitions */
76 #define UART_FCR6_R_TRIGGER_8 0x00 /* Mask for receive trigger set at 1 */
77 #define UART_FCR6_R_TRIGGER_16 0x40 /* Mask for receive trigger set at 4 */
78 #define UART_FCR6_R_TRIGGER_24 0x80 /* Mask for receive trigger set at 8 */
79 #define UART_FCR6_R_TRIGGER_28 0xC0 /* Mask for receive trigger set at 14 */
80 #define UART_FCR6_T_TRIGGER_16 0x00 /* Mask for transmit trigger set at 16 */
81 #define UART_FCR6_T_TRIGGER_8 0x10 /* Mask for transmit trigger set at 8 */
82 #define UART_FCR6_T_TRIGGER_24 0x20 /* Mask for transmit trigger set at 24 */
83 #define UART_FCR6_T_TRIGGER_30 0x30 /* Mask for transmit trigger set at 30 */
84 #define UART_FCR7_64BYTE 0x20 /* Go into 64 byte mode (TI16C750) */
86 #define UART_LCR 3 /* Out: Line Control Register */
88 * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
89 * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
91 #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
92 #define UART_LCR_SBC 0x40 /* Set break control */
93 #define UART_LCR_SPAR 0x20 /* Stick parity (?) */
94 #define UART_LCR_EPAR 0x10 /* Even parity select */
95 #define UART_LCR_PARITY 0x08 /* Parity Enable */
96 #define UART_LCR_STOP 0x04 /* Stop bits: 0=1 bit, 1=2 bits */
97 #define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */
98 #define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */
99 #define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */
100 #define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
103 * Access to some registers depends on register access / configuration
106 #define UART_LCR_CONF_MODE_A UART_LCR_DLAB /* Configutation mode A */
107 #define UART_LCR_CONF_MODE_B 0xBF /* Configutation mode B */
109 #define UART_MCR 4 /* Out: Modem Control Register */
110 #define UART_MCR_CLKSEL 0x80 /* Divide clock by 4 (TI16C752, EFR[4]=1) */
111 #define UART_MCR_TCRTLR 0x40 /* Access TCR/TLR (TI16C752, EFR[4]=1) */
112 #define UART_MCR_XONANY 0x20 /* Enable Xon Any (TI16C752, EFR[4]=1) */
113 #define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS (TI16C550C/TI16C750) */
114 #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
115 #define UART_MCR_OUT2 0x08 /* Out2 complement */
116 #define UART_MCR_OUT1 0x04 /* Out1 complement */
117 #define UART_MCR_RTS 0x02 /* RTS complement */
118 #define UART_MCR_DTR 0x01 /* DTR complement */
120 #define UART_LSR 5 /* In: Line Status Register */
121 #define UART_LSR_TEMT 0x40 /* Transmitter empty */
122 #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
123 #define UART_LSR_BI 0x10 /* Break interrupt indicator */
124 #define UART_LSR_FE 0x08 /* Frame error indicator */
125 #define UART_LSR_PE 0x04 /* Parity error indicator */
126 #define UART_LSR_OE 0x02 /* Overrun error indicator */
127 #define UART_LSR_DR 0x01 /* Receiver data ready */
128 #define UART_LSR_BRK_ERROR_BITS 0x1E /* BI, FE, PE, OE bits */
130 #define UART_MSR 6 /* In: Modem Status Register */
131 #define UART_MSR_DCD 0x80 /* Data Carrier Detect */
132 #define UART_MSR_RI 0x40 /* Ring Indicator */
133 #define UART_MSR_DSR 0x20 /* Data Set Ready */
134 #define UART_MSR_CTS 0x10 /* Clear to Send */
135 #define UART_MSR_DDCD 0x08 /* Delta DCD */
136 #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
137 #define UART_MSR_DDSR 0x02 /* Delta DSR */
138 #define UART_MSR_DCTS 0x01 /* Delta CTS */
139 #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
141 #define UART_SCR 7 /* I/O: Scratch Register */
146 #define UART_DLL 0 /* Out: Divisor Latch Low */
147 #define UART_DLM 1 /* Out: Divisor Latch High */
150 * LCR=0xBF (or DLAB=1 for 16C660)
152 #define UART_EFR 2 /* I/O: Extended Features Register */
153 #define UART_EFR_CTS 0x80 /* CTS flow control */
154 #define UART_EFR_RTS 0x40 /* RTS flow control */
155 #define UART_EFR_SCD 0x20 /* Special character detect */
156 #define UART_EFR_ECB 0x10 /* Enhanced control bit */
158 * the low four bits control software flow control
162 * LCR=0xBF, TI16C752, ST16650, ST16650A, ST16654
164 #define UART_XON1 4 /* I/O: Xon character 1 */
165 #define UART_XON2 5 /* I/O: Xon character 2 */
166 #define UART_XOFF1 6 /* I/O: Xoff character 1 */
167 #define UART_XOFF2 7 /* I/O: Xoff character 2 */
170 * EFR[4]=1 MCR[6]=1, TI16C752
172 #define UART_TI752_TCR 6 /* I/O: transmission control register */
173 #define UART_TI752_TLR 7 /* I/O: trigger level register */
178 #define UART_TRG 0 /* FCTR bit 7 selects Rx or Tx
180 * Out: Fifo custom trigger levels */
182 * These are the definitions for the Programmable Trigger Register
184 #define UART_TRG_1 0x01
185 #define UART_TRG_4 0x04
186 #define UART_TRG_8 0x08
187 #define UART_TRG_16 0x10
188 #define UART_TRG_32 0x20
189 #define UART_TRG_64 0x40
190 #define UART_TRG_96 0x60
191 #define UART_TRG_120 0x78
192 #define UART_TRG_128 0x80
194 #define UART_FCTR 1 /* Feature Control Register */
195 #define UART_FCTR_RTS_NODELAY 0x00 /* RTS flow control delay */
196 #define UART_FCTR_RTS_4DELAY 0x01
197 #define UART_FCTR_RTS_6DELAY 0x02
198 #define UART_FCTR_RTS_8DELAY 0x03
199 #define UART_FCTR_IRDA 0x04 /* IrDa data encode select */
200 #define UART_FCTR_TX_INT 0x08 /* Tx interrupt type select */
201 #define UART_FCTR_TRGA 0x00 /* Tx/Rx 550 trigger table select */
202 #define UART_FCTR_TRGB 0x10 /* Tx/Rx 650 trigger table select */
203 #define UART_FCTR_TRGC 0x20 /* Tx/Rx 654 trigger table select */
204 #define UART_FCTR_TRGD 0x30 /* Tx/Rx 850 programmable trigger select */
205 #define UART_FCTR_SCR_SWAP 0x40 /* Scratch pad register swap */
206 #define UART_FCTR_RX 0x00 /* Programmable trigger mode select */
207 #define UART_FCTR_TX 0x80 /* Programmable trigger mode select */
210 * LCR=0xBF, FCTR[6]=1
212 #define UART_EMSR 7 /* Extended Mode Select Register */
213 #define UART_EMSR_FIFO_COUNT 0x01 /* Rx/Tx select */
214 #define UART_EMSR_ALT_COUNT 0x02 /* Alternating count select */
217 * The Intel XScale on-chip UARTs define these bits
219 #define UART_IER_DMAE 0x80 /* DMA Requests Enable */
220 #define UART_IER_UUE 0x40 /* UART Unit Enable */
221 #define UART_IER_NRZE 0x20 /* NRZ coding Enable */
222 #define UART_IER_RTOIE 0x10 /* Receiver Time Out Interrupt Enable */
224 #define UART_IIR_TOD 0x08 /* Character Timeout Indication Detected */
226 #define UART_FCR_PXAR1 0x00 /* receive FIFO threshold = 1 */
227 #define UART_FCR_PXAR8 0x40 /* receive FIFO threshold = 8 */
228 #define UART_FCR_PXAR16 0x80 /* receive FIFO threshold = 16 */
229 #define UART_FCR_PXAR32 0xc0 /* receive FIFO threshold = 32 */
232 * Intel MID on-chip HSU (High Speed UART) defined bits
234 #define UART_FCR_HSU_64_1B 0x00 /* receive FIFO treshold = 1 */
235 #define UART_FCR_HSU_64_16B 0x40 /* receive FIFO treshold = 16 */
236 #define UART_FCR_HSU_64_32B 0x80 /* receive FIFO treshold = 32 */
237 #define UART_FCR_HSU_64_56B 0xc0 /* receive FIFO treshold = 56 */
239 #define UART_FCR_HSU_16_1B 0x00 /* receive FIFO treshold = 1 */
240 #define UART_FCR_HSU_16_4B 0x40 /* receive FIFO treshold = 4 */
241 #define UART_FCR_HSU_16_8B 0x80 /* receive FIFO treshold = 8 */
242 #define UART_FCR_HSU_16_14B 0xc0 /* receive FIFO treshold = 14 */
244 #define UART_FCR_HSU_64B_FIFO 0x20 /* chose 64 bytes FIFO */
245 #define UART_FCR_HSU_16B_FIFO 0x00 /* chose 16 bytes FIFO */
247 #define UART_FCR_HALF_EMPT_TXI 0x00 /* trigger TX_EMPT IRQ for half empty */
248 #define UART_FCR_FULL_EMPT_TXI 0x08 /* trigger TX_EMPT IRQ for full empty */
251 * These register definitions are for the 16C950
253 #define UART_ASR 0x01 /* Additional Status Register */
254 #define UART_RFL 0x03 /* Receiver FIFO level */
255 #define UART_TFL 0x04 /* Transmitter FIFO level */
256 #define UART_ICR 0x05 /* Index Control Register */
258 /* The 16950 ICR registers */
259 #define UART_ACR 0x00 /* Additional Control Register */
260 #define UART_CPR 0x01 /* Clock Prescalar Register */
261 #define UART_TCR 0x02 /* Times Clock Register */
262 #define UART_CKS 0x03 /* Clock Select Register */
263 #define UART_TTL 0x04 /* Transmitter Interrupt Trigger Level */
264 #define UART_RTL 0x05 /* Receiver Interrupt Trigger Level */
265 #define UART_FCL 0x06 /* Flow Control Level Lower */
266 #define UART_FCH 0x07 /* Flow Control Level Higher */
267 #define UART_ID1 0x08 /* ID #1 */
268 #define UART_ID2 0x09 /* ID #2 */
269 #define UART_ID3 0x0A /* ID #3 */
270 #define UART_REV 0x0B /* Revision */
271 #define UART_CSR 0x0C /* Channel Software Reset */
272 #define UART_NMR 0x0D /* Nine-bit Mode Register */
273 #define UART_CTR 0xFF
276 * The 16C950 Additional Control Register
278 #define UART_ACR_RXDIS 0x01 /* Receiver disable */
279 #define UART_ACR_TXDIS 0x02 /* Transmitter disable */
280 #define UART_ACR_DSRFC 0x04 /* DSR Flow Control */
281 #define UART_ACR_TLENB 0x20 /* 950 trigger levels enable */
282 #define UART_ACR_ICRRD 0x40 /* ICR Read enable */
283 #define UART_ACR_ASREN 0x80 /* Additional status enable */
288 * These definitions are for the RSA-DV II/S card, from
290 * Kiyokazu SUTO <suto@ks-and-ks.ne.jp>
293 #define UART_RSA_BASE (-8)
295 #define UART_RSA_MSR ((UART_RSA_BASE) + 0) /* I/O: Mode Select Register */
297 #define UART_RSA_MSR_SWAP (1 << 0) /* Swap low/high 8 bytes in I/O port addr */
298 #define UART_RSA_MSR_FIFO (1 << 2) /* Enable the external FIFO */
299 #define UART_RSA_MSR_FLOW (1 << 3) /* Enable the auto RTS/CTS flow control */
300 #define UART_RSA_MSR_ITYP (1 << 4) /* Level (1) / Edge triger (0) */
302 #define UART_RSA_IER ((UART_RSA_BASE) + 1) /* I/O: Interrupt Enable Register */
304 #define UART_RSA_IER_Rx_FIFO_H (1 << 0) /* Enable Rx FIFO half full int. */
305 #define UART_RSA_IER_Tx_FIFO_H (1 << 1) /* Enable Tx FIFO half full int. */
306 #define UART_RSA_IER_Tx_FIFO_E (1 << 2) /* Enable Tx FIFO empty int. */
307 #define UART_RSA_IER_Rx_TOUT (1 << 3) /* Enable char receive timeout int */
308 #define UART_RSA_IER_TIMER (1 << 4) /* Enable timer interrupt */
310 #define UART_RSA_SRR ((UART_RSA_BASE) + 2) /* IN: Status Read Register */
312 #define UART_RSA_SRR_Tx_FIFO_NEMP (1 << 0) /* Tx FIFO is not empty (1) */
313 #define UART_RSA_SRR_Tx_FIFO_NHFL (1 << 1) /* Tx FIFO is not half full (1) */
314 #define UART_RSA_SRR_Tx_FIFO_NFUL (1 << 2) /* Tx FIFO is not full (1) */
315 #define UART_RSA_SRR_Rx_FIFO_NEMP (1 << 3) /* Rx FIFO is not empty (1) */
316 #define UART_RSA_SRR_Rx_FIFO_NHFL (1 << 4) /* Rx FIFO is not half full (1) */
317 #define UART_RSA_SRR_Rx_FIFO_NFUL (1 << 5) /* Rx FIFO is not full (1) */
318 #define UART_RSA_SRR_Rx_TOUT (1 << 6) /* Character reception timeout occurred (1) */
319 #define UART_RSA_SRR_TIMER (1 << 7) /* Timer interrupt occurred */
321 #define UART_RSA_FRR ((UART_RSA_BASE) + 2) /* OUT: FIFO Reset Register */
323 #define UART_RSA_TIVSR ((UART_RSA_BASE) + 3) /* I/O: Timer Interval Value Set Register */
325 #define UART_RSA_TCR ((UART_RSA_BASE) + 4) /* OUT: Timer Control Register */
327 #define UART_RSA_TCR_SWITCH (1 << 0) /* Timer on */
330 * The RSA DSV/II board has two fixed clock frequencies. One is the
331 * standard rate, and the other is 8 times faster.
333 #define SERIAL_RSA_BAUD_BASE (921600)
334 #define SERIAL_RSA_BAUD_BASE_LO (SERIAL_RSA_BAUD_BASE / 8)
337 * Extra serial register definitions for the internal UARTs
338 * in TI OMAP processors.
340 #define UART_OMAP_MDR1 0x08 /* Mode definition register */
341 #define UART_OMAP_MDR2 0x09 /* Mode definition register 2 */
342 #define UART_OMAP_SCR 0x10 /* Supplementary control register */
343 #define UART_OMAP_SSR 0x11 /* Supplementary status register */
344 #define UART_OMAP_EBLR 0x12 /* BOF length register */
345 #define UART_OMAP_OSC_12M_SEL 0x13 /* OMAP1510 12MHz osc select */
346 #define UART_OMAP_MVER 0x14 /* Module version register */
347 #define UART_OMAP_SYSC 0x15 /* System configuration register */
348 #define UART_OMAP_SYSS 0x16 /* System status register */
349 #define UART_OMAP_WER 0x17 /* Wake-up enable register */
352 * These are the definitions for the MDR1 register
354 #define UART_OMAP_MDR1_16X_MODE 0x00 /* UART 16x mode */
355 #define UART_OMAP_MDR1_SIR_MODE 0x01 /* SIR mode */
356 #define UART_OMAP_MDR1_16X_ABAUD_MODE 0x02 /* UART 16x auto-baud */
357 #define UART_OMAP_MDR1_13X_MODE 0x03 /* UART 13x mode */
358 #define UART_OMAP_MDR1_MIR_MODE 0x04 /* MIR mode */
359 #define UART_OMAP_MDR1_FIR_MODE 0x05 /* FIR mode */
360 #define UART_OMAP_MDR1_CIR_MODE 0x06 /* CIR mode */
361 #define UART_OMAP_MDR1_DISABLE 0x07 /* Disable (default state) */
363 #endif /* _LINUX_SERIAL_REG_H */