4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
20 #include <linux/pci_regs.h> /* The pci register defines */
23 * The PCI interface treats multi-function devices as independent
24 * devices. The slot/function address of each device is encoded
25 * in a single byte as follows:
30 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
31 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
32 #define PCI_FUNC(devfn) ((devfn) & 0x07)
34 /* Ioctls for /proc/bus/pci/X/Y nodes. */
35 #define PCIIOC_BASE ('P' << 24 | 'C' << 16 | 'I' << 8)
36 #define PCIIOC_CONTROLLER (PCIIOC_BASE | 0x00) /* Get controller for PCI device. */
37 #define PCIIOC_MMAP_IS_IO (PCIIOC_BASE | 0x01) /* Set mmap state to I/O space. */
38 #define PCIIOC_MMAP_IS_MEM (PCIIOC_BASE | 0x02) /* Set mmap state to MEM space. */
39 #define PCIIOC_WRITE_COMBINE (PCIIOC_BASE | 0x03) /* Enable/disable write-combining. */
43 #include <linux/mod_devicetable.h>
45 #include <linux/types.h>
46 #include <linux/init.h>
47 #include <linux/ioport.h>
48 #include <linux/list.h>
49 #include <linux/compiler.h>
50 #include <linux/errno.h>
51 #include <linux/kobject.h>
52 #include <linux/atomic.h>
53 #include <linux/device.h>
55 #include <linux/irqreturn.h>
57 /* Include the ID list */
58 #include <linux/pci_ids.h>
60 /* pci_slot represents a physical slot */
62 struct pci_bus *bus; /* The bus this slot is on */
63 struct list_head list; /* node in list of slots on this bus */
64 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */
65 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
69 static inline const char *pci_slot_name(const struct pci_slot *slot)
71 return kobject_name(&slot->kobj);
74 /* File state for mmap()s on /proc/bus/pci/X/Y */
80 /* This defines the direction arg to the DMA mapping routines. */
81 #define PCI_DMA_BIDIRECTIONAL 0
82 #define PCI_DMA_TODEVICE 1
83 #define PCI_DMA_FROMDEVICE 2
84 #define PCI_DMA_NONE 3
87 * For PCI devices, the region numbers are assigned this way:
90 /* #0-5: standard PCI resources */
92 PCI_STD_RESOURCE_END = 5,
94 /* #6: expansion ROM resource */
97 /* device specific resources */
100 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
103 /* resources assigned to buses behind the bridge */
104 #define PCI_BRIDGE_RESOURCE_NUM 4
106 PCI_BRIDGE_RESOURCES,
107 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
108 PCI_BRIDGE_RESOURCE_NUM - 1,
110 /* total resources associated with a PCI device */
113 /* preserve this for compatibility */
114 DEVICE_COUNT_RESOURCE
117 typedef int __bitwise pci_power_t;
119 #define PCI_D0 ((pci_power_t __force) 0)
120 #define PCI_D1 ((pci_power_t __force) 1)
121 #define PCI_D2 ((pci_power_t __force) 2)
122 #define PCI_D3hot ((pci_power_t __force) 3)
123 #define PCI_D3cold ((pci_power_t __force) 4)
124 #define PCI_UNKNOWN ((pci_power_t __force) 5)
125 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
127 /* Remember to update this when the list above changes! */
128 extern const char *pci_power_names[];
130 static inline const char *pci_power_name(pci_power_t state)
132 return pci_power_names[1 + (int) state];
135 #define PCI_PM_D2_DELAY 200
136 #define PCI_PM_D3_WAIT 10
137 #define PCI_PM_BUS_WAIT 50
139 /** The pci_channel state describes connectivity between the CPU and
140 * the pci device. If some PCI bus between here and the pci device
141 * has crashed or locked up, this info is reflected here.
143 typedef unsigned int __bitwise pci_channel_state_t;
145 enum pci_channel_state {
146 /* I/O channel is in normal state */
147 pci_channel_io_normal = (__force pci_channel_state_t) 1,
149 /* I/O to channel is blocked */
150 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
152 /* PCI card is dead */
153 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
156 typedef unsigned int __bitwise pcie_reset_state_t;
158 enum pcie_reset_state {
159 /* Reset is NOT asserted (Use to deassert reset) */
160 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
162 /* Use #PERST to reset PCI-E device */
163 pcie_warm_reset = (__force pcie_reset_state_t) 2,
165 /* Use PCI-E Hot Reset to reset device */
166 pcie_hot_reset = (__force pcie_reset_state_t) 3
169 typedef unsigned short __bitwise pci_dev_flags_t;
171 /* INTX_DISABLE in PCI_COMMAND register disables MSI
174 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) 1,
175 /* Device configuration is irrevocably lost if disabled into D3 */
176 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) 2,
177 /* Provide indication device is assigned by a Virtual Machine Manager */
178 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) 4,
181 enum pci_irq_reroute_variant {
182 INTEL_IRQ_REROUTE_VARIANT = 1,
183 MAX_IRQ_REROUTE_VARIANTS = 3
186 typedef unsigned short __bitwise pci_bus_flags_t;
188 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
189 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
192 /* Based on the PCI Hotplug Spec, but some values are made up by us */
194 PCI_SPEED_33MHz = 0x00,
195 PCI_SPEED_66MHz = 0x01,
196 PCI_SPEED_66MHz_PCIX = 0x02,
197 PCI_SPEED_100MHz_PCIX = 0x03,
198 PCI_SPEED_133MHz_PCIX = 0x04,
199 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
200 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
201 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
202 PCI_SPEED_66MHz_PCIX_266 = 0x09,
203 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
204 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
210 PCI_SPEED_66MHz_PCIX_533 = 0x11,
211 PCI_SPEED_100MHz_PCIX_533 = 0x12,
212 PCI_SPEED_133MHz_PCIX_533 = 0x13,
213 PCIE_SPEED_2_5GT = 0x14,
214 PCIE_SPEED_5_0GT = 0x15,
215 PCIE_SPEED_8_0GT = 0x16,
216 PCI_SPEED_UNKNOWN = 0xff,
219 struct pci_cap_saved_data {
225 struct pci_cap_saved_state {
226 struct hlist_node next;
227 struct pci_cap_saved_data cap;
230 struct pcie_link_state;
236 * The pci_dev structure is used to describe PCI devices.
239 struct list_head bus_list; /* node in per-bus list */
240 struct pci_bus *bus; /* bus this device is on */
241 struct pci_bus *subordinate; /* bus this device bridges to */
243 void *sysdata; /* hook for sys-specific extension */
244 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
245 struct pci_slot *slot; /* Physical slot this device is in */
247 unsigned int devfn; /* encoded device & function index */
248 unsigned short vendor;
249 unsigned short device;
250 unsigned short subsystem_vendor;
251 unsigned short subsystem_device;
252 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
253 u8 revision; /* PCI revision, low byte of class word */
254 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
255 u8 pcie_cap; /* PCI-E capability offset */
256 u8 pcie_type:4; /* PCI-E device/port type */
257 u8 pcie_mpss:3; /* PCI-E Max Payload Size Supported */
258 u8 rom_base_reg; /* which config register controls the ROM */
259 u8 pin; /* which interrupt pin this device uses */
261 struct pci_driver *driver; /* which driver has allocated this device */
262 u64 dma_mask; /* Mask of the bits of bus address this
263 device implements. Normally this is
264 0xffffffff. You only need to change
265 this if your device has broken DMA
266 or supports 64-bit transfers. */
268 struct device_dma_parameters dma_parms;
270 pci_power_t current_state; /* Current operating state. In ACPI-speak,
271 this is D0-D3, D0 being fully functional,
273 int pm_cap; /* PM capability offset in the
274 configuration space */
275 unsigned int pme_support:5; /* Bitmask of states from which PME#
277 unsigned int pme_interrupt:1;
278 unsigned int pme_poll:1; /* Poll device's PME status bit */
279 unsigned int d1_support:1; /* Low power state D1 is supported */
280 unsigned int d2_support:1; /* Low power state D2 is supported */
281 unsigned int no_d1d2:1; /* Only allow D0 and D3 */
282 unsigned int mmio_always_on:1; /* disallow turning off io/mem
283 decoding during bar sizing */
284 unsigned int wakeup_prepared:1;
285 unsigned int d3_delay; /* D3->D0 transition time in ms */
287 #ifdef CONFIG_PCIEASPM
288 struct pcie_link_state *link_state; /* ASPM link state. */
291 pci_channel_state_t error_state; /* current connectivity state */
292 struct device dev; /* Generic device interface */
294 int cfg_size; /* Size of configuration space */
297 * Instead of touching interrupt line and base address registers
298 * directly, use the values stored here. They might be different!
301 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
302 resource_size_t fw_addr[DEVICE_COUNT_RESOURCE]; /* FW-assigned addr */
304 /* These fields are used by common fixups */
305 unsigned int transparent:1; /* Transparent PCI bridge */
306 unsigned int multifunction:1;/* Part of multi-function device */
307 /* keep track of device state */
308 unsigned int is_added:1;
309 unsigned int is_busmaster:1; /* device is busmaster */
310 unsigned int no_msi:1; /* device may not use msi */
311 unsigned int block_ucfg_access:1; /* userspace config space access is blocked */
312 unsigned int broken_parity_status:1; /* Device generates false positive parity */
313 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */
314 unsigned int msi_enabled:1;
315 unsigned int msix_enabled:1;
316 unsigned int ari_enabled:1; /* ARI forwarding */
317 unsigned int is_managed:1;
318 unsigned int is_pcie:1; /* Obsolete. Will be removed.
319 Use pci_is_pcie() instead */
320 unsigned int needs_freset:1; /* Dev requires fundamental reset */
321 unsigned int state_saved:1;
322 unsigned int is_physfn:1;
323 unsigned int is_virtfn:1;
324 unsigned int reset_fn:1;
325 unsigned int is_hotplug_bridge:1;
326 unsigned int __aer_firmware_first_valid:1;
327 unsigned int __aer_firmware_first:1;
328 pci_dev_flags_t dev_flags;
329 atomic_t enable_cnt; /* pci_enable_device has been called */
331 u32 saved_config_space[16]; /* config space saved at suspend time */
332 struct hlist_head saved_cap_space;
333 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
334 int rom_attr_enabled; /* has display of the rom attribute been enabled? */
335 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
336 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
337 #ifdef CONFIG_PCI_MSI
338 struct list_head msi_list;
341 #ifdef CONFIG_PCI_ATS
343 struct pci_sriov *sriov; /* SR-IOV capability related */
344 struct pci_dev *physfn; /* the PF this VF is associated with */
346 struct pci_ats *ats; /* Address Translation Service */
350 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
352 #ifdef CONFIG_PCI_IOV
360 extern struct pci_dev *alloc_pci_dev(void);
362 #define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list)
363 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
364 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
366 static inline int pci_channel_offline(struct pci_dev *pdev)
368 return (pdev->error_state != pci_channel_io_normal);
371 static inline struct pci_cap_saved_state *pci_find_saved_cap(
372 struct pci_dev *pci_dev, char cap)
374 struct pci_cap_saved_state *tmp;
375 struct hlist_node *pos;
377 hlist_for_each_entry(tmp, pos, &pci_dev->saved_cap_space, next) {
378 if (tmp->cap.cap_nr == cap)
384 static inline void pci_add_saved_cap(struct pci_dev *pci_dev,
385 struct pci_cap_saved_state *new_cap)
387 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
391 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
392 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
393 * buses below host bridges or subtractive decode bridges) go in the list.
394 * Use pci_bus_for_each_resource() to iterate through all the resources.
398 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
399 * and there's no way to program the bridge with the details of the window.
400 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
401 * decode bit set, because they are explicit and can be programmed with _SRS.
403 #define PCI_SUBTRACTIVE_DECODE 0x1
405 struct pci_bus_resource {
406 struct list_head list;
407 struct resource *res;
411 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
414 struct list_head node; /* node in list of buses */
415 struct pci_bus *parent; /* parent bus this bridge is on */
416 struct list_head children; /* list of child buses */
417 struct list_head devices; /* list of devices on this bus */
418 struct pci_dev *self; /* bridge device as seen by parent */
419 struct list_head slots; /* list of slots on this bus */
420 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
421 struct list_head resources; /* address space routed to this bus */
423 struct pci_ops *ops; /* configuration access functions */
424 void *sysdata; /* hook for sys-specific extension */
425 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
427 unsigned char number; /* bus number */
428 unsigned char primary; /* number of primary bridge */
429 unsigned char secondary; /* number of secondary bridge */
430 unsigned char subordinate; /* max number of subordinate buses */
431 unsigned char max_bus_speed; /* enum pci_bus_speed */
432 unsigned char cur_bus_speed; /* enum pci_bus_speed */
436 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
437 pci_bus_flags_t bus_flags; /* Inherited by child busses */
438 struct device *bridge;
440 struct bin_attribute *legacy_io; /* legacy I/O for this bus */
441 struct bin_attribute *legacy_mem; /* legacy mem */
442 unsigned int is_added:1;
445 #define pci_bus_b(n) list_entry(n, struct pci_bus, node)
446 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
449 * Returns true if the pci bus is root (behind host-pci bridge),
452 static inline bool pci_is_root_bus(struct pci_bus *pbus)
454 return !(pbus->parent);
457 #ifdef CONFIG_PCI_MSI
458 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
460 return pci_dev->msi_enabled || pci_dev->msix_enabled;
463 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
467 * Error values that may be returned by PCI functions.
469 #define PCIBIOS_SUCCESSFUL 0x00
470 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
471 #define PCIBIOS_BAD_VENDOR_ID 0x83
472 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
473 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
474 #define PCIBIOS_SET_FAILED 0x88
475 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
477 /* Low-level architecture-dependent routines */
480 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
481 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
485 * ACPI needs to be able to access PCI config space before we've done a
486 * PCI bus scan and created pci_bus structures.
488 extern int raw_pci_read(unsigned int domain, unsigned int bus,
489 unsigned int devfn, int reg, int len, u32 *val);
490 extern int raw_pci_write(unsigned int domain, unsigned int bus,
491 unsigned int devfn, int reg, int len, u32 val);
493 struct pci_bus_region {
494 resource_size_t start;
499 spinlock_t lock; /* protects list, index */
500 struct list_head list; /* for IDs added at runtime */
503 /* ---------------------------------------------------------------- */
504 /** PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
505 * a set of callbacks in struct pci_error_handlers, then that device driver
506 * will be notified of PCI bus errors, and will be driven to recovery
507 * when an error occurs.
510 typedef unsigned int __bitwise pci_ers_result_t;
512 enum pci_ers_result {
513 /* no result/none/not supported in device driver */
514 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
516 /* Device driver can recover without slot reset */
517 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
519 /* Device driver wants slot to be reset. */
520 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
522 /* Device has completely failed, is unrecoverable */
523 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
525 /* Device driver is fully recovered and operational */
526 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
529 /* PCI bus error event callbacks */
530 struct pci_error_handlers {
531 /* PCI bus error detected on this device */
532 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
533 enum pci_channel_state error);
535 /* MMIO has been re-enabled, but not DMA */
536 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
538 /* PCI Express link has been reset */
539 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
541 /* PCI slot has been reset */
542 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
544 /* Device driver may resume normal operations */
545 void (*resume)(struct pci_dev *dev);
548 /* ---------------------------------------------------------------- */
552 struct list_head node;
554 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */
555 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
556 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
557 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
558 int (*suspend_late) (struct pci_dev *dev, pm_message_t state);
559 int (*resume_early) (struct pci_dev *dev);
560 int (*resume) (struct pci_dev *dev); /* Device woken up */
561 void (*shutdown) (struct pci_dev *dev);
562 struct pci_error_handlers *err_handler;
563 struct device_driver driver;
564 struct pci_dynids dynids;
567 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
570 * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table
571 * @_table: device table name
573 * This macro is used to create a struct pci_device_id array (a device table)
574 * in a generic manner.
576 #define DEFINE_PCI_DEVICE_TABLE(_table) \
577 const struct pci_device_id _table[] __devinitconst
580 * PCI_DEVICE - macro used to describe a specific pci device
581 * @vend: the 16 bit PCI Vendor ID
582 * @dev: the 16 bit PCI Device ID
584 * This macro is used to create a struct pci_device_id that matches a
585 * specific device. The subvendor and subdevice fields will be set to
588 #define PCI_DEVICE(vend,dev) \
589 .vendor = (vend), .device = (dev), \
590 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
593 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem
594 * @vend: the 16 bit PCI Vendor ID
595 * @dev: the 16 bit PCI Device ID
596 * @subvend: the 16 bit PCI Subvendor ID
597 * @subdev: the 16 bit PCI Subdevice ID
599 * This macro is used to create a struct pci_device_id that matches a
600 * specific device with subsystem information.
602 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
603 .vendor = (vend), .device = (dev), \
604 .subvendor = (subvend), .subdevice = (subdev)
607 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
608 * @dev_class: the class, subclass, prog-if triple for this device
609 * @dev_class_mask: the class mask for this device
611 * This macro is used to create a struct pci_device_id that matches a
612 * specific PCI class. The vendor, device, subvendor, and subdevice
613 * fields will be set to PCI_ANY_ID.
615 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
616 .class = (dev_class), .class_mask = (dev_class_mask), \
617 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
618 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
621 * PCI_VDEVICE - macro used to describe a specific pci device in short form
622 * @vendor: the vendor name
623 * @device: the 16 bit PCI Device ID
625 * This macro is used to create a struct pci_device_id that matches a
626 * specific PCI device. The subvendor, and subdevice fields will be set
627 * to PCI_ANY_ID. The macro allows the next field to follow as the device
631 #define PCI_VDEVICE(vendor, device) \
632 PCI_VENDOR_ID_##vendor, (device), \
633 PCI_ANY_ID, PCI_ANY_ID, 0, 0
635 /* these external functions are only available when PCI support is enabled */
638 extern void pcie_bus_configure_settings(struct pci_bus *bus, u8 smpss);
640 enum pcie_bus_config_types {
643 PCIE_BUS_PERFORMANCE,
647 extern enum pcie_bus_config_types pcie_bus_config;
649 extern struct bus_type pci_bus_type;
651 /* Do NOT directly access these two variables, unless you are arch specific pci
652 * code, or pci core code. */
653 extern struct list_head pci_root_buses; /* list of all known PCI buses */
654 /* Some device drivers need know if pci is initiated */
655 extern int no_pci_devices(void);
657 void pcibios_fixup_bus(struct pci_bus *);
658 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
659 char *pcibios_setup(char *str);
661 /* Used only when drivers/pci/setup.c is used */
662 resource_size_t pcibios_align_resource(void *, const struct resource *,
665 void pcibios_update_irq(struct pci_dev *, int irq);
667 /* Weak but can be overriden by arch */
668 void pci_fixup_cardbus(struct pci_bus *);
670 /* Generic PCI functions used internally */
672 void pcibios_scan_specific_bus(int busn);
673 extern struct pci_bus *pci_find_bus(int domain, int busnr);
674 void pci_bus_add_devices(const struct pci_bus *bus);
675 struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus,
676 struct pci_ops *ops, void *sysdata);
677 static inline struct pci_bus * __devinit pci_scan_bus(int bus, struct pci_ops *ops,
680 struct pci_bus *root_bus;
681 root_bus = pci_scan_bus_parented(NULL, bus, ops, sysdata);
683 pci_bus_add_devices(root_bus);
686 struct pci_bus *pci_create_bus(struct device *parent, int bus,
687 struct pci_ops *ops, void *sysdata);
688 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
690 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
691 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
693 struct hotplug_slot *hotplug);
694 void pci_destroy_slot(struct pci_slot *slot);
695 void pci_renumber_slot(struct pci_slot *slot, int slot_nr);
696 int pci_scan_slot(struct pci_bus *bus, int devfn);
697 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
698 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
699 unsigned int pci_scan_child_bus(struct pci_bus *bus);
700 int __must_check pci_bus_add_device(struct pci_dev *dev);
701 void pci_read_bridge_bases(struct pci_bus *child);
702 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
703 struct resource *res);
704 u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin);
705 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
706 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
707 extern struct pci_dev *pci_dev_get(struct pci_dev *dev);
708 extern void pci_dev_put(struct pci_dev *dev);
709 extern void pci_remove_bus(struct pci_bus *b);
710 extern void pci_remove_bus_device(struct pci_dev *dev);
711 extern void pci_stop_bus_device(struct pci_dev *dev);
712 void pci_setup_cardbus(struct pci_bus *bus);
713 extern void pci_sort_breadthfirst(void);
714 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
715 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
716 #define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0))
718 /* Generic PCI functions exported to card drivers */
720 enum pci_lost_interrupt_reason {
721 PCI_LOST_IRQ_NO_INFORMATION = 0,
722 PCI_LOST_IRQ_DISABLE_MSI,
723 PCI_LOST_IRQ_DISABLE_MSIX,
724 PCI_LOST_IRQ_DISABLE_ACPI,
726 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
727 int pci_find_capability(struct pci_dev *dev, int cap);
728 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
729 int pci_find_ext_capability(struct pci_dev *dev, int cap);
730 int pci_bus_find_ext_capability(struct pci_bus *bus, unsigned int devfn,
732 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
733 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
734 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
736 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
737 struct pci_dev *from);
738 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
739 unsigned int ss_vendor, unsigned int ss_device,
740 struct pci_dev *from);
741 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
742 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
744 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
747 return pci_get_domain_bus_and_slot(0, bus, devfn);
749 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
750 int pci_dev_present(const struct pci_device_id *ids);
752 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
754 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
755 int where, u16 *val);
756 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
757 int where, u32 *val);
758 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
760 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
762 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
764 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
766 static inline int pci_read_config_byte(struct pci_dev *dev, int where, u8 *val)
768 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
770 static inline int pci_read_config_word(struct pci_dev *dev, int where, u16 *val)
772 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
774 static inline int pci_read_config_dword(struct pci_dev *dev, int where,
777 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
779 static inline int pci_write_config_byte(struct pci_dev *dev, int where, u8 val)
781 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
783 static inline int pci_write_config_word(struct pci_dev *dev, int where, u16 val)
785 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
787 static inline int pci_write_config_dword(struct pci_dev *dev, int where,
790 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
793 int __must_check pci_enable_device(struct pci_dev *dev);
794 int __must_check pci_enable_device_io(struct pci_dev *dev);
795 int __must_check pci_enable_device_mem(struct pci_dev *dev);
796 int __must_check pci_reenable_device(struct pci_dev *);
797 int __must_check pcim_enable_device(struct pci_dev *pdev);
798 void pcim_pin_device(struct pci_dev *pdev);
800 static inline int pci_is_enabled(struct pci_dev *pdev)
802 return (atomic_read(&pdev->enable_cnt) > 0);
805 static inline int pci_is_managed(struct pci_dev *pdev)
807 return pdev->is_managed;
810 void pci_disable_device(struct pci_dev *dev);
811 void pci_set_master(struct pci_dev *dev);
812 void pci_clear_master(struct pci_dev *dev);
813 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
814 int pci_set_cacheline_size(struct pci_dev *dev);
815 #define HAVE_PCI_SET_MWI
816 int __must_check pci_set_mwi(struct pci_dev *dev);
817 int pci_try_set_mwi(struct pci_dev *dev);
818 void pci_clear_mwi(struct pci_dev *dev);
819 void pci_intx(struct pci_dev *dev, int enable);
820 void pci_msi_off(struct pci_dev *dev);
821 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size);
822 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask);
823 int pcix_get_max_mmrbc(struct pci_dev *dev);
824 int pcix_get_mmrbc(struct pci_dev *dev);
825 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
826 int pcie_get_readrq(struct pci_dev *dev);
827 int pcie_set_readrq(struct pci_dev *dev, int rq);
828 int pcie_get_mps(struct pci_dev *dev);
829 int pcie_set_mps(struct pci_dev *dev, int mps);
830 int __pci_reset_function(struct pci_dev *dev);
831 int pci_reset_function(struct pci_dev *dev);
832 void pci_update_resource(struct pci_dev *dev, int resno);
833 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
834 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
835 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
837 /* ROM control related routines */
838 int pci_enable_rom(struct pci_dev *pdev);
839 void pci_disable_rom(struct pci_dev *pdev);
840 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
841 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
842 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
844 /* Power management related routines */
845 int pci_save_state(struct pci_dev *dev);
846 void pci_restore_state(struct pci_dev *dev);
847 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
848 int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state);
849 int pci_load_and_free_saved_state(struct pci_dev *dev,
850 struct pci_saved_state **state);
851 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
852 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
853 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
854 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
855 void pci_pme_active(struct pci_dev *dev, bool enable);
856 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
857 bool runtime, bool enable);
858 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
859 pci_power_t pci_target_state(struct pci_dev *dev);
860 int pci_prepare_to_sleep(struct pci_dev *dev);
861 int pci_back_from_sleep(struct pci_dev *dev);
862 bool pci_dev_run_wake(struct pci_dev *dev);
863 bool pci_check_pme_status(struct pci_dev *dev);
864 void pci_pme_wakeup_bus(struct pci_bus *bus);
866 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
869 return __pci_enable_wake(dev, state, false, enable);
872 #define PCI_EXP_IDO_REQUEST (1<<0)
873 #define PCI_EXP_IDO_COMPLETION (1<<1)
874 void pci_enable_ido(struct pci_dev *dev, unsigned long type);
875 void pci_disable_ido(struct pci_dev *dev, unsigned long type);
877 enum pci_obff_signal_type {
878 PCI_EXP_OBFF_SIGNAL_L0 = 0,
879 PCI_EXP_OBFF_SIGNAL_ALWAYS = 1,
881 int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type);
882 void pci_disable_obff(struct pci_dev *dev);
884 bool pci_ltr_supported(struct pci_dev *dev);
885 int pci_enable_ltr(struct pci_dev *dev);
886 void pci_disable_ltr(struct pci_dev *dev);
887 int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns);
889 /* For use by arch with custom probe code */
890 void set_pcie_port_type(struct pci_dev *pdev);
891 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
893 /* Functions for PCI Hotplug drivers to use */
894 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
895 #ifdef CONFIG_HOTPLUG
896 unsigned int pci_rescan_bus(struct pci_bus *bus);
899 /* Vital product data routines */
900 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
901 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
902 int pci_vpd_truncate(struct pci_dev *dev, size_t size);
904 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
905 void pci_bus_assign_resources(const struct pci_bus *bus);
906 void pci_bus_size_bridges(struct pci_bus *bus);
907 int pci_claim_resource(struct pci_dev *, int);
908 void pci_assign_unassigned_resources(void);
909 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
910 void pdev_enable_device(struct pci_dev *);
911 void pdev_sort_resources(struct pci_dev *, struct resource_list *);
912 int pci_enable_resources(struct pci_dev *, int mask);
913 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
914 int (*)(const struct pci_dev *, u8, u8));
915 #define HAVE_PCI_REQ_REGIONS 2
916 int __must_check pci_request_regions(struct pci_dev *, const char *);
917 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
918 void pci_release_regions(struct pci_dev *);
919 int __must_check pci_request_region(struct pci_dev *, int, const char *);
920 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
921 void pci_release_region(struct pci_dev *, int);
922 int pci_request_selected_regions(struct pci_dev *, int, const char *);
923 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
924 void pci_release_selected_regions(struct pci_dev *, int);
926 /* drivers/pci/bus.c */
927 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, unsigned int flags);
928 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
929 void pci_bus_remove_resources(struct pci_bus *bus);
931 #define pci_bus_for_each_resource(bus, res, i) \
933 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
936 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
937 struct resource *res, resource_size_t size,
938 resource_size_t align, resource_size_t min,
939 unsigned int type_mask,
940 resource_size_t (*alignf)(void *,
941 const struct resource *,
945 void pci_enable_bridges(struct pci_bus *bus);
947 /* Proper probing supporting hot-pluggable devices */
948 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
949 const char *mod_name);
952 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
954 #define pci_register_driver(driver) \
955 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
957 void pci_unregister_driver(struct pci_driver *dev);
958 void pci_remove_behind_bridge(struct pci_dev *dev);
959 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
960 int pci_add_dynid(struct pci_driver *drv,
961 unsigned int vendor, unsigned int device,
962 unsigned int subvendor, unsigned int subdevice,
963 unsigned int class, unsigned int class_mask,
964 unsigned long driver_data);
965 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
966 struct pci_dev *dev);
967 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
970 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
972 int pci_cfg_space_size_ext(struct pci_dev *dev);
973 int pci_cfg_space_size(struct pci_dev *dev);
974 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
975 void pci_setup_bridge(struct pci_bus *bus);
977 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
978 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
980 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
981 unsigned int command_bits, u32 flags);
982 /* kmem_cache style wrapper around pci_alloc_consistent() */
984 #include <linux/pci-dma.h>
985 #include <linux/dmapool.h>
987 #define pci_pool dma_pool
988 #define pci_pool_create(name, pdev, size, align, allocation) \
989 dma_pool_create(name, &pdev->dev, size, align, allocation)
990 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
991 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
992 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
994 enum pci_dma_burst_strategy {
995 PCI_DMA_BURST_INFINITY, /* make bursts as large as possible,
996 strategy_parameter is N/A */
997 PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter
999 PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of
1000 strategy_parameter byte boundaries */
1004 u32 vector; /* kernel uses to write allocated vector */
1005 u16 entry; /* driver uses to specify entry, OS writes */
1009 #ifndef CONFIG_PCI_MSI
1010 static inline int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec)
1015 static inline void pci_msi_shutdown(struct pci_dev *dev)
1017 static inline void pci_disable_msi(struct pci_dev *dev)
1020 static inline int pci_msix_table_size(struct pci_dev *dev)
1024 static inline int pci_enable_msix(struct pci_dev *dev,
1025 struct msix_entry *entries, int nvec)
1030 static inline void pci_msix_shutdown(struct pci_dev *dev)
1032 static inline void pci_disable_msix(struct pci_dev *dev)
1035 static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev)
1038 static inline void pci_restore_msi_state(struct pci_dev *dev)
1040 static inline int pci_msi_enabled(void)
1045 extern int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec);
1046 extern void pci_msi_shutdown(struct pci_dev *dev);
1047 extern void pci_disable_msi(struct pci_dev *dev);
1048 extern int pci_msix_table_size(struct pci_dev *dev);
1049 extern int pci_enable_msix(struct pci_dev *dev,
1050 struct msix_entry *entries, int nvec);
1051 extern void pci_msix_shutdown(struct pci_dev *dev);
1052 extern void pci_disable_msix(struct pci_dev *dev);
1053 extern void msi_remove_pci_irq_vectors(struct pci_dev *dev);
1054 extern void pci_restore_msi_state(struct pci_dev *dev);
1055 extern int pci_msi_enabled(void);
1058 #ifdef CONFIG_PCIEPORTBUS
1059 extern bool pcie_ports_disabled;
1060 extern bool pcie_ports_auto;
1062 #define pcie_ports_disabled true
1063 #define pcie_ports_auto false
1066 #ifndef CONFIG_PCIEASPM
1067 static inline int pcie_aspm_enabled(void) { return 0; }
1068 static inline bool pcie_aspm_support_enabled(void) { return false; }
1070 extern int pcie_aspm_enabled(void);
1071 extern bool pcie_aspm_support_enabled(void);
1074 #ifdef CONFIG_PCIEAER
1075 void pci_no_aer(void);
1076 bool pci_aer_available(void);
1078 static inline void pci_no_aer(void) { }
1079 static inline bool pci_aer_available(void) { return false; }
1082 #ifndef CONFIG_PCIE_ECRC
1083 static inline void pcie_set_ecrc_checking(struct pci_dev *dev)
1087 static inline void pcie_ecrc_get_policy(char *str) {};
1089 extern void pcie_set_ecrc_checking(struct pci_dev *dev);
1090 extern void pcie_ecrc_get_policy(char *str);
1093 #define pci_enable_msi(pdev) pci_enable_msi_block(pdev, 1)
1095 #ifdef CONFIG_HT_IRQ
1096 /* The functions a driver should call */
1097 int ht_create_irq(struct pci_dev *dev, int idx);
1098 void ht_destroy_irq(unsigned int irq);
1099 #endif /* CONFIG_HT_IRQ */
1101 extern void pci_block_user_cfg_access(struct pci_dev *dev);
1102 extern void pci_unblock_user_cfg_access(struct pci_dev *dev);
1105 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1106 * a PCI domain is defined to be a set of PCI busses which share
1107 * configuration space.
1109 #ifdef CONFIG_PCI_DOMAINS
1110 extern int pci_domains_supported;
1112 enum { pci_domains_supported = 0 };
1113 static inline int pci_domain_nr(struct pci_bus *bus)
1118 static inline int pci_proc_domain(struct pci_bus *bus)
1122 #endif /* CONFIG_PCI_DOMAINS */
1124 /* some architectures require additional setup to direct VGA traffic */
1125 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1126 unsigned int command_bits, u32 flags);
1127 extern void pci_register_set_vga_state(arch_set_vga_state_t func);
1129 #else /* CONFIG_PCI is not enabled */
1132 * If the system does not have PCI, clearly these return errors. Define
1133 * these as simple inline functions to avoid hair in drivers.
1136 #define _PCI_NOP(o, s, t) \
1137 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1139 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1141 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1142 _PCI_NOP(o, word, u16 x) \
1143 _PCI_NOP(o, dword, u32 x)
1144 _PCI_NOP_ALL(read, *)
1145 _PCI_NOP_ALL(write,)
1147 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1148 unsigned int device,
1149 struct pci_dev *from)
1154 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1155 unsigned int device,
1156 unsigned int ss_vendor,
1157 unsigned int ss_device,
1158 struct pci_dev *from)
1163 static inline struct pci_dev *pci_get_class(unsigned int class,
1164 struct pci_dev *from)
1169 #define pci_dev_present(ids) (0)
1170 #define no_pci_devices() (1)
1171 #define pci_dev_put(dev) do { } while (0)
1173 static inline void pci_set_master(struct pci_dev *dev)
1176 static inline int pci_enable_device(struct pci_dev *dev)
1181 static inline void pci_disable_device(struct pci_dev *dev)
1184 static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
1189 static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
1194 static inline int pci_set_dma_max_seg_size(struct pci_dev *dev,
1200 static inline int pci_set_dma_seg_boundary(struct pci_dev *dev,
1206 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1211 static inline int __pci_register_driver(struct pci_driver *drv,
1212 struct module *owner)
1217 static inline int pci_register_driver(struct pci_driver *drv)
1222 static inline void pci_unregister_driver(struct pci_driver *drv)
1225 static inline int pci_find_capability(struct pci_dev *dev, int cap)
1230 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1236 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1241 /* Power management related routines */
1242 static inline int pci_save_state(struct pci_dev *dev)
1247 static inline void pci_restore_state(struct pci_dev *dev)
1250 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1255 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1260 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1266 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1272 static inline void pci_enable_ido(struct pci_dev *dev, unsigned long type)
1276 static inline void pci_disable_ido(struct pci_dev *dev, unsigned long type)
1280 static inline int pci_enable_obff(struct pci_dev *dev, unsigned long type)
1285 static inline void pci_disable_obff(struct pci_dev *dev)
1289 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1294 static inline void pci_release_regions(struct pci_dev *dev)
1297 #define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
1299 static inline void pci_block_user_cfg_access(struct pci_dev *dev)
1302 static inline void pci_unblock_user_cfg_access(struct pci_dev *dev)
1305 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1308 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1312 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
1316 static inline int pci_domain_nr(struct pci_bus *bus)
1319 #define dev_is_pci(d) (false)
1320 #define dev_is_pf(d) (false)
1321 #define dev_num_vf(d) (0)
1322 #endif /* CONFIG_PCI */
1324 /* Include architecture-dependent settings and functions */
1326 #include <asm/pci.h>
1328 #ifndef PCIBIOS_MAX_MEM_32
1329 #define PCIBIOS_MAX_MEM_32 (-1)
1332 /* these helpers provide future and backwards compatibility
1333 * for accessing popular PCI BAR info */
1334 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1335 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1336 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1337 #define pci_resource_len(dev,bar) \
1338 ((pci_resource_start((dev), (bar)) == 0 && \
1339 pci_resource_end((dev), (bar)) == \
1340 pci_resource_start((dev), (bar))) ? 0 : \
1342 (pci_resource_end((dev), (bar)) - \
1343 pci_resource_start((dev), (bar)) + 1))
1345 /* Similar to the helpers above, these manipulate per-pci_dev
1346 * driver-specific data. They are really just a wrapper around
1347 * the generic device structure functions of these calls.
1349 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1351 return dev_get_drvdata(&pdev->dev);
1354 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1356 dev_set_drvdata(&pdev->dev, data);
1359 /* If you want to know what to call your pci_dev, ask this function.
1360 * Again, it's a wrapper around the generic device.
1362 static inline const char *pci_name(const struct pci_dev *pdev)
1364 return dev_name(&pdev->dev);
1368 /* Some archs don't want to expose struct resource to userland as-is
1369 * in sysfs and /proc
1371 #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
1372 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1373 const struct resource *rsrc, resource_size_t *start,
1374 resource_size_t *end)
1376 *start = rsrc->start;
1379 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1383 * The world is not perfect and supplies us with broken PCI devices.
1384 * For at least a part of these bugs we need a work-around, so both
1385 * generic (drivers/pci/quirks.c) and per-architecture code can define
1386 * fixup hooks to be called for particular buggy devices.
1390 u16 vendor, device; /* You can use PCI_ANY_ID here of course */
1391 void (*hook)(struct pci_dev *dev);
1394 enum pci_fixup_pass {
1395 pci_fixup_early, /* Before probing BARs */
1396 pci_fixup_header, /* After reading configuration header */
1397 pci_fixup_final, /* Final phase of device fixups */
1398 pci_fixup_enable, /* pci_enable_device() time */
1399 pci_fixup_resume, /* pci_device_resume() */
1400 pci_fixup_suspend, /* pci_device_suspend */
1401 pci_fixup_resume_early, /* pci_device_resume_early() */
1404 /* Anonymous variables would be nice... */
1405 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, hook) \
1406 static const struct pci_fixup __pci_fixup_##name __used \
1407 __attribute__((__section__(#section))) = { vendor, device, hook };
1408 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1409 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1410 vendor##device##hook, vendor, device, hook)
1411 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1412 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1413 vendor##device##hook, vendor, device, hook)
1414 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1415 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1416 vendor##device##hook, vendor, device, hook)
1417 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1418 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1419 vendor##device##hook, vendor, device, hook)
1420 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1421 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1422 resume##vendor##device##hook, vendor, device, hook)
1423 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1424 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1425 resume_early##vendor##device##hook, vendor, device, hook)
1426 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1427 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1428 suspend##vendor##device##hook, vendor, device, hook)
1430 #ifdef CONFIG_PCI_QUIRKS
1431 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1433 static inline void pci_fixup_device(enum pci_fixup_pass pass,
1434 struct pci_dev *dev) {}
1437 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1438 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1439 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1440 int pcim_iomap_regions(struct pci_dev *pdev, u16 mask, const char *name);
1441 int pcim_iomap_regions_request_all(struct pci_dev *pdev, u16 mask,
1443 void pcim_iounmap_regions(struct pci_dev *pdev, u16 mask);
1445 extern int pci_pci_problems;
1446 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1447 #define PCIPCI_TRITON 2
1448 #define PCIPCI_NATOMA 4
1449 #define PCIPCI_VIAETBF 8
1450 #define PCIPCI_VSFX 16
1451 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1452 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1454 extern unsigned long pci_cardbus_io_size;
1455 extern unsigned long pci_cardbus_mem_size;
1456 extern u8 __devinitdata pci_dfl_cache_line_size;
1457 extern u8 pci_cache_line_size;
1459 extern unsigned long pci_hotplug_io_size;
1460 extern unsigned long pci_hotplug_mem_size;
1462 int pcibios_add_platform_entries(struct pci_dev *dev);
1463 void pcibios_disable_device(struct pci_dev *dev);
1464 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1465 enum pcie_reset_state state);
1467 #ifdef CONFIG_PCI_MMCONFIG
1468 extern void __init pci_mmcfg_early_init(void);
1469 extern void __init pci_mmcfg_late_init(void);
1471 static inline void pci_mmcfg_early_init(void) { }
1472 static inline void pci_mmcfg_late_init(void) { }
1475 int pci_ext_cfg_avail(struct pci_dev *dev);
1477 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
1479 #ifdef CONFIG_PCI_IOV
1480 extern int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1481 extern void pci_disable_sriov(struct pci_dev *dev);
1482 extern irqreturn_t pci_sriov_migration(struct pci_dev *dev);
1483 extern int pci_num_vf(struct pci_dev *dev);
1485 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
1489 static inline void pci_disable_sriov(struct pci_dev *dev)
1492 static inline irqreturn_t pci_sriov_migration(struct pci_dev *dev)
1496 static inline int pci_num_vf(struct pci_dev *dev)
1502 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
1503 extern void pci_hp_create_module_link(struct pci_slot *pci_slot);
1504 extern void pci_hp_remove_module_link(struct pci_slot *pci_slot);
1508 * pci_pcie_cap - get the saved PCIe capability offset
1511 * PCIe capability offset is calculated at PCI device initialization
1512 * time and saved in the data structure. This function returns saved
1513 * PCIe capability offset. Using this instead of pci_find_capability()
1514 * reduces unnecessary search in the PCI configuration space. If you
1515 * need to calculate PCIe capability offset from raw device for some
1516 * reasons, please use pci_find_capability() instead.
1518 static inline int pci_pcie_cap(struct pci_dev *dev)
1520 return dev->pcie_cap;
1524 * pci_is_pcie - check if the PCI device is PCI Express capable
1527 * Retrun true if the PCI device is PCI Express capable, false otherwise.
1529 static inline bool pci_is_pcie(struct pci_dev *dev)
1531 return !!pci_pcie_cap(dev);
1534 void pci_request_acs(void);
1537 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
1538 #define PCI_VPD_LRDT_ID(x) (x | PCI_VPD_LRDT)
1540 /* Large Resource Data Type Tag Item Names */
1541 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
1542 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
1543 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
1545 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
1546 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
1547 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
1549 /* Small Resource Data Type Tag Item Names */
1550 #define PCI_VPD_STIN_END 0x78 /* End */
1552 #define PCI_VPD_SRDT_END PCI_VPD_STIN_END
1554 #define PCI_VPD_SRDT_TIN_MASK 0x78
1555 #define PCI_VPD_SRDT_LEN_MASK 0x07
1557 #define PCI_VPD_LRDT_TAG_SIZE 3
1558 #define PCI_VPD_SRDT_TAG_SIZE 1
1560 #define PCI_VPD_INFO_FLD_HDR_SIZE 3
1562 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
1563 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
1564 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
1565 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
1568 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
1569 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
1571 * Returns the extracted Large Resource Data Type length.
1573 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
1575 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
1579 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
1580 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag
1582 * Returns the extracted Small Resource Data Type length.
1584 static inline u8 pci_vpd_srdt_size(const u8 *srdt)
1586 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
1590 * pci_vpd_info_field_size - Extracts the information field length
1591 * @lrdt: Pointer to the beginning of an information field header
1593 * Returns the extracted information field length.
1595 static inline u8 pci_vpd_info_field_size(const u8 *info_field)
1597 return info_field[2];
1601 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
1602 * @buf: Pointer to buffered vpd data
1603 * @off: The offset into the buffer at which to begin the search
1604 * @len: The length of the vpd buffer
1605 * @rdt: The Resource Data Type to search for
1607 * Returns the index where the Resource Data Type was found or
1608 * -ENOENT otherwise.
1610 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
1613 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
1614 * @buf: Pointer to buffered vpd data
1615 * @off: The offset into the buffer at which to begin the search
1616 * @len: The length of the buffer area, relative to off, in which to search
1617 * @kw: The keyword to search for
1619 * Returns the index where the information field keyword was found or
1620 * -ENOENT otherwise.
1622 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
1623 unsigned int len, const char *kw);
1625 /* PCI <-> OF binding helpers */
1628 extern void pci_set_of_node(struct pci_dev *dev);
1629 extern void pci_release_of_node(struct pci_dev *dev);
1630 extern void pci_set_bus_of_node(struct pci_bus *bus);
1631 extern void pci_release_bus_of_node(struct pci_bus *bus);
1633 /* Arch may override this (weak) */
1634 extern struct device_node * __weak pcibios_get_phb_of_node(struct pci_bus *bus);
1636 static inline struct device_node *pci_device_to_OF_node(struct pci_dev *pdev)
1638 return pdev ? pdev->dev.of_node : NULL;
1641 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
1643 return bus ? bus->dev.of_node : NULL;
1646 #else /* CONFIG_OF */
1647 static inline void pci_set_of_node(struct pci_dev *dev) { }
1648 static inline void pci_release_of_node(struct pci_dev *dev) { }
1649 static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
1650 static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
1651 #endif /* CONFIG_OF */
1654 * pci_find_upstream_pcie_bridge - find upstream PCIe-to-PCI bridge of a device
1655 * @pdev: the PCI device
1657 * if the device is PCIE, return NULL
1658 * if the device isn't connected to a PCIe bridge (that is its parent is a
1659 * legacy PCI bridge and the bridge is directly connected to bus 0), return its
1662 struct pci_dev *pci_find_upstream_pcie_bridge(struct pci_dev *pdev);
1664 #endif /* __KERNEL__ */
1665 #endif /* LINUX_PCI_H */