2 * linux/include/linux/mtd/nand.h
4 * Copyright (c) 2000 David Woodhouse <dwmw2@mvhi.com>
5 * Steven J. Hill <sjhill@realitydiluted.com>
6 * Thomas Gleixner <tglx@linutronix.de>
8 * $Id: nand.h,v 1.74 2005/09/15 13:58:50 vwool Exp $
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 * Contains standard defines and IDs for NAND flash devices
20 #ifndef __LINUX_MTD_NAND_H
21 #define __LINUX_MTD_NAND_H
23 #include <linux/config.h>
24 #include <linux/wait.h>
25 #include <linux/spinlock.h>
26 #include <linux/mtd/mtd.h>
29 /* Scan and identify a NAND device */
30 extern int nand_scan (struct mtd_info *mtd, int max_chips);
31 /* Free resources held by the NAND device */
32 extern void nand_release (struct mtd_info *mtd);
34 /* The maximum number of NAND chips in an array */
35 #define NAND_MAX_CHIPS 8
37 /* This constant declares the max. oobsize / page, which
38 * is supported now. If you add a chip with bigger oobsize/page
39 * adjust this accordingly.
41 #define NAND_MAX_OOBSIZE 64
42 #define NAND_MAX_PAGESIZE 2048
45 * Constants for hardware specific CLE/ALE/NCE function
47 * These are bits which can be or'ed to set/clear multiple
50 /* Select the chip by setting nCE to low */
52 /* Select the command latch by setting CLE to high */
54 /* Select the address latch by setting ALE to high */
57 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
58 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
59 #define NAND_CTRL_CHANGE 0x80
62 * Standard NAND flash commands
64 #define NAND_CMD_READ0 0
65 #define NAND_CMD_READ1 1
66 #define NAND_CMD_RNDOUT 5
67 #define NAND_CMD_PAGEPROG 0x10
68 #define NAND_CMD_READOOB 0x50
69 #define NAND_CMD_ERASE1 0x60
70 #define NAND_CMD_STATUS 0x70
71 #define NAND_CMD_STATUS_MULTI 0x71
72 #define NAND_CMD_SEQIN 0x80
73 #define NAND_CMD_RNDIN 0x85
74 #define NAND_CMD_READID 0x90
75 #define NAND_CMD_ERASE2 0xd0
76 #define NAND_CMD_RESET 0xff
78 /* Extended commands for large page devices */
79 #define NAND_CMD_READSTART 0x30
80 #define NAND_CMD_RNDOUTSTART 0xE0
81 #define NAND_CMD_CACHEDPROG 0x15
83 /* Extended commands for AG-AND device */
85 * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but
86 * there is no way to distinguish that from NAND_CMD_READ0
87 * until the remaining sequence of commands has been completed
88 * so add a high order bit and mask it off in the command.
90 #define NAND_CMD_DEPLETE1 0x100
91 #define NAND_CMD_DEPLETE2 0x38
92 #define NAND_CMD_STATUS_MULTI 0x71
93 #define NAND_CMD_STATUS_ERROR 0x72
94 /* multi-bank error status (banks 0-3) */
95 #define NAND_CMD_STATUS_ERROR0 0x73
96 #define NAND_CMD_STATUS_ERROR1 0x74
97 #define NAND_CMD_STATUS_ERROR2 0x75
98 #define NAND_CMD_STATUS_ERROR3 0x76
99 #define NAND_CMD_STATUS_RESET 0x7f
100 #define NAND_CMD_STATUS_CLEAR 0xff
102 #define NAND_CMD_NONE -1
105 #define NAND_STATUS_FAIL 0x01
106 #define NAND_STATUS_FAIL_N1 0x02
107 #define NAND_STATUS_TRUE_READY 0x20
108 #define NAND_STATUS_READY 0x40
109 #define NAND_STATUS_WP 0x80
112 * Constants for ECC_MODES
118 NAND_ECC_HW_SYNDROME,
122 * Constants for Hardware ECC
124 /* Reset Hardware ECC for read */
125 #define NAND_ECC_READ 0
126 /* Reset Hardware ECC for write */
127 #define NAND_ECC_WRITE 1
128 /* Enable Hardware ECC before syndrom is read back from flash */
129 #define NAND_ECC_READSYN 2
131 /* Bit mask for flags passed to do_nand_read_ecc */
132 #define NAND_GET_DEVICE 0x80
135 /* Option constants for bizarre disfunctionality and real
138 /* Chip can not auto increment pages */
139 #define NAND_NO_AUTOINCR 0x00000001
140 /* Buswitdh is 16 bit */
141 #define NAND_BUSWIDTH_16 0x00000002
142 /* Device supports partial programming without padding */
143 #define NAND_NO_PADDING 0x00000004
144 /* Chip has cache program function */
145 #define NAND_CACHEPRG 0x00000008
146 /* Chip has copy back function */
147 #define NAND_COPYBACK 0x00000010
148 /* AND Chip which has 4 banks and a confusing page / block
149 * assignment. See Renesas datasheet for further information */
150 #define NAND_IS_AND 0x00000020
151 /* Chip has a array of 4 pages which can be read without
152 * additional ready /busy waits */
153 #define NAND_4PAGE_ARRAY 0x00000040
154 /* Chip requires that BBT is periodically rewritten to prevent
155 * bits from adjacent blocks from 'leaking' in altering data.
156 * This happens with the Renesas AG-AND chips, possibly others. */
157 #define BBT_AUTO_REFRESH 0x00000080
158 /* Chip does not require ready check on read. True
159 * for all large page devices, as they do not support
161 #define NAND_NO_READRDY 0x00000100
163 /* Options valid for Samsung large page devices */
164 #define NAND_SAMSUNG_LP_OPTIONS \
165 (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK)
167 /* Macros to identify the above */
168 #define NAND_CANAUTOINCR(chip) (!(chip->options & NAND_NO_AUTOINCR))
169 #define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING))
170 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
171 #define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK))
173 /* Mask to zero out the chip options, which come from the id table */
174 #define NAND_CHIPOPTIONS_MSK (0x0000ffff & ~NAND_NO_AUTOINCR)
176 /* Non chip related options */
177 /* Use a flash based bad block table. This option is passed to the
178 * default bad block table function. */
179 #define NAND_USE_FLASH_BBT 0x00010000
180 /* This option skips the bbt scan during initialization. */
181 #define NAND_SKIP_BBTSCAN 0x00020000
183 /* Options set by nand scan */
184 /* Nand scan has allocated controller struct */
185 #define NAND_CONTROLLER_ALLOC 0x80000000
189 * nand_state_t - chip states
190 * Enumeration for NAND flash chip state
206 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independend devices
207 * @lock: protection lock
208 * @active: the mtd device which holds the controller currently
209 * @wq: wait queue to sleep on if a NAND operation is in progress
210 * used instead of the per chip wait queue when a hw controller is available
212 struct nand_hw_control {
214 struct nand_chip *active;
215 wait_queue_head_t wq;
219 * struct nand_ecc_ctrl - Control structure for ecc
221 * @steps: number of ecc steps per page
222 * @size: data bytes per ecc step
223 * @bytes: ecc bytes per step
224 * @total: total number of ecc bytes per page
225 * @prepad: padding information for syndrome based ecc generators
226 * @postpad: padding information for syndrome based ecc generators
227 * @hwctl: function to control hardware ecc generator. Must only
228 * be provided if an hardware ECC is available
229 * @calculate: function for ecc calculation or readback from ecc hardware
230 * @correct: function for ecc correction, matching to ecc generator (sw/hw)
231 * @read_page: function to read a page according to the ecc generator requirements
232 * @write_page: function to write a page according to the ecc generator requirements
234 struct nand_ecc_ctrl {
235 nand_ecc_modes_t mode;
242 struct nand_ecclayout *layout;
243 void (*hwctl)(struct mtd_info *mtd, int mode);
244 int (*calculate)(struct mtd_info *mtd,
247 int (*correct)(struct mtd_info *mtd, uint8_t *dat,
250 int (*read_page)(struct mtd_info *mtd,
251 struct nand_chip *chip,
253 void (*write_page)(struct mtd_info *mtd,
254 struct nand_chip *chip,
256 int (*read_oob)(struct mtd_info *mtd,
257 struct nand_chip *chip,
260 int (*write_oob)(struct mtd_info *mtd,
261 struct nand_chip *chip,
266 * struct nand_buffers - buffer structure for read/write
267 * @ecccalc: buffer for calculated ecc
268 * @ecccode: buffer for ecc read from flash
269 * @oobwbuf: buffer for write oob data
270 * @databuf: buffer for data - dynamically sized
271 * @oobrbuf: buffer to read oob data
273 * Do not change the order of buffers. databuf and oobrbuf must be in
276 struct nand_buffers {
277 uint8_t ecccalc[NAND_MAX_OOBSIZE];
278 uint8_t ecccode[NAND_MAX_OOBSIZE];
279 uint8_t oobwbuf[NAND_MAX_OOBSIZE];
280 uint8_t databuf[NAND_MAX_PAGESIZE];
281 uint8_t oobrbuf[NAND_MAX_OOBSIZE];
285 * struct nand_chip - NAND Private Flash Chip Data
286 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device
287 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device
288 * @read_byte: [REPLACEABLE] read one byte from the chip
289 * @read_word: [REPLACEABLE] read one word from the chip
290 * @write_buf: [REPLACEABLE] write data from the buffer to the chip
291 * @read_buf: [REPLACEABLE] read data from the chip into the buffer
292 * @verify_buf: [REPLACEABLE] verify buffer contents against the chip data
293 * @select_chip: [REPLACEABLE] select chip nr
294 * @block_bad: [REPLACEABLE] check, if the block is bad
295 * @block_markbad: [REPLACEABLE] mark the block bad
296 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific funtion for controlling
297 * ALE/CLE/nCE. Also used to write command and address
298 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line
299 * If set to NULL no access to ready/busy is available and the ready/busy information
300 * is read from the chip status register
301 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing commands to the chip
302 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on ready
303 * @ecc: [BOARDSPECIFIC] ecc control ctructure
304 * @erase_cmd: [INTERN] erase command write function, selectable due to AND support
305 * @scan_bbt: [REPLACEABLE] function to scan bad block table
306 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR)
307 * @wq: [INTERN] wait queue to sleep on if a NAND operation is in progress
308 * @state: [INTERN] the current state of the NAND device
309 * @page_shift: [INTERN] number of address bits in a page (column address bits)
310 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
311 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
312 * @chip_shift: [INTERN] number of address bits in one chip
313 * @datbuf: [INTERN] internal buffer for one page + oob
314 * @oobbuf: [INTERN] oob buffer for one eraseblock
315 * @oobdirty: [INTERN] indicates that oob_buf must be reinitialized
316 * @data_poi: [INTERN] pointer to a data buffer
317 * @options: [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about
318 * special functionality. See the defines for further explanation
319 * @badblockpos: [INTERN] position of the bad block marker in the oob area
320 * @numchips: [INTERN] number of physical chips
321 * @chipsize: [INTERN] the size of one chip for multichip arrays
322 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
323 * @pagebuf: [INTERN] holds the pagenumber which is currently in data_buf
324 * @ecclayout: [REPLACEABLE] the default ecc placement scheme
325 * @bbt: [INTERN] bad block table pointer
326 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash lookup
327 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor
328 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial bad block scan
329 * @controller: [REPLACEABLE] a pointer to a hardware controller structure
330 * which is shared among multiple independend devices
331 * @priv: [OPTIONAL] pointer to private chip date
332 * @errstat: [OPTIONAL] hardware specific function to perform additional error status checks
333 * (determine if errors are correctable)
337 void __iomem *IO_ADDR_R;
338 void __iomem *IO_ADDR_W;
340 uint8_t (*read_byte)(struct mtd_info *mtd);
341 u16 (*read_word)(struct mtd_info *mtd);
342 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
343 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
344 int (*verify_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
345 void (*select_chip)(struct mtd_info *mtd, int chip);
346 int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
347 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
348 void (*cmd_ctrl)(struct mtd_info *mtd, int dat,
350 int (*dev_ready)(struct mtd_info *mtd);
351 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, int page_addr);
352 int (*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
353 void (*erase_cmd)(struct mtd_info *mtd, int page);
354 int (*scan_bbt)(struct mtd_info *mtd);
355 int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state, int status, int page);
358 unsigned int options;
361 int phys_erase_shift;
365 unsigned long chipsize;
373 struct nand_hw_control *controller;
374 struct nand_ecclayout *ecclayout;
376 struct nand_ecc_ctrl ecc;
377 struct nand_buffers buffers;
378 struct nand_hw_control hwcontrol;
380 struct mtd_oob_ops ops;
383 struct nand_bbt_descr *bbt_td;
384 struct nand_bbt_descr *bbt_md;
386 struct nand_bbt_descr *badblock_pattern;
392 * NAND Flash Manufacturer ID Codes
394 #define NAND_MFR_TOSHIBA 0x98
395 #define NAND_MFR_SAMSUNG 0xec
396 #define NAND_MFR_FUJITSU 0x04
397 #define NAND_MFR_NATIONAL 0x8f
398 #define NAND_MFR_RENESAS 0x07
399 #define NAND_MFR_STMICRO 0x20
400 #define NAND_MFR_HYNIX 0xad
403 * struct nand_flash_dev - NAND Flash Device ID Structure
405 * @name: Identify the device type
406 * @id: device ID code
407 * @pagesize: Pagesize in bytes. Either 256 or 512 or 0
408 * If the pagesize is 0, then the real pagesize
409 * and the eraseize are determined from the
410 * extended id bytes in the chip
411 * @erasesize: Size of an erase block in the flash device.
412 * @chipsize: Total chipsize in Mega Bytes
413 * @options: Bitfield to store chip relevant options
415 struct nand_flash_dev {
418 unsigned long pagesize;
419 unsigned long chipsize;
420 unsigned long erasesize;
421 unsigned long options;
425 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
426 * @name: Manufacturer name
427 * @id: manufacturer ID code of device.
429 struct nand_manufacturers {
434 extern struct nand_flash_dev nand_flash_ids[];
435 extern struct nand_manufacturers nand_manuf_ids[];
438 * struct nand_bbt_descr - bad block table descriptor
439 * @options: options for this descriptor
440 * @pages: the page(s) where we find the bbt, used with option BBT_ABSPAGE
441 * when bbt is searched, then we store the found bbts pages here.
442 * Its an array and supports up to 8 chips now
443 * @offs: offset of the pattern in the oob area of the page
444 * @veroffs: offset of the bbt version counter in the oob are of the page
445 * @version: version read from the bbt page during scan
446 * @len: length of the pattern, if 0 no pattern check is performed
447 * @maxblocks: maximum number of blocks to search for a bbt. This number of
448 * blocks is reserved at the end of the device where the tables are
450 * @reserved_block_code: if non-0, this pattern denotes a reserved (rather than
451 * bad) block in the stored bbt
452 * @pattern: pattern to identify bad block table or factory marked good /
453 * bad blocks, can be NULL, if len = 0
455 * Descriptor for the bad block table marker and the descriptor for the
456 * pattern which identifies good and bad blocks. The assumption is made
457 * that the pattern and the version count are always located in the oob area
458 * of the first block.
460 struct nand_bbt_descr {
462 int pages[NAND_MAX_CHIPS];
465 uint8_t version[NAND_MAX_CHIPS];
468 int reserved_block_code;
472 /* Options for the bad block table descriptors */
474 /* The number of bits used per block in the bbt on the device */
475 #define NAND_BBT_NRBITS_MSK 0x0000000F
476 #define NAND_BBT_1BIT 0x00000001
477 #define NAND_BBT_2BIT 0x00000002
478 #define NAND_BBT_4BIT 0x00000004
479 #define NAND_BBT_8BIT 0x00000008
480 /* The bad block table is in the last good block of the device */
481 #define NAND_BBT_LASTBLOCK 0x00000010
482 /* The bbt is at the given page, else we must scan for the bbt */
483 #define NAND_BBT_ABSPAGE 0x00000020
484 /* The bbt is at the given page, else we must scan for the bbt */
485 #define NAND_BBT_SEARCH 0x00000040
486 /* bbt is stored per chip on multichip devices */
487 #define NAND_BBT_PERCHIP 0x00000080
488 /* bbt has a version counter at offset veroffs */
489 #define NAND_BBT_VERSION 0x00000100
490 /* Create a bbt if none axists */
491 #define NAND_BBT_CREATE 0x00000200
492 /* Search good / bad pattern through all pages of a block */
493 #define NAND_BBT_SCANALLPAGES 0x00000400
494 /* Scan block empty during good / bad block scan */
495 #define NAND_BBT_SCANEMPTY 0x00000800
496 /* Write bbt if neccecary */
497 #define NAND_BBT_WRITE 0x00001000
498 /* Read and write back block contents when writing bbt */
499 #define NAND_BBT_SAVECONTENT 0x00002000
500 /* Search good / bad pattern on the first and the second page */
501 #define NAND_BBT_SCAN2NDPAGE 0x00004000
503 /* The maximum number of blocks to scan for a bbt */
504 #define NAND_BBT_SCAN_MAXBLOCKS 4
506 extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd);
507 extern int nand_update_bbt(struct mtd_info *mtd, loff_t offs);
508 extern int nand_default_bbt(struct mtd_info *mtd);
509 extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
510 extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
512 extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
513 size_t * retlen, uint8_t * buf);
516 * Constants for oob configuration
518 #define NAND_SMALL_BADBLOCK_POS 5
519 #define NAND_LARGE_BADBLOCK_POS 0
522 * struct platform_nand_chip - chip level device structure
524 * @nr_chips: max. number of chips to scan for
525 * @chip_offs: chip number offset
526 * @nr_partitions: number of partitions pointed to by partitions (or zero)
527 * @partitions: mtd partition list
528 * @chip_delay: R/B delay value in us
529 * @options: Option flags, e.g. 16bit buswidth
530 * @ecclayout: ecc layout info structure
531 * @priv: hardware controller specific settings
533 struct platform_nand_chip {
537 struct mtd_partition *partitions;
538 struct nand_ecclayout *ecclayout;
540 unsigned int options;
545 * struct platform_nand_ctrl - controller level device structure
547 * @hwcontrol: platform specific hardware control structure
548 * @dev_ready: platform specific function to read ready/busy pin
549 * @select_chip: platform specific chip select function
550 * @priv_data: private data to transport driver specific settings
552 * All fields are optional and depend on the hardware driver requirements
554 struct platform_nand_ctrl {
555 void (*hwcontrol)(struct mtd_info *mtd, int cmd);
556 int (*dev_ready)(struct mtd_info *mtd);
557 void (*select_chip)(struct mtd_info *mtd, int chip);
561 /* Some helpers to access the data structures */
563 struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd)
565 struct nand_chip *chip = mtd->priv;
570 #endif /* __LINUX_MTD_NAND_H */