2 * include/linux/mmc/sh_mmcif.h
4 * platform data for eMMC driver
6 * Copyright (C) 2010 Renesas Solutions Corp.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License.
14 #ifndef LINUX_MMC_SH_MMCIF_H
15 #define LINUX_MMC_SH_MMCIF_H
18 #include <linux/platform_device.h>
19 #include <linux/sh_dma.h>
22 * MMCIF : CE_CLK_CTRL [19:16]
23 * 1000 : Peripheral clock / 512
24 * 0111 : Peripheral clock / 256
25 * 0110 : Peripheral clock / 128
26 * 0101 : Peripheral clock / 64
27 * 0100 : Peripheral clock / 32
28 * 0011 : Peripheral clock / 16
29 * 0010 : Peripheral clock / 8
30 * 0001 : Peripheral clock / 4
31 * 0000 : Peripheral clock / 2
32 * 1111 : Peripheral clock (sup_pclk set '1')
36 struct sh_dmae_slave chan_priv_tx;
37 struct sh_dmae_slave chan_priv_rx;
40 struct sh_mmcif_plat_data {
41 void (*set_pwr)(struct platform_device *pdev, int state);
42 void (*down_pwr)(struct platform_device *pdev);
43 int (*get_cd)(struct platform_device *pdef);
44 struct sh_mmcif_dma *dma; /* Deprecated. Instead */
45 unsigned int slave_id_tx; /* use embedded slave_id_[tr]x */
46 unsigned int slave_id_rx;
47 u8 sup_pclk; /* 1 :SH7757, 0: SH7724/SH7372 */
52 #define MMCIF_CE_CMD_SET 0x00000000
53 #define MMCIF_CE_ARG 0x00000008
54 #define MMCIF_CE_ARG_CMD12 0x0000000C
55 #define MMCIF_CE_CMD_CTRL 0x00000010
56 #define MMCIF_CE_BLOCK_SET 0x00000014
57 #define MMCIF_CE_CLK_CTRL 0x00000018
58 #define MMCIF_CE_BUF_ACC 0x0000001C
59 #define MMCIF_CE_RESP3 0x00000020
60 #define MMCIF_CE_RESP2 0x00000024
61 #define MMCIF_CE_RESP1 0x00000028
62 #define MMCIF_CE_RESP0 0x0000002C
63 #define MMCIF_CE_RESP_CMD12 0x00000030
64 #define MMCIF_CE_DATA 0x00000034
65 #define MMCIF_CE_INT 0x00000040
66 #define MMCIF_CE_INT_MASK 0x00000044
67 #define MMCIF_CE_HOST_STS1 0x00000048
68 #define MMCIF_CE_HOST_STS2 0x0000004C
69 #define MMCIF_CE_VERSION 0x0000007C
72 #define BUF_ACC_DMAWEN (1 << 25)
73 #define BUF_ACC_DMAREN (1 << 24)
74 #define BUF_ACC_BUSW_32 (0 << 17)
75 #define BUF_ACC_BUSW_16 (1 << 17)
76 #define BUF_ACC_ATYP (1 << 16)
79 #define CLK_ENABLE (1 << 24) /* 1: output mmc clock */
80 #define CLK_CLEAR (0xf << 16)
81 #define CLK_SUP_PCLK (0xf << 16)
82 #define CLKDIV_4 (1 << 16) /* mmc clock frequency.
83 * n: bus clock/(2^(n+1)) */
84 #define CLKDIV_256 (7 << 16) /* mmc clock frequency. (see above) */
85 #define SRSPTO_256 (2 << 12) /* resp timeout */
86 #define SRBSYTO_29 (0xf << 8) /* resp busy timeout */
87 #define SRWDTO_29 (0xf << 4) /* read/write timeout */
88 #define SCCSTO_29 (0xf << 0) /* ccs timeout */
91 #define SOFT_RST_ON (1 << 31)
92 #define SOFT_RST_OFF 0
94 static inline u32 sh_mmcif_readl(void __iomem *addr, int reg)
96 return __raw_readl(addr + reg);
99 static inline void sh_mmcif_writel(void __iomem *addr, int reg, u32 val)
101 __raw_writel(val, addr + reg);
104 #define SH_MMCIF_BBS 512 /* boot block size */
106 static inline void sh_mmcif_boot_cmd_send(void __iomem *base,
107 unsigned long cmd, unsigned long arg)
109 sh_mmcif_writel(base, MMCIF_CE_INT, 0);
110 sh_mmcif_writel(base, MMCIF_CE_ARG, arg);
111 sh_mmcif_writel(base, MMCIF_CE_CMD_SET, cmd);
114 static inline int sh_mmcif_boot_cmd_poll(void __iomem *base, unsigned long mask)
119 for (cnt = 0; cnt < 1000000; cnt++) {
120 tmp = sh_mmcif_readl(base, MMCIF_CE_INT);
122 sh_mmcif_writel(base, MMCIF_CE_INT, tmp & ~mask);
130 static inline int sh_mmcif_boot_cmd(void __iomem *base,
131 unsigned long cmd, unsigned long arg)
133 sh_mmcif_boot_cmd_send(base, cmd, arg);
134 return sh_mmcif_boot_cmd_poll(base, 0x00010000);
137 static inline int sh_mmcif_boot_do_read_single(void __iomem *base,
138 unsigned int block_nr,
144 sh_mmcif_boot_cmd(base, 0x0d400000, 0x00010000);
146 if (sh_mmcif_readl(base, MMCIF_CE_RESP0) != 0x0900)
150 sh_mmcif_boot_cmd(base, 0x11480000, block_nr * SH_MMCIF_BBS);
151 if (sh_mmcif_boot_cmd_poll(base, 0x00100000) < 0)
154 for (k = 0; k < (SH_MMCIF_BBS / 4); k++)
155 buf[k] = sh_mmcif_readl(base, MMCIF_CE_DATA);
160 static inline int sh_mmcif_boot_do_read(void __iomem *base,
161 unsigned long first_block,
162 unsigned long nr_blocks,
168 /* In data transfer mode: Set clock to Bus clock/4 (about 20Mhz) */
169 sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL,
170 CLK_ENABLE | CLKDIV_4 | SRSPTO_256 |
171 SRBSYTO_29 | SRWDTO_29 | SCCSTO_29);
174 sh_mmcif_boot_cmd(base, 0x09806000, 0x00010000);
176 /* CMD7 - Select the card */
177 sh_mmcif_boot_cmd(base, 0x07400000, 0x00010000);
179 /* CMD16 - Set the block size */
180 sh_mmcif_boot_cmd(base, 0x10400000, SH_MMCIF_BBS);
182 for (k = 0; !ret && k < nr_blocks; k++)
183 ret = sh_mmcif_boot_do_read_single(base, first_block + k,
184 buf + (k * SH_MMCIF_BBS));
189 static inline void sh_mmcif_boot_init(void __iomem *base)
192 sh_mmcif_writel(base, MMCIF_CE_VERSION, SOFT_RST_ON);
193 sh_mmcif_writel(base, MMCIF_CE_VERSION, SOFT_RST_OFF);
196 sh_mmcif_writel(base, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP);
198 /* Set block size in MMCIF hardware */
199 sh_mmcif_writel(base, MMCIF_CE_BLOCK_SET, SH_MMCIF_BBS);
201 /* Enable the clock, set it to Bus clock/256 (about 325Khz). */
202 sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL,
203 CLK_ENABLE | CLKDIV_256 | SRSPTO_256 |
204 SRBSYTO_29 | SRWDTO_29 | SCCSTO_29);
207 sh_mmcif_boot_cmd(base, 0x00000040, 0);
211 sh_mmcif_boot_cmd(base, 0x01405040, 0x40300000); /* CMD1 */
212 } while ((sh_mmcif_readl(base, MMCIF_CE_RESP0) & 0x80000000)
216 sh_mmcif_boot_cmd(base, 0x02806040, 0);
218 /* CMD3 - Set card relative address */
219 sh_mmcif_boot_cmd(base, 0x03400040, 0x00010000);
222 #endif /* LINUX_MMC_SH_MMCIF_H */