2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/pci.h>
37 #include <linux/completion.h>
38 #include <linux/radix-tree.h>
40 #include <asm/atomic.h>
43 MLX4_FLAG_MSI_X = 1 << 0,
44 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1,
52 MLX4_BOARD_ID_LEN = 64
56 MLX4_DEV_CAP_FLAG_RC = 1 << 0,
57 MLX4_DEV_CAP_FLAG_UC = 1 << 1,
58 MLX4_DEV_CAP_FLAG_UD = 1 << 2,
59 MLX4_DEV_CAP_FLAG_SRQ = 1 << 6,
60 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1 << 7,
61 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1 << 8,
62 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1 << 9,
63 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1 << 16,
64 MLX4_DEV_CAP_FLAG_APM = 1 << 17,
65 MLX4_DEV_CAP_FLAG_ATOMIC = 1 << 18,
66 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1 << 19,
67 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1 << 20,
68 MLX4_DEV_CAP_FLAG_UD_MCAST = 1 << 21
72 MLX4_EVENT_TYPE_COMP = 0x00,
73 MLX4_EVENT_TYPE_PATH_MIG = 0x01,
74 MLX4_EVENT_TYPE_COMM_EST = 0x02,
75 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03,
76 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13,
77 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14,
78 MLX4_EVENT_TYPE_CQ_ERROR = 0x04,
79 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
80 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06,
81 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
82 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
83 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
84 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
85 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08,
86 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09,
87 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f,
88 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e,
89 MLX4_EVENT_TYPE_CMD = 0x0a
93 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1,
94 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4
98 MLX4_PERM_LOCAL_READ = 1 << 10,
99 MLX4_PERM_LOCAL_WRITE = 1 << 11,
100 MLX4_PERM_REMOTE_READ = 1 << 12,
101 MLX4_PERM_REMOTE_WRITE = 1 << 13,
102 MLX4_PERM_ATOMIC = 1 << 14
106 MLX4_OPCODE_NOP = 0x00,
107 MLX4_OPCODE_SEND_INVAL = 0x01,
108 MLX4_OPCODE_RDMA_WRITE = 0x08,
109 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09,
110 MLX4_OPCODE_SEND = 0x0a,
111 MLX4_OPCODE_SEND_IMM = 0x0b,
112 MLX4_OPCODE_LSO = 0x0e,
113 MLX4_OPCODE_RDMA_READ = 0x10,
114 MLX4_OPCODE_ATOMIC_CS = 0x11,
115 MLX4_OPCODE_ATOMIC_FA = 0x12,
116 MLX4_OPCODE_ATOMIC_MASK_CS = 0x14,
117 MLX4_OPCODE_ATOMIC_MASK_FA = 0x15,
118 MLX4_OPCODE_BIND_MW = 0x18,
119 MLX4_OPCODE_FMR = 0x19,
120 MLX4_OPCODE_LOCAL_INVAL = 0x1b,
121 MLX4_OPCODE_CONFIG_CMD = 0x1f,
123 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
124 MLX4_RECV_OPCODE_SEND = 0x01,
125 MLX4_RECV_OPCODE_SEND_IMM = 0x02,
126 MLX4_RECV_OPCODE_SEND_INVAL = 0x03,
128 MLX4_CQE_OPCODE_ERROR = 0x1e,
129 MLX4_CQE_OPCODE_RESIZE = 0x16,
133 MLX4_STAT_RATE_OFFSET = 5
136 static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
138 return (major << 32) | (minor << 16) | subminor;
144 int vl_cap[MLX4_MAX_PORTS + 1];
145 int mtu_cap[MLX4_MAX_PORTS + 1];
146 int gid_table_len[MLX4_MAX_PORTS + 1];
147 int pkey_table_len[MLX4_MAX_PORTS + 1];
148 int local_ca_ack_delay;
151 int bf_regs_per_page;
158 int max_qp_init_rdma;
159 int max_qp_dest_rdma;
173 int fmr_reserved_mtts;
187 u16 stat_rate_support;
188 u8 port_width_cap[MLX4_MAX_PORTS + 1];
192 struct mlx4_buf_list {
198 struct mlx4_buf_list direct;
199 struct mlx4_buf_list *page_list;
212 MLX4_DB_PER_PAGE = PAGE_SIZE / 4
215 struct mlx4_db_pgdir {
216 struct list_head list;
217 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE);
218 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2);
219 unsigned long *bits[2];
224 struct mlx4_ib_user_db_page;
229 struct mlx4_db_pgdir *pgdir;
230 struct mlx4_ib_user_db_page *user_page;
237 struct mlx4_hwq_resources {
255 struct mlx4_mpt_entry *mpt;
257 dma_addr_t dma_handle;
270 void (*comp) (struct mlx4_cq *);
271 void (*event) (struct mlx4_cq *, enum mlx4_event);
273 struct mlx4_uar *uar;
284 struct completion free;
288 void (*event) (struct mlx4_qp *, enum mlx4_event);
293 struct completion free;
297 void (*event) (struct mlx4_srq *, enum mlx4_event);
305 struct completion free;
317 __be32 sl_tclass_flowlabel;
322 struct pci_dev *pdev;
324 struct mlx4_caps caps;
325 struct radix_tree_root qp_table_tree;
327 char board_id[MLX4_BOARD_ID_LEN];
330 struct mlx4_init_port_param {
344 int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
345 struct mlx4_buf *buf);
346 void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf);
347 static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset)
349 if (BITS_PER_LONG == 64 || buf->nbufs == 1)
350 return buf->direct.buf + offset;
352 return buf->page_list[offset >> PAGE_SHIFT].buf +
353 (offset & (PAGE_SIZE - 1));
356 int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn);
357 void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);
359 int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar);
360 void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar);
362 int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
363 struct mlx4_mtt *mtt);
364 void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
365 u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
367 int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
368 int npages, int page_shift, struct mlx4_mr *mr);
369 void mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr);
370 int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr);
371 int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
372 int start_index, int npages, u64 *page_list);
373 int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
374 struct mlx4_buf *buf);
376 int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order);
377 void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db);
379 int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres,
380 int size, int max_direct);
381 void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres,
384 int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
385 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq,
387 void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq);
389 int mlx4_qp_alloc(struct mlx4_dev *dev, int sqpn, struct mlx4_qp *qp);
390 void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp);
392 int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, struct mlx4_mtt *mtt,
393 u64 db_rec, struct mlx4_srq *srq);
394 void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq);
395 int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark);
396 int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark);
398 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
399 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);
401 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
402 int block_mcast_loopback);
403 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16]);
405 int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
406 int npages, u64 iova, u32 *lkey, u32 *rkey);
407 int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
408 int max_maps, u8 page_shift, struct mlx4_fmr *fmr);
409 int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
410 void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
411 u32 *lkey, u32 *rkey);
412 int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
413 int mlx4_SYNC_TPT(struct mlx4_dev *dev);
415 #endif /* MLX4_DEVICE_H */