2 * twl4030.h - header for TWL4030 PM and audio CODEC device
4 * Copyright (C) 2005-2006 Texas Instruments, Inc.
6 * Based on tlv320aic23.c:
7 * Copyright (c) by Kai Svahn <kai.svahn@nokia.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
28 #include <linux/types.h>
29 #include <linux/input/matrix_keypad.h>
32 * Using the twl4030 core we address registers using a pair
33 * { module id, relative register offset }
34 * which that core then maps to the relevant
35 * { i2c slave, absolute register address }
37 * The module IDs are meaningful only to the twl4030 core code,
38 * which uses them as array indices to look up the first register
39 * address each module uses within a given i2c slave.
42 /* Slave 0 (i2c address 0x48) */
43 #define TWL4030_MODULE_USB 0x00
45 /* Slave 1 (i2c address 0x49) */
46 #define TWL4030_MODULE_AUDIO_VOICE 0x01
47 #define TWL4030_MODULE_GPIO 0x02
48 #define TWL4030_MODULE_INTBR 0x03
49 #define TWL4030_MODULE_PIH 0x04
50 #define TWL4030_MODULE_TEST 0x05
52 /* Slave 2 (i2c address 0x4a) */
53 #define TWL4030_MODULE_KEYPAD 0x06
54 #define TWL4030_MODULE_MADC 0x07
55 #define TWL4030_MODULE_INTERRUPTS 0x08
56 #define TWL4030_MODULE_LED 0x09
57 #define TWL4030_MODULE_MAIN_CHARGE 0x0A
58 #define TWL4030_MODULE_PRECHARGE 0x0B
59 #define TWL4030_MODULE_PWM0 0x0C
60 #define TWL4030_MODULE_PWM1 0x0D
61 #define TWL4030_MODULE_PWMA 0x0E
62 #define TWL4030_MODULE_PWMB 0x0F
64 #define TWL5031_MODULE_ACCESSORY 0x10
65 #define TWL5031_MODULE_INTERRUPTS 0x11
67 /* Slave 3 (i2c address 0x4b) */
68 #define TWL4030_MODULE_BACKUP 0x12
69 #define TWL4030_MODULE_INT 0x13
70 #define TWL4030_MODULE_PM_MASTER 0x14
71 #define TWL4030_MODULE_PM_RECEIVER 0x15
72 #define TWL4030_MODULE_RTC 0x16
73 #define TWL4030_MODULE_SECURED_REG 0x17
75 #define TWL_MODULE_USB TWL4030_MODULE_USB
76 #define TWL_MODULE_AUDIO_VOICE TWL4030_MODULE_AUDIO_VOICE
77 #define TWL_MODULE_PIH TWL4030_MODULE_PIH
78 #define TWL_MODULE_MADC TWL4030_MODULE_MADC
79 #define TWL_MODULE_MAIN_CHARGE TWL4030_MODULE_MAIN_CHARGE
80 #define TWL_MODULE_PM_MASTER TWL4030_MODULE_PM_MASTER
81 #define TWL_MODULE_PM_RECEIVER TWL4030_MODULE_PM_RECEIVER
82 #define TWL_MODULE_RTC TWL4030_MODULE_RTC
83 #define TWL_MODULE_PWM TWL4030_MODULE_PWM0
85 #define TWL6030_MODULE_ID0 0x0D
86 #define TWL6030_MODULE_ID1 0x0E
87 #define TWL6030_MODULE_ID2 0x0F
89 #define GPIO_INTR_OFFSET 0
90 #define KEYPAD_INTR_OFFSET 1
91 #define BCI_INTR_OFFSET 2
92 #define MADC_INTR_OFFSET 3
93 #define USB_INTR_OFFSET 4
94 #define CHARGERFAULT_INTR_OFFSET 5
95 #define BCI_PRES_INTR_OFFSET 9
96 #define USB_PRES_INTR_OFFSET 10
97 #define RTC_INTR_OFFSET 11
100 * Offset from TWL6030_IRQ_BASE / pdata->irq_base
102 #define PWR_INTR_OFFSET 0
103 #define HOTDIE_INTR_OFFSET 12
104 #define SMPSLDO_INTR_OFFSET 13
105 #define BATDETECT_INTR_OFFSET 14
106 #define SIMDETECT_INTR_OFFSET 15
107 #define MMCDETECT_INTR_OFFSET 16
108 #define GASGAUGE_INTR_OFFSET 17
109 #define USBOTG_INTR_OFFSET 4
110 #define CHARGER_INTR_OFFSET 2
111 #define RSV_INTR_OFFSET 0
113 /* INT register offsets */
114 #define REG_INT_STS_A 0x00
115 #define REG_INT_STS_B 0x01
116 #define REG_INT_STS_C 0x02
118 #define REG_INT_MSK_LINE_A 0x03
119 #define REG_INT_MSK_LINE_B 0x04
120 #define REG_INT_MSK_LINE_C 0x05
122 #define REG_INT_MSK_STS_A 0x06
123 #define REG_INT_MSK_STS_B 0x07
124 #define REG_INT_MSK_STS_C 0x08
126 /* MASK INT REG GROUP A */
127 #define TWL6030_PWR_INT_MASK 0x07
128 #define TWL6030_RTC_INT_MASK 0x18
129 #define TWL6030_HOTDIE_INT_MASK 0x20
130 #define TWL6030_SMPSLDOA_INT_MASK 0xC0
132 /* MASK INT REG GROUP B */
133 #define TWL6030_SMPSLDOB_INT_MASK 0x01
134 #define TWL6030_BATDETECT_INT_MASK 0x02
135 #define TWL6030_SIMDETECT_INT_MASK 0x04
136 #define TWL6030_MMCDETECT_INT_MASK 0x08
137 #define TWL6030_GPADC_INT_MASK 0x60
138 #define TWL6030_GASGAUGE_INT_MASK 0x80
140 /* MASK INT REG GROUP C */
141 #define TWL6030_USBOTG_INT_MASK 0x0F
142 #define TWL6030_CHARGER_CTRL_INT_MASK 0x10
143 #define TWL6030_CHARGER_FAULT_INT_MASK 0x60
145 #define TWL6030_MMCCTRL 0xEE
146 #define VMMC_AUTO_OFF (0x1 << 3)
147 #define SW_FC (0x1 << 2)
150 #define TWL6030_CFG_INPUT_PUPD3 0xF2
151 #define MMC_PU (0x1 << 3)
152 #define MMC_PD (0x1 << 2)
154 #define TWL_SIL_TYPE(rev) ((rev) & 0x00FFFFFF)
155 #define TWL_SIL_REV(rev) ((rev) >> 24)
156 #define TWL_SIL_5030 0x09002F
157 #define TWL5030_REV_1_0 0x00
158 #define TWL5030_REV_1_1 0x10
159 #define TWL5030_REV_1_2 0x30
161 #define TWL4030_CLASS_ID 0x4030
162 #define TWL6030_CLASS_ID 0x6030
163 unsigned int twl_rev(void);
164 #define GET_TWL_REV (twl_rev())
165 #define TWL_CLASS_IS(class, id) \
166 static inline int twl_class_is_ ##class(void) \
168 return ((id) == (GET_TWL_REV)) ? 1 : 0; \
171 TWL_CLASS_IS(4030, TWL4030_CLASS_ID)
172 TWL_CLASS_IS(6030, TWL6030_CLASS_ID)
174 #define TWL6025_SUBCLASS BIT(4) /* TWL6025 has changed registers */
177 * Read and write single 8-bit registers
179 int twl_i2c_write_u8(u8 mod_no, u8 val, u8 reg);
180 int twl_i2c_read_u8(u8 mod_no, u8 *val, u8 reg);
181 int twl_i2c_rmw_u8(u8 mod_no, u8 bits_to_clear, u8 bits_to_set, u8 reg);
184 * Read and write several 8-bit registers at once.
186 * IMPORTANT: For twl_i2c_write(), allocate num_bytes + 1
187 * for the value, and populate your data starting at offset 1.
189 int twl_i2c_write(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes);
190 int twl_i2c_read(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes);
192 int twl_get_type(void);
193 int twl_get_version(void);
195 int twl6030_interrupt_unmask(u8 bit_mask, u8 offset);
196 int twl6030_interrupt_mask(u8 bit_mask, u8 offset);
198 /* Card detect Configuration for MMC1 Controller on OMAP4 */
199 #ifdef CONFIG_TWL4030_CORE
200 int twl6030_mmc_card_detect_config(void);
202 static inline int twl6030_mmc_card_detect_config(void)
204 pr_debug("twl6030_mmc_card_detect_config not supported\n");
209 /* MMC1 Controller on OMAP4 uses Phoenix irq for Card detect */
210 #ifdef CONFIG_TWL4030_CORE
211 int twl6030_mmc_card_detect(struct device *dev, int slot);
213 static inline int twl6030_mmc_card_detect(struct device *dev, int slot)
215 pr_debug("Call back twl6030_mmc_card_detect not supported\n");
219 /*----------------------------------------------------------------------*/
222 * NOTE: at up to 1024 registers, this is a big chip.
224 * Avoid putting register declarations in this file, instead of into
225 * a driver-private file, unless some of the registers in a block
226 * need to be shared with other drivers. One example is blocks that
227 * have Secondary IRQ Handler (SIH) registers.
230 #define TWL4030_SIH_CTRL_EXCLEN_MASK BIT(0)
231 #define TWL4030_SIH_CTRL_PENDDIS_MASK BIT(1)
232 #define TWL4030_SIH_CTRL_COR_MASK BIT(2)
234 /*----------------------------------------------------------------------*/
237 * GPIO Block Register offsets (use TWL4030_MODULE_GPIO)
240 #define REG_GPIODATAIN1 0x0
241 #define REG_GPIODATAIN2 0x1
242 #define REG_GPIODATAIN3 0x2
243 #define REG_GPIODATADIR1 0x3
244 #define REG_GPIODATADIR2 0x4
245 #define REG_GPIODATADIR3 0x5
246 #define REG_GPIODATAOUT1 0x6
247 #define REG_GPIODATAOUT2 0x7
248 #define REG_GPIODATAOUT3 0x8
249 #define REG_CLEARGPIODATAOUT1 0x9
250 #define REG_CLEARGPIODATAOUT2 0xA
251 #define REG_CLEARGPIODATAOUT3 0xB
252 #define REG_SETGPIODATAOUT1 0xC
253 #define REG_SETGPIODATAOUT2 0xD
254 #define REG_SETGPIODATAOUT3 0xE
255 #define REG_GPIO_DEBEN1 0xF
256 #define REG_GPIO_DEBEN2 0x10
257 #define REG_GPIO_DEBEN3 0x11
258 #define REG_GPIO_CTRL 0x12
259 #define REG_GPIOPUPDCTR1 0x13
260 #define REG_GPIOPUPDCTR2 0x14
261 #define REG_GPIOPUPDCTR3 0x15
262 #define REG_GPIOPUPDCTR4 0x16
263 #define REG_GPIOPUPDCTR5 0x17
264 #define REG_GPIO_ISR1A 0x19
265 #define REG_GPIO_ISR2A 0x1A
266 #define REG_GPIO_ISR3A 0x1B
267 #define REG_GPIO_IMR1A 0x1C
268 #define REG_GPIO_IMR2A 0x1D
269 #define REG_GPIO_IMR3A 0x1E
270 #define REG_GPIO_ISR1B 0x1F
271 #define REG_GPIO_ISR2B 0x20
272 #define REG_GPIO_ISR3B 0x21
273 #define REG_GPIO_IMR1B 0x22
274 #define REG_GPIO_IMR2B 0x23
275 #define REG_GPIO_IMR3B 0x24
276 #define REG_GPIO_EDR1 0x28
277 #define REG_GPIO_EDR2 0x29
278 #define REG_GPIO_EDR3 0x2A
279 #define REG_GPIO_EDR4 0x2B
280 #define REG_GPIO_EDR5 0x2C
281 #define REG_GPIO_SIH_CTRL 0x2D
283 /* Up to 18 signals are available as GPIOs, when their
284 * pins are not assigned to another use (such as ULPI/USB).
286 #define TWL4030_GPIO_MAX 18
288 /*----------------------------------------------------------------------*/
290 /*Interface Bit Register (INTBR) offsets
291 *(Use TWL_4030_MODULE_INTBR)
294 #define REG_IDCODE_7_0 0x00
295 #define REG_IDCODE_15_8 0x01
296 #define REG_IDCODE_16_23 0x02
297 #define REG_IDCODE_31_24 0x03
298 #define REG_GPPUPDCTR1 0x0F
299 #define REG_UNLOCK_TEST_REG 0x12
301 /*I2C1 and I2C4(SR) SDA/SCL pull-up control bits */
303 #define I2C_SCL_CTRL_PU BIT(0)
304 #define I2C_SDA_CTRL_PU BIT(2)
305 #define SR_I2C_SCL_CTRL_PU BIT(4)
306 #define SR_I2C_SDA_CTRL_PU BIT(6)
308 #define TWL_EEPROM_R_UNLOCK 0x49
310 /*----------------------------------------------------------------------*/
313 * Keypad register offsets (use TWL4030_MODULE_KEYPAD)
314 * ... SIH/interrupt only
317 #define TWL4030_KEYPAD_KEYP_ISR1 0x11
318 #define TWL4030_KEYPAD_KEYP_IMR1 0x12
319 #define TWL4030_KEYPAD_KEYP_ISR2 0x13
320 #define TWL4030_KEYPAD_KEYP_IMR2 0x14
321 #define TWL4030_KEYPAD_KEYP_SIR 0x15 /* test register */
322 #define TWL4030_KEYPAD_KEYP_EDR 0x16
323 #define TWL4030_KEYPAD_KEYP_SIH_CTRL 0x17
325 /*----------------------------------------------------------------------*/
328 * Multichannel ADC register offsets (use TWL4030_MODULE_MADC)
329 * ... SIH/interrupt only
332 #define TWL4030_MADC_ISR1 0x61
333 #define TWL4030_MADC_IMR1 0x62
334 #define TWL4030_MADC_ISR2 0x63
335 #define TWL4030_MADC_IMR2 0x64
336 #define TWL4030_MADC_SIR 0x65 /* test register */
337 #define TWL4030_MADC_EDR 0x66
338 #define TWL4030_MADC_SIH_CTRL 0x67
340 /*----------------------------------------------------------------------*/
343 * Battery charger register offsets (use TWL4030_MODULE_INTERRUPTS)
346 #define TWL4030_INTERRUPTS_BCIISR1A 0x0
347 #define TWL4030_INTERRUPTS_BCIISR2A 0x1
348 #define TWL4030_INTERRUPTS_BCIIMR1A 0x2
349 #define TWL4030_INTERRUPTS_BCIIMR2A 0x3
350 #define TWL4030_INTERRUPTS_BCIISR1B 0x4
351 #define TWL4030_INTERRUPTS_BCIISR2B 0x5
352 #define TWL4030_INTERRUPTS_BCIIMR1B 0x6
353 #define TWL4030_INTERRUPTS_BCIIMR2B 0x7
354 #define TWL4030_INTERRUPTS_BCISIR1 0x8 /* test register */
355 #define TWL4030_INTERRUPTS_BCISIR2 0x9 /* test register */
356 #define TWL4030_INTERRUPTS_BCIEDR1 0xa
357 #define TWL4030_INTERRUPTS_BCIEDR2 0xb
358 #define TWL4030_INTERRUPTS_BCIEDR3 0xc
359 #define TWL4030_INTERRUPTS_BCISIHCTRL 0xd
361 /*----------------------------------------------------------------------*/
364 * Power Interrupt block register offsets (use TWL4030_MODULE_INT)
367 #define TWL4030_INT_PWR_ISR1 0x0
368 #define TWL4030_INT_PWR_IMR1 0x1
369 #define TWL4030_INT_PWR_ISR2 0x2
370 #define TWL4030_INT_PWR_IMR2 0x3
371 #define TWL4030_INT_PWR_SIR 0x4 /* test register */
372 #define TWL4030_INT_PWR_EDR1 0x5
373 #define TWL4030_INT_PWR_EDR2 0x6
374 #define TWL4030_INT_PWR_SIH_CTRL 0x7
376 /*----------------------------------------------------------------------*/
379 * Accessory Interrupts
381 #define TWL5031_ACIIMR_LSB 0x05
382 #define TWL5031_ACIIMR_MSB 0x06
383 #define TWL5031_ACIIDR_LSB 0x07
384 #define TWL5031_ACIIDR_MSB 0x08
385 #define TWL5031_ACCISR1 0x0F
386 #define TWL5031_ACCIMR1 0x10
387 #define TWL5031_ACCISR2 0x11
388 #define TWL5031_ACCIMR2 0x12
389 #define TWL5031_ACCSIR 0x13
390 #define TWL5031_ACCEDR1 0x14
391 #define TWL5031_ACCSIHCTRL 0x15
393 /*----------------------------------------------------------------------*/
396 * Battery Charger Controller
399 #define TWL5031_INTERRUPTS_BCIISR1 0x0
400 #define TWL5031_INTERRUPTS_BCIIMR1 0x1
401 #define TWL5031_INTERRUPTS_BCIISR2 0x2
402 #define TWL5031_INTERRUPTS_BCIIMR2 0x3
403 #define TWL5031_INTERRUPTS_BCISIR 0x4
404 #define TWL5031_INTERRUPTS_BCIEDR1 0x5
405 #define TWL5031_INTERRUPTS_BCIEDR2 0x6
406 #define TWL5031_INTERRUPTS_BCISIHCTRL 0x7
408 /*----------------------------------------------------------------------*/
411 * PM Master module register offsets (use TWL4030_MODULE_PM_MASTER)
414 #define TWL4030_PM_MASTER_CFG_P1_TRANSITION 0x00
415 #define TWL4030_PM_MASTER_CFG_P2_TRANSITION 0x01
416 #define TWL4030_PM_MASTER_CFG_P3_TRANSITION 0x02
417 #define TWL4030_PM_MASTER_CFG_P123_TRANSITION 0x03
418 #define TWL4030_PM_MASTER_STS_BOOT 0x04
419 #define TWL4030_PM_MASTER_CFG_BOOT 0x05
420 #define TWL4030_PM_MASTER_SHUNDAN 0x06
421 #define TWL4030_PM_MASTER_BOOT_BCI 0x07
422 #define TWL4030_PM_MASTER_CFG_PWRANA1 0x08
423 #define TWL4030_PM_MASTER_CFG_PWRANA2 0x09
424 #define TWL4030_PM_MASTER_BACKUP_MISC_STS 0x0b
425 #define TWL4030_PM_MASTER_BACKUP_MISC_CFG 0x0c
426 #define TWL4030_PM_MASTER_BACKUP_MISC_TST 0x0d
427 #define TWL4030_PM_MASTER_PROTECT_KEY 0x0e
428 #define TWL4030_PM_MASTER_STS_HW_CONDITIONS 0x0f
429 #define TWL4030_PM_MASTER_P1_SW_EVENTS 0x10
430 #define TWL4030_PM_MASTER_P2_SW_EVENTS 0x11
431 #define TWL4030_PM_MASTER_P3_SW_EVENTS 0x12
432 #define TWL4030_PM_MASTER_STS_P123_STATE 0x13
433 #define TWL4030_PM_MASTER_PB_CFG 0x14
434 #define TWL4030_PM_MASTER_PB_WORD_MSB 0x15
435 #define TWL4030_PM_MASTER_PB_WORD_LSB 0x16
436 #define TWL4030_PM_MASTER_SEQ_ADD_W2P 0x1c
437 #define TWL4030_PM_MASTER_SEQ_ADD_P2A 0x1d
438 #define TWL4030_PM_MASTER_SEQ_ADD_A2W 0x1e
439 #define TWL4030_PM_MASTER_SEQ_ADD_A2S 0x1f
440 #define TWL4030_PM_MASTER_SEQ_ADD_S2A12 0x20
441 #define TWL4030_PM_MASTER_SEQ_ADD_S2A3 0x21
442 #define TWL4030_PM_MASTER_SEQ_ADD_WARM 0x22
443 #define TWL4030_PM_MASTER_MEMORY_ADDRESS 0x23
444 #define TWL4030_PM_MASTER_MEMORY_DATA 0x24
446 #define TWL4030_PM_MASTER_KEY_CFG1 0xc0
447 #define TWL4030_PM_MASTER_KEY_CFG2 0x0c
449 #define TWL4030_PM_MASTER_KEY_TST1 0xe0
450 #define TWL4030_PM_MASTER_KEY_TST2 0x0e
452 #define TWL4030_PM_MASTER_GLOBAL_TST 0xb6
454 /*----------------------------------------------------------------------*/
456 /* Power bus message definitions */
458 /* The TWL4030/5030 splits its power-management resources (the various
459 * regulators, clock and reset lines) into 3 processor groups - P1, P2 and
460 * P3. These groups can then be configured to transition between sleep, wait-on
461 * and active states by sending messages to the power bus. See Section 5.4.2
462 * Power Resources of TWL4030 TRM
465 /* Processor groups */
466 #define DEV_GRP_NULL 0x0
467 #define DEV_GRP_P1 0x1 /* P1: all OMAP devices */
468 #define DEV_GRP_P2 0x2 /* P2: all Modem devices */
469 #define DEV_GRP_P3 0x4 /* P3: all peripheral devices */
471 /* Resource groups */
472 #define RES_GRP_RES 0x0 /* Reserved */
473 #define RES_GRP_PP 0x1 /* Power providers */
474 #define RES_GRP_RC 0x2 /* Reset and control */
475 #define RES_GRP_PP_RC 0x3
476 #define RES_GRP_PR 0x4 /* Power references */
477 #define RES_GRP_PP_PR 0x5
478 #define RES_GRP_RC_PR 0x6
479 #define RES_GRP_ALL 0x7 /* All resource groups */
481 #define RES_TYPE2_R0 0x0
483 #define RES_TYPE_ALL 0x7
485 /* Resource states */
486 #define RES_STATE_WRST 0xF
487 #define RES_STATE_ACTIVE 0xE
488 #define RES_STATE_SLEEP 0x8
489 #define RES_STATE_OFF 0x0
491 /* Power resources */
493 /* Power providers */
504 #define RES_VINTANA1 11
505 #define RES_VINTANA2 12
506 #define RES_VINTDIG 13
510 #define RES_VUSB_1V5 17
511 #define RES_VUSB_1V8 18
512 #define RES_VUSB_3V1 19
513 #define RES_VUSBCP 20
515 /* Reset and control */
516 #define RES_NRES_PWRON 22
519 #define RES_HFCLKOUT 25
520 #define RES_32KCLKOUT 26
522 /* Power Reference */
523 #define RES_MAIN_REF 28
525 #define TOTAL_RESOURCES 28
527 * Power Bus Message Format ... these can be sent individually by Linux,
528 * but are usually part of downloaded scripts that are run when various
529 * power events are triggered.
531 * Broadcast Message (16 Bits):
532 * DEV_GRP[15:13] MT[12] RES_GRP[11:9] RES_TYPE2[8:7] RES_TYPE[6:4]
535 * Singular Message (16 Bits):
536 * DEV_GRP[15:13] MT[12] RES_ID[11:4] RES_STATE[3:0]
539 #define MSG_BROADCAST(devgrp, grp, type, type2, state) \
540 ( (devgrp) << 13 | 1 << 12 | (grp) << 9 | (type2) << 7 \
541 | (type) << 4 | (state))
543 #define MSG_SINGULAR(devgrp, id, state) \
544 ((devgrp) << 13 | 0 << 12 | (id) << 4 | (state))
546 #define MSG_BROADCAST_ALL(devgrp, state) \
547 ((devgrp) << 5 | (state))
549 #define MSG_BROADCAST_REF MSG_BROADCAST_ALL
550 #define MSG_BROADCAST_PROV MSG_BROADCAST_ALL
551 #define MSG_BROADCAST__CLK_RST MSG_BROADCAST_ALL
552 /*----------------------------------------------------------------------*/
554 struct twl4030_clock_init_data {
555 bool ck32k_lowpwr_enable;
558 struct twl4030_bci_platform_data {
559 int *battery_tmp_tbl;
560 unsigned int tblsize;
562 size_t num_supplicants;
565 /* TWL4030_GPIO_MAX (18) GPIOs, with interrupts */
566 struct twl4030_gpio_platform_data {
568 unsigned irq_base, irq_end;
570 /* package the two LED signals as output-only GPIOs? */
573 /* gpio-n should control VMMC(n+1) if BIT(n) in mmc_cd is set */
576 /* if BIT(N) is set, or VMMC(n+1) is linked, debounce GPIO-N */
579 /* For gpio-N, bit (1 << N) in "pullups" is set if that pullup
580 * should be enabled. Else, if that bit is set in "pulldowns",
581 * that pulldown is enabled. Don't waste power by letting any
582 * digital inputs float...
587 int (*setup)(struct device *dev,
588 unsigned gpio, unsigned ngpio);
589 int (*teardown)(struct device *dev,
590 unsigned gpio, unsigned ngpio);
593 struct twl4030_madc_platform_data {
597 /* Boards have unique mappings of {row, col} --> keycode.
598 * Column and row are 8 bits each, but range only from 0..7.
599 * a PERSISTENT_KEY is "always on" and never reported.
601 #define PERSISTENT_KEY(r, c) KEY((r), (c), KEY_RESERVED)
603 struct twl4030_keypad_data {
604 const struct matrix_keymap_data *keymap_data;
610 enum twl4030_usb_mode {
611 T2_USB_MODE_ULPI = 1,
612 T2_USB_MODE_CEA2011_3PIN = 2,
615 struct twl4030_usb_data {
616 enum twl4030_usb_mode usb_mode;
617 unsigned long features;
619 int (*phy_init)(struct device *dev);
620 int (*phy_exit)(struct device *dev);
621 /* Power on/off the PHY */
622 int (*phy_power)(struct device *dev, int iD, int on);
623 /* enable/disable phy clocks */
624 int (*phy_set_clock)(struct device *dev, int on);
625 /* suspend/resume of phy */
626 int (*phy_suspend)(struct device *dev, int suspend);
634 struct twl4030_script {
635 struct twl4030_ins *script;
638 #define TWL4030_WRST_SCRIPT (1<<0)
639 #define TWL4030_WAKEUP12_SCRIPT (1<<1)
640 #define TWL4030_WAKEUP3_SCRIPT (1<<2)
641 #define TWL4030_SLEEP_SCRIPT (1<<3)
644 struct twl4030_resconfig {
646 u8 devgroup; /* Processor group that Power resource belongs to */
647 u8 type; /* Power resource addressed, 6 / broadcast message */
648 u8 type2; /* Power resource addressed, 3 / broadcast message */
649 u8 remap_off; /* off state remapping */
650 u8 remap_sleep; /* sleep state remapping */
653 struct twl4030_power_data {
654 struct twl4030_script **scripts;
656 struct twl4030_resconfig *resource_config;
657 #define TWL4030_RESCONFIG_UNDEF ((u8)-1)
658 bool use_poweroff; /* Board is wired for TWL poweroff */
661 extern void twl4030_power_init(struct twl4030_power_data *triton2_scripts);
662 extern int twl4030_remove_script(u8 flags);
663 extern void twl4030_power_off(void);
665 struct twl4030_codec_data {
666 unsigned int digimic_delay; /* in ms */
667 unsigned int ramp_delay_value;
668 unsigned int offset_cncl_path;
669 unsigned int check_defaults:1;
670 unsigned int reset_registers:1;
671 unsigned int hs_extmute:1;
676 void (*set_hs_extmute)(int mute);
679 struct twl4030_vibra_data {
680 unsigned int coexist;
683 unsigned int vibldrv_res; /* left driver resistance */
684 unsigned int vibrdrv_res; /* right driver resistance */
685 unsigned int viblmotor_res; /* left motor resistance */
686 unsigned int vibrmotor_res; /* right motor resistance */
687 int vddvibl_uV; /* VDDVIBL volt, set 0 for fixed reg */
688 int vddvibr_uV; /* VDDVIBR volt, set 0 for fixed reg */
691 struct twl4030_audio_data {
692 unsigned int audio_mclk;
693 struct twl4030_codec_data *codec;
694 struct twl4030_vibra_data *vibra;
697 int audpwron_gpio; /* audio power-on gpio */
698 int naudint_irq; /* audio interrupt */
699 unsigned int irq_base;
702 struct twl4030_platform_data {
703 unsigned irq_base, irq_end;
704 struct twl4030_clock_init_data *clock;
705 struct twl4030_bci_platform_data *bci;
706 struct twl4030_gpio_platform_data *gpio;
707 struct twl4030_madc_platform_data *madc;
708 struct twl4030_keypad_data *keypad;
709 struct twl4030_usb_data *usb;
710 struct twl4030_power_data *power;
711 struct twl4030_audio_data *audio;
713 /* Common LDO regulators for TWL4030/TWL6030 */
714 struct regulator_init_data *vdac;
715 struct regulator_init_data *vaux1;
716 struct regulator_init_data *vaux2;
717 struct regulator_init_data *vaux3;
718 struct regulator_init_data *vdd1;
719 struct regulator_init_data *vdd2;
720 struct regulator_init_data *vdd3;
721 /* TWL4030 LDO regulators */
722 struct regulator_init_data *vpll1;
723 struct regulator_init_data *vpll2;
724 struct regulator_init_data *vmmc1;
725 struct regulator_init_data *vmmc2;
726 struct regulator_init_data *vsim;
727 struct regulator_init_data *vaux4;
728 struct regulator_init_data *vio;
729 struct regulator_init_data *vintana1;
730 struct regulator_init_data *vintana2;
731 struct regulator_init_data *vintdig;
732 /* TWL6030 LDO regulators */
733 struct regulator_init_data *vmmc;
734 struct regulator_init_data *vpp;
735 struct regulator_init_data *vusim;
736 struct regulator_init_data *vana;
737 struct regulator_init_data *vcxio;
738 struct regulator_init_data *vusb;
739 struct regulator_init_data *clk32kg;
740 /* TWL6025 LDO regulators */
741 struct regulator_init_data *ldo1;
742 struct regulator_init_data *ldo2;
743 struct regulator_init_data *ldo3;
744 struct regulator_init_data *ldo4;
745 struct regulator_init_data *ldo5;
746 struct regulator_init_data *ldo6;
747 struct regulator_init_data *ldo7;
748 struct regulator_init_data *ldoln;
749 struct regulator_init_data *ldousb;
750 /* TWL6025 DCDC regulators */
751 struct regulator_init_data *smps3;
752 struct regulator_init_data *smps4;
753 struct regulator_init_data *vio6025;
756 struct twl_regulator_driver_data {
757 int (*set_voltage)(void *data, int target_uV);
758 int (*get_voltage)(void *data);
760 unsigned long features;
763 /*----------------------------------------------------------------------*/
765 int twl4030_sih_setup(int module);
767 /* Offsets to Power Registers */
768 #define TWL4030_VDAC_DEV_GRP 0x3B
769 #define TWL4030_VDAC_DEDICATED 0x3E
770 #define TWL4030_VAUX1_DEV_GRP 0x17
771 #define TWL4030_VAUX1_DEDICATED 0x1A
772 #define TWL4030_VAUX2_DEV_GRP 0x1B
773 #define TWL4030_VAUX2_DEDICATED 0x1E
774 #define TWL4030_VAUX3_DEV_GRP 0x1F
775 #define TWL4030_VAUX3_DEDICATED 0x22
777 static inline int twl4030charger_usb_en(int enable) { return 0; }
779 /*----------------------------------------------------------------------*/
781 /* Linux-specific regulator identifiers ... for now, we only support
782 * the LDOs, and leave the three buck converters alone. VDD1 and VDD2
783 * need to tie into hardware based voltage scaling (cpufreq etc), while
784 * VIO is generally fixed.
787 /* TWL4030 SMPS/LDO's */
788 /* EXTERNAL dc-to-dc buck converters */
789 #define TWL4030_REG_VDD1 0
790 #define TWL4030_REG_VDD2 1
791 #define TWL4030_REG_VIO 2
794 #define TWL4030_REG_VDAC 3
795 #define TWL4030_REG_VPLL1 4
796 #define TWL4030_REG_VPLL2 5 /* not on all chips */
797 #define TWL4030_REG_VMMC1 6
798 #define TWL4030_REG_VMMC2 7 /* not on all chips */
799 #define TWL4030_REG_VSIM 8 /* not on all chips */
800 #define TWL4030_REG_VAUX1 9 /* not on all chips */
801 #define TWL4030_REG_VAUX2_4030 10 /* (twl4030-specific) */
802 #define TWL4030_REG_VAUX2 11 /* (twl5030 and newer) */
803 #define TWL4030_REG_VAUX3 12 /* not on all chips */
804 #define TWL4030_REG_VAUX4 13 /* not on all chips */
807 #define TWL4030_REG_VINTANA1 14
808 #define TWL4030_REG_VINTANA2 15
809 #define TWL4030_REG_VINTDIG 16
810 #define TWL4030_REG_VUSB1V5 17
811 #define TWL4030_REG_VUSB1V8 18
812 #define TWL4030_REG_VUSB3V1 19
814 /* TWL6030 SMPS/LDO's */
815 /* EXTERNAL dc-to-dc buck convertor controllable via SR */
816 #define TWL6030_REG_VDD1 30
817 #define TWL6030_REG_VDD2 31
818 #define TWL6030_REG_VDD3 32
820 /* Non SR compliant dc-to-dc buck convertors */
821 #define TWL6030_REG_VMEM 33
822 #define TWL6030_REG_V2V1 34
823 #define TWL6030_REG_V1V29 35
824 #define TWL6030_REG_V1V8 36
827 #define TWL6030_REG_VAUX1_6030 37
828 #define TWL6030_REG_VAUX2_6030 38
829 #define TWL6030_REG_VAUX3_6030 39
830 #define TWL6030_REG_VMMC 40
831 #define TWL6030_REG_VPP 41
832 #define TWL6030_REG_VUSIM 42
833 #define TWL6030_REG_VANA 43
834 #define TWL6030_REG_VCXIO 44
835 #define TWL6030_REG_VDAC 45
836 #define TWL6030_REG_VUSB 46
839 #define TWL6030_REG_VRTC 47
840 #define TWL6030_REG_CLK32KG 48
842 /* LDOs on 6025 have different names */
843 #define TWL6025_REG_LDO2 49
844 #define TWL6025_REG_LDO4 50
845 #define TWL6025_REG_LDO3 51
846 #define TWL6025_REG_LDO5 52
847 #define TWL6025_REG_LDO1 53
848 #define TWL6025_REG_LDO7 54
849 #define TWL6025_REG_LDO6 55
850 #define TWL6025_REG_LDOLN 56
851 #define TWL6025_REG_LDOUSB 57
853 /* 6025 DCDC supplies */
854 #define TWL6025_REG_SMPS3 58
855 #define TWL6025_REG_SMPS4 59
856 #define TWL6025_REG_VIO 60
859 #endif /* End of __TWL4030_H */