2 * twl4030.h - header for TWL4030 PM and audio CODEC device
4 * Copyright (C) 2005-2006 Texas Instruments, Inc.
6 * Based on tlv320aic23.c:
7 * Copyright (c) by Kai Svahn <kai.svahn@nokia.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
28 #include <linux/types.h>
29 #include <linux/input/matrix_keypad.h>
32 * Using the twl4030 core we address registers using a pair
33 * { module id, relative register offset }
34 * which that core then maps to the relevant
35 * { i2c slave, absolute register address }
37 * The module IDs are meaningful only to the twl4030 core code,
38 * which uses them as array indices to look up the first register
39 * address each module uses within a given i2c slave.
42 /* Slave 0 (i2c address 0x48) */
43 #define TWL4030_MODULE_USB 0x00
45 /* Slave 1 (i2c address 0x49) */
46 #define TWL4030_MODULE_AUDIO_VOICE 0x01
47 #define TWL4030_MODULE_GPIO 0x02
48 #define TWL4030_MODULE_INTBR 0x03
49 #define TWL4030_MODULE_PIH 0x04
50 #define TWL4030_MODULE_TEST 0x05
52 /* Slave 2 (i2c address 0x4a) */
53 #define TWL4030_MODULE_KEYPAD 0x06
54 #define TWL4030_MODULE_MADC 0x07
55 #define TWL4030_MODULE_INTERRUPTS 0x08
56 #define TWL4030_MODULE_LED 0x09
57 #define TWL4030_MODULE_MAIN_CHARGE 0x0A
58 #define TWL4030_MODULE_PRECHARGE 0x0B
59 #define TWL4030_MODULE_PWM0 0x0C
60 #define TWL4030_MODULE_PWM1 0x0D
61 #define TWL4030_MODULE_PWMA 0x0E
62 #define TWL4030_MODULE_PWMB 0x0F
64 #define TWL5031_MODULE_ACCESSORY 0x10
65 #define TWL5031_MODULE_INTERRUPTS 0x11
67 /* Slave 3 (i2c address 0x4b) */
68 #define TWL4030_MODULE_BACKUP 0x12
69 #define TWL4030_MODULE_INT 0x13
70 #define TWL4030_MODULE_PM_MASTER 0x14
71 #define TWL4030_MODULE_PM_RECEIVER 0x15
72 #define TWL4030_MODULE_RTC 0x16
73 #define TWL4030_MODULE_SECURED_REG 0x17
75 #define TWL_MODULE_USB TWL4030_MODULE_USB
76 #define TWL_MODULE_AUDIO_VOICE TWL4030_MODULE_AUDIO_VOICE
77 #define TWL_MODULE_PIH TWL4030_MODULE_PIH
78 #define TWL_MODULE_MADC TWL4030_MODULE_MADC
79 #define TWL_MODULE_MAIN_CHARGE TWL4030_MODULE_MAIN_CHARGE
80 #define TWL_MODULE_PM_MASTER TWL4030_MODULE_PM_MASTER
81 #define TWL_MODULE_PM_RECEIVER TWL4030_MODULE_PM_RECEIVER
82 #define TWL_MODULE_RTC TWL4030_MODULE_RTC
83 #define TWL_MODULE_PWM TWL4030_MODULE_PWM0
85 #define TWL6030_MODULE_ID0 0x0D
86 #define TWL6030_MODULE_ID1 0x0E
87 #define TWL6030_MODULE_ID2 0x0F
89 #define GPIO_INTR_OFFSET 0
90 #define KEYPAD_INTR_OFFSET 1
91 #define BCI_INTR_OFFSET 2
92 #define MADC_INTR_OFFSET 3
93 #define USB_INTR_OFFSET 4
94 #define BCI_PRES_INTR_OFFSET 9
95 #define USB_PRES_INTR_OFFSET 10
96 #define RTC_INTR_OFFSET 11
99 * Offset from TWL6030_IRQ_BASE / pdata->irq_base
101 #define PWR_INTR_OFFSET 0
102 #define HOTDIE_INTR_OFFSET 12
103 #define SMPSLDO_INTR_OFFSET 13
104 #define BATDETECT_INTR_OFFSET 14
105 #define SIMDETECT_INTR_OFFSET 15
106 #define MMCDETECT_INTR_OFFSET 16
107 #define GASGAUGE_INTR_OFFSET 17
108 #define USBOTG_INTR_OFFSET 4
109 #define CHARGER_INTR_OFFSET 2
110 #define RSV_INTR_OFFSET 0
112 /* INT register offsets */
113 #define REG_INT_STS_A 0x00
114 #define REG_INT_STS_B 0x01
115 #define REG_INT_STS_C 0x02
117 #define REG_INT_MSK_LINE_A 0x03
118 #define REG_INT_MSK_LINE_B 0x04
119 #define REG_INT_MSK_LINE_C 0x05
121 #define REG_INT_MSK_STS_A 0x06
122 #define REG_INT_MSK_STS_B 0x07
123 #define REG_INT_MSK_STS_C 0x08
125 /* MASK INT REG GROUP A */
126 #define TWL6030_PWR_INT_MASK 0x07
127 #define TWL6030_RTC_INT_MASK 0x18
128 #define TWL6030_HOTDIE_INT_MASK 0x20
129 #define TWL6030_SMPSLDOA_INT_MASK 0xC0
131 /* MASK INT REG GROUP B */
132 #define TWL6030_SMPSLDOB_INT_MASK 0x01
133 #define TWL6030_BATDETECT_INT_MASK 0x02
134 #define TWL6030_SIMDETECT_INT_MASK 0x04
135 #define TWL6030_MMCDETECT_INT_MASK 0x08
136 #define TWL6030_GPADC_INT_MASK 0x60
137 #define TWL6030_GASGAUGE_INT_MASK 0x80
139 /* MASK INT REG GROUP C */
140 #define TWL6030_USBOTG_INT_MASK 0x0F
141 #define TWL6030_CHARGER_CTRL_INT_MASK 0x10
142 #define TWL6030_CHARGER_FAULT_INT_MASK 0x60
144 #define TWL6030_MMCCTRL 0xEE
145 #define VMMC_AUTO_OFF (0x1 << 3)
146 #define SW_FC (0x1 << 2)
149 #define TWL6030_CFG_INPUT_PUPD3 0xF2
150 #define MMC_PU (0x1 << 3)
151 #define MMC_PD (0x1 << 2)
153 #define TWL_SIL_TYPE(rev) ((rev) & 0x00FFFFFF)
154 #define TWL_SIL_REV(rev) ((rev) >> 24)
155 #define TWL_SIL_5030 0x09002F
156 #define TWL5030_REV_1_0 0x00
157 #define TWL5030_REV_1_1 0x10
158 #define TWL5030_REV_1_2 0x30
160 #define TWL4030_CLASS_ID 0x4030
161 #define TWL6030_CLASS_ID 0x6030
162 unsigned int twl_rev(void);
163 #define GET_TWL_REV (twl_rev())
164 #define TWL_CLASS_IS(class, id) \
165 static inline int twl_class_is_ ##class(void) \
167 return ((id) == (GET_TWL_REV)) ? 1 : 0; \
170 TWL_CLASS_IS(4030, TWL4030_CLASS_ID)
171 TWL_CLASS_IS(6030, TWL6030_CLASS_ID)
174 * Read and write single 8-bit registers
176 int twl_i2c_write_u8(u8 mod_no, u8 val, u8 reg);
177 int twl_i2c_read_u8(u8 mod_no, u8 *val, u8 reg);
180 * Read and write several 8-bit registers at once.
182 * IMPORTANT: For twl_i2c_write(), allocate num_bytes + 1
183 * for the value, and populate your data starting at offset 1.
185 int twl_i2c_write(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes);
186 int twl_i2c_read(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes);
188 int twl_get_type(void);
189 int twl_get_version(void);
191 int twl6030_interrupt_unmask(u8 bit_mask, u8 offset);
192 int twl6030_interrupt_mask(u8 bit_mask, u8 offset);
194 /* Card detect Configuration for MMC1 Controller on OMAP4 */
195 #ifdef CONFIG_TWL4030_CORE
196 int twl6030_mmc_card_detect_config(void);
198 static inline int twl6030_mmc_card_detect_config(void)
200 pr_debug("twl6030_mmc_card_detect_config not supported\n");
205 /* MMC1 Controller on OMAP4 uses Phoenix irq for Card detect */
206 #ifdef CONFIG_TWL4030_CORE
207 int twl6030_mmc_card_detect(struct device *dev, int slot);
209 static inline int twl6030_mmc_card_detect(struct device *dev, int slot)
211 pr_debug("Call back twl6030_mmc_card_detect not supported\n");
215 /*----------------------------------------------------------------------*/
218 * NOTE: at up to 1024 registers, this is a big chip.
220 * Avoid putting register declarations in this file, instead of into
221 * a driver-private file, unless some of the registers in a block
222 * need to be shared with other drivers. One example is blocks that
223 * have Secondary IRQ Handler (SIH) registers.
226 #define TWL4030_SIH_CTRL_EXCLEN_MASK BIT(0)
227 #define TWL4030_SIH_CTRL_PENDDIS_MASK BIT(1)
228 #define TWL4030_SIH_CTRL_COR_MASK BIT(2)
230 /*----------------------------------------------------------------------*/
233 * GPIO Block Register offsets (use TWL4030_MODULE_GPIO)
236 #define REG_GPIODATAIN1 0x0
237 #define REG_GPIODATAIN2 0x1
238 #define REG_GPIODATAIN3 0x2
239 #define REG_GPIODATADIR1 0x3
240 #define REG_GPIODATADIR2 0x4
241 #define REG_GPIODATADIR3 0x5
242 #define REG_GPIODATAOUT1 0x6
243 #define REG_GPIODATAOUT2 0x7
244 #define REG_GPIODATAOUT3 0x8
245 #define REG_CLEARGPIODATAOUT1 0x9
246 #define REG_CLEARGPIODATAOUT2 0xA
247 #define REG_CLEARGPIODATAOUT3 0xB
248 #define REG_SETGPIODATAOUT1 0xC
249 #define REG_SETGPIODATAOUT2 0xD
250 #define REG_SETGPIODATAOUT3 0xE
251 #define REG_GPIO_DEBEN1 0xF
252 #define REG_GPIO_DEBEN2 0x10
253 #define REG_GPIO_DEBEN3 0x11
254 #define REG_GPIO_CTRL 0x12
255 #define REG_GPIOPUPDCTR1 0x13
256 #define REG_GPIOPUPDCTR2 0x14
257 #define REG_GPIOPUPDCTR3 0x15
258 #define REG_GPIOPUPDCTR4 0x16
259 #define REG_GPIOPUPDCTR5 0x17
260 #define REG_GPIO_ISR1A 0x19
261 #define REG_GPIO_ISR2A 0x1A
262 #define REG_GPIO_ISR3A 0x1B
263 #define REG_GPIO_IMR1A 0x1C
264 #define REG_GPIO_IMR2A 0x1D
265 #define REG_GPIO_IMR3A 0x1E
266 #define REG_GPIO_ISR1B 0x1F
267 #define REG_GPIO_ISR2B 0x20
268 #define REG_GPIO_ISR3B 0x21
269 #define REG_GPIO_IMR1B 0x22
270 #define REG_GPIO_IMR2B 0x23
271 #define REG_GPIO_IMR3B 0x24
272 #define REG_GPIO_EDR1 0x28
273 #define REG_GPIO_EDR2 0x29
274 #define REG_GPIO_EDR3 0x2A
275 #define REG_GPIO_EDR4 0x2B
276 #define REG_GPIO_EDR5 0x2C
277 #define REG_GPIO_SIH_CTRL 0x2D
279 /* Up to 18 signals are available as GPIOs, when their
280 * pins are not assigned to another use (such as ULPI/USB).
282 #define TWL4030_GPIO_MAX 18
284 /*----------------------------------------------------------------------*/
286 /*Interface Bit Register (INTBR) offsets
287 *(Use TWL_4030_MODULE_INTBR)
290 #define REG_IDCODE_7_0 0x00
291 #define REG_IDCODE_15_8 0x01
292 #define REG_IDCODE_16_23 0x02
293 #define REG_IDCODE_31_24 0x03
294 #define REG_GPPUPDCTR1 0x0F
295 #define REG_UNLOCK_TEST_REG 0x12
297 /*I2C1 and I2C4(SR) SDA/SCL pull-up control bits */
299 #define I2C_SCL_CTRL_PU BIT(0)
300 #define I2C_SDA_CTRL_PU BIT(2)
301 #define SR_I2C_SCL_CTRL_PU BIT(4)
302 #define SR_I2C_SDA_CTRL_PU BIT(6)
304 #define TWL_EEPROM_R_UNLOCK 0x49
306 /*----------------------------------------------------------------------*/
309 * Keypad register offsets (use TWL4030_MODULE_KEYPAD)
310 * ... SIH/interrupt only
313 #define TWL4030_KEYPAD_KEYP_ISR1 0x11
314 #define TWL4030_KEYPAD_KEYP_IMR1 0x12
315 #define TWL4030_KEYPAD_KEYP_ISR2 0x13
316 #define TWL4030_KEYPAD_KEYP_IMR2 0x14
317 #define TWL4030_KEYPAD_KEYP_SIR 0x15 /* test register */
318 #define TWL4030_KEYPAD_KEYP_EDR 0x16
319 #define TWL4030_KEYPAD_KEYP_SIH_CTRL 0x17
321 /*----------------------------------------------------------------------*/
324 * Multichannel ADC register offsets (use TWL4030_MODULE_MADC)
325 * ... SIH/interrupt only
328 #define TWL4030_MADC_ISR1 0x61
329 #define TWL4030_MADC_IMR1 0x62
330 #define TWL4030_MADC_ISR2 0x63
331 #define TWL4030_MADC_IMR2 0x64
332 #define TWL4030_MADC_SIR 0x65 /* test register */
333 #define TWL4030_MADC_EDR 0x66
334 #define TWL4030_MADC_SIH_CTRL 0x67
336 /*----------------------------------------------------------------------*/
339 * Battery charger register offsets (use TWL4030_MODULE_INTERRUPTS)
342 #define TWL4030_INTERRUPTS_BCIISR1A 0x0
343 #define TWL4030_INTERRUPTS_BCIISR2A 0x1
344 #define TWL4030_INTERRUPTS_BCIIMR1A 0x2
345 #define TWL4030_INTERRUPTS_BCIIMR2A 0x3
346 #define TWL4030_INTERRUPTS_BCIISR1B 0x4
347 #define TWL4030_INTERRUPTS_BCIISR2B 0x5
348 #define TWL4030_INTERRUPTS_BCIIMR1B 0x6
349 #define TWL4030_INTERRUPTS_BCIIMR2B 0x7
350 #define TWL4030_INTERRUPTS_BCISIR1 0x8 /* test register */
351 #define TWL4030_INTERRUPTS_BCISIR2 0x9 /* test register */
352 #define TWL4030_INTERRUPTS_BCIEDR1 0xa
353 #define TWL4030_INTERRUPTS_BCIEDR2 0xb
354 #define TWL4030_INTERRUPTS_BCIEDR3 0xc
355 #define TWL4030_INTERRUPTS_BCISIHCTRL 0xd
357 /*----------------------------------------------------------------------*/
360 * Power Interrupt block register offsets (use TWL4030_MODULE_INT)
363 #define TWL4030_INT_PWR_ISR1 0x0
364 #define TWL4030_INT_PWR_IMR1 0x1
365 #define TWL4030_INT_PWR_ISR2 0x2
366 #define TWL4030_INT_PWR_IMR2 0x3
367 #define TWL4030_INT_PWR_SIR 0x4 /* test register */
368 #define TWL4030_INT_PWR_EDR1 0x5
369 #define TWL4030_INT_PWR_EDR2 0x6
370 #define TWL4030_INT_PWR_SIH_CTRL 0x7
372 /*----------------------------------------------------------------------*/
375 * Accessory Interrupts
377 #define TWL5031_ACIIMR_LSB 0x05
378 #define TWL5031_ACIIMR_MSB 0x06
379 #define TWL5031_ACIIDR_LSB 0x07
380 #define TWL5031_ACIIDR_MSB 0x08
381 #define TWL5031_ACCISR1 0x0F
382 #define TWL5031_ACCIMR1 0x10
383 #define TWL5031_ACCISR2 0x11
384 #define TWL5031_ACCIMR2 0x12
385 #define TWL5031_ACCSIR 0x13
386 #define TWL5031_ACCEDR1 0x14
387 #define TWL5031_ACCSIHCTRL 0x15
389 /*----------------------------------------------------------------------*/
392 * Battery Charger Controller
395 #define TWL5031_INTERRUPTS_BCIISR1 0x0
396 #define TWL5031_INTERRUPTS_BCIIMR1 0x1
397 #define TWL5031_INTERRUPTS_BCIISR2 0x2
398 #define TWL5031_INTERRUPTS_BCIIMR2 0x3
399 #define TWL5031_INTERRUPTS_BCISIR 0x4
400 #define TWL5031_INTERRUPTS_BCIEDR1 0x5
401 #define TWL5031_INTERRUPTS_BCIEDR2 0x6
402 #define TWL5031_INTERRUPTS_BCISIHCTRL 0x7
404 /*----------------------------------------------------------------------*/
407 * PM Master module register offsets (use TWL4030_MODULE_PM_MASTER)
410 #define TWL4030_PM_MASTER_CFG_P1_TRANSITION 0x00
411 #define TWL4030_PM_MASTER_CFG_P2_TRANSITION 0x01
412 #define TWL4030_PM_MASTER_CFG_P3_TRANSITION 0x02
413 #define TWL4030_PM_MASTER_CFG_P123_TRANSITION 0x03
414 #define TWL4030_PM_MASTER_STS_BOOT 0x04
415 #define TWL4030_PM_MASTER_CFG_BOOT 0x05
416 #define TWL4030_PM_MASTER_SHUNDAN 0x06
417 #define TWL4030_PM_MASTER_BOOT_BCI 0x07
418 #define TWL4030_PM_MASTER_CFG_PWRANA1 0x08
419 #define TWL4030_PM_MASTER_CFG_PWRANA2 0x09
420 #define TWL4030_PM_MASTER_BACKUP_MISC_STS 0x0b
421 #define TWL4030_PM_MASTER_BACKUP_MISC_CFG 0x0c
422 #define TWL4030_PM_MASTER_BACKUP_MISC_TST 0x0d
423 #define TWL4030_PM_MASTER_PROTECT_KEY 0x0e
424 #define TWL4030_PM_MASTER_STS_HW_CONDITIONS 0x0f
425 #define TWL4030_PM_MASTER_P1_SW_EVENTS 0x10
426 #define TWL4030_PM_MASTER_P2_SW_EVENTS 0x11
427 #define TWL4030_PM_MASTER_P3_SW_EVENTS 0x12
428 #define TWL4030_PM_MASTER_STS_P123_STATE 0x13
429 #define TWL4030_PM_MASTER_PB_CFG 0x14
430 #define TWL4030_PM_MASTER_PB_WORD_MSB 0x15
431 #define TWL4030_PM_MASTER_PB_WORD_LSB 0x16
432 #define TWL4030_PM_MASTER_SEQ_ADD_W2P 0x1c
433 #define TWL4030_PM_MASTER_SEQ_ADD_P2A 0x1d
434 #define TWL4030_PM_MASTER_SEQ_ADD_A2W 0x1e
435 #define TWL4030_PM_MASTER_SEQ_ADD_A2S 0x1f
436 #define TWL4030_PM_MASTER_SEQ_ADD_S2A12 0x20
437 #define TWL4030_PM_MASTER_SEQ_ADD_S2A3 0x21
438 #define TWL4030_PM_MASTER_SEQ_ADD_WARM 0x22
439 #define TWL4030_PM_MASTER_MEMORY_ADDRESS 0x23
440 #define TWL4030_PM_MASTER_MEMORY_DATA 0x24
442 #define TWL4030_PM_MASTER_KEY_CFG1 0xc0
443 #define TWL4030_PM_MASTER_KEY_CFG2 0x0c
445 #define TWL4030_PM_MASTER_KEY_TST1 0xe0
446 #define TWL4030_PM_MASTER_KEY_TST2 0x0e
448 #define TWL4030_PM_MASTER_GLOBAL_TST 0xb6
450 /*----------------------------------------------------------------------*/
452 /* Power bus message definitions */
454 /* The TWL4030/5030 splits its power-management resources (the various
455 * regulators, clock and reset lines) into 3 processor groups - P1, P2 and
456 * P3. These groups can then be configured to transition between sleep, wait-on
457 * and active states by sending messages to the power bus. See Section 5.4.2
458 * Power Resources of TWL4030 TRM
461 /* Processor groups */
462 #define DEV_GRP_NULL 0x0
463 #define DEV_GRP_P1 0x1 /* P1: all OMAP devices */
464 #define DEV_GRP_P2 0x2 /* P2: all Modem devices */
465 #define DEV_GRP_P3 0x4 /* P3: all peripheral devices */
467 /* Resource groups */
468 #define RES_GRP_RES 0x0 /* Reserved */
469 #define RES_GRP_PP 0x1 /* Power providers */
470 #define RES_GRP_RC 0x2 /* Reset and control */
471 #define RES_GRP_PP_RC 0x3
472 #define RES_GRP_PR 0x4 /* Power references */
473 #define RES_GRP_PP_PR 0x5
474 #define RES_GRP_RC_PR 0x6
475 #define RES_GRP_ALL 0x7 /* All resource groups */
477 #define RES_TYPE2_R0 0x0
479 #define RES_TYPE_ALL 0x7
481 /* Resource states */
482 #define RES_STATE_WRST 0xF
483 #define RES_STATE_ACTIVE 0xE
484 #define RES_STATE_SLEEP 0x8
485 #define RES_STATE_OFF 0x0
487 /* Power resources */
489 /* Power providers */
500 #define RES_VINTANA1 11
501 #define RES_VINTANA2 12
502 #define RES_VINTDIG 13
506 #define RES_VUSB_1V5 17
507 #define RES_VUSB_1V8 18
508 #define RES_VUSB_3V1 19
509 #define RES_VUSBCP 20
511 /* Reset and control */
512 #define RES_NRES_PWRON 22
515 #define RES_HFCLKOUT 25
516 #define RES_32KCLKOUT 26
518 /* Power Reference */
519 #define RES_MAIN_REF 28
521 #define TOTAL_RESOURCES 28
523 * Power Bus Message Format ... these can be sent individually by Linux,
524 * but are usually part of downloaded scripts that are run when various
525 * power events are triggered.
527 * Broadcast Message (16 Bits):
528 * DEV_GRP[15:13] MT[12] RES_GRP[11:9] RES_TYPE2[8:7] RES_TYPE[6:4]
531 * Singular Message (16 Bits):
532 * DEV_GRP[15:13] MT[12] RES_ID[11:4] RES_STATE[3:0]
535 #define MSG_BROADCAST(devgrp, grp, type, type2, state) \
536 ( (devgrp) << 13 | 1 << 12 | (grp) << 9 | (type2) << 7 \
537 | (type) << 4 | (state))
539 #define MSG_SINGULAR(devgrp, id, state) \
540 ((devgrp) << 13 | 0 << 12 | (id) << 4 | (state))
542 #define MSG_BROADCAST_ALL(devgrp, state) \
543 ((devgrp) << 5 | (state))
545 #define MSG_BROADCAST_REF MSG_BROADCAST_ALL
546 #define MSG_BROADCAST_PROV MSG_BROADCAST_ALL
547 #define MSG_BROADCAST__CLK_RST MSG_BROADCAST_ALL
548 /*----------------------------------------------------------------------*/
550 struct twl4030_clock_init_data {
551 bool ck32k_lowpwr_enable;
554 struct twl4030_bci_platform_data {
555 int *battery_tmp_tbl;
556 unsigned int tblsize;
559 /* TWL4030_GPIO_MAX (18) GPIOs, with interrupts */
560 struct twl4030_gpio_platform_data {
562 unsigned irq_base, irq_end;
564 /* package the two LED signals as output-only GPIOs? */
567 /* gpio-n should control VMMC(n+1) if BIT(n) in mmc_cd is set */
570 /* if BIT(N) is set, or VMMC(n+1) is linked, debounce GPIO-N */
573 /* For gpio-N, bit (1 << N) in "pullups" is set if that pullup
574 * should be enabled. Else, if that bit is set in "pulldowns",
575 * that pulldown is enabled. Don't waste power by letting any
576 * digital inputs float...
581 int (*setup)(struct device *dev,
582 unsigned gpio, unsigned ngpio);
583 int (*teardown)(struct device *dev,
584 unsigned gpio, unsigned ngpio);
587 struct twl4030_madc_platform_data {
591 /* Boards have unique mappings of {row, col} --> keycode.
592 * Column and row are 8 bits each, but range only from 0..7.
593 * a PERSISTENT_KEY is "always on" and never reported.
595 #define PERSISTENT_KEY(r, c) KEY((r), (c), KEY_RESERVED)
597 struct twl4030_keypad_data {
598 const struct matrix_keymap_data *keymap_data;
604 enum twl4030_usb_mode {
605 T2_USB_MODE_ULPI = 1,
606 T2_USB_MODE_CEA2011_3PIN = 2,
609 struct twl4030_usb_data {
610 enum twl4030_usb_mode usb_mode;
612 int (*phy_init)(struct device *dev);
613 int (*phy_exit)(struct device *dev);
614 /* Power on/off the PHY */
615 int (*phy_power)(struct device *dev, int iD, int on);
616 /* enable/disable phy clocks */
617 int (*phy_set_clock)(struct device *dev, int on);
618 /* suspend/resume of phy */
619 int (*phy_suspend)(struct device *dev, int suspend);
627 struct twl4030_script {
628 struct twl4030_ins *script;
631 #define TWL4030_WRST_SCRIPT (1<<0)
632 #define TWL4030_WAKEUP12_SCRIPT (1<<1)
633 #define TWL4030_WAKEUP3_SCRIPT (1<<2)
634 #define TWL4030_SLEEP_SCRIPT (1<<3)
637 struct twl4030_resconfig {
639 u8 devgroup; /* Processor group that Power resource belongs to */
640 u8 type; /* Power resource addressed, 6 / broadcast message */
641 u8 type2; /* Power resource addressed, 3 / broadcast message */
642 u8 remap_off; /* off state remapping */
643 u8 remap_sleep; /* sleep state remapping */
646 struct twl4030_power_data {
647 struct twl4030_script **scripts;
649 struct twl4030_resconfig *resource_config;
650 #define TWL4030_RESCONFIG_UNDEF ((u8)-1)
653 extern void twl4030_power_init(struct twl4030_power_data *triton2_scripts);
654 extern int twl4030_remove_script(u8 flags);
656 struct twl4030_codec_audio_data {
657 unsigned int digimic_delay; /* in ms */
658 unsigned int ramp_delay_value;
659 unsigned int offset_cncl_path;
660 unsigned int check_defaults:1;
661 unsigned int reset_registers:1;
662 unsigned int hs_extmute:1;
663 void (*set_hs_extmute)(int mute);
666 struct twl4030_codec_vibra_data {
667 unsigned int coexist;
670 struct twl4030_codec_data {
671 unsigned int audio_mclk;
672 struct twl4030_codec_audio_data *audio;
673 struct twl4030_codec_vibra_data *vibra;
676 int audpwron_gpio; /* audio power-on gpio */
677 int naudint_irq; /* audio interrupt */
680 struct twl4030_platform_data {
681 unsigned irq_base, irq_end;
682 struct twl4030_clock_init_data *clock;
683 struct twl4030_bci_platform_data *bci;
684 struct twl4030_gpio_platform_data *gpio;
685 struct twl4030_madc_platform_data *madc;
686 struct twl4030_keypad_data *keypad;
687 struct twl4030_usb_data *usb;
688 struct twl4030_power_data *power;
689 struct twl4030_codec_data *codec;
691 /* Common LDO regulators for TWL4030/TWL6030 */
692 struct regulator_init_data *vdac;
693 struct regulator_init_data *vaux1;
694 struct regulator_init_data *vaux2;
695 struct regulator_init_data *vaux3;
696 /* TWL4030 LDO regulators */
697 struct regulator_init_data *vpll1;
698 struct regulator_init_data *vpll2;
699 struct regulator_init_data *vmmc1;
700 struct regulator_init_data *vmmc2;
701 struct regulator_init_data *vsim;
702 struct regulator_init_data *vaux4;
703 struct regulator_init_data *vio;
704 struct regulator_init_data *vdd1;
705 struct regulator_init_data *vdd2;
706 struct regulator_init_data *vintana1;
707 struct regulator_init_data *vintana2;
708 struct regulator_init_data *vintdig;
709 /* TWL6030 LDO regulators */
710 struct regulator_init_data *vmmc;
711 struct regulator_init_data *vpp;
712 struct regulator_init_data *vusim;
713 struct regulator_init_data *vana;
714 struct regulator_init_data *vcxio;
715 struct regulator_init_data *vusb;
716 struct regulator_init_data *clk32kg;
719 /*----------------------------------------------------------------------*/
721 int twl4030_sih_setup(int module);
723 /* Offsets to Power Registers */
724 #define TWL4030_VDAC_DEV_GRP 0x3B
725 #define TWL4030_VDAC_DEDICATED 0x3E
726 #define TWL4030_VAUX1_DEV_GRP 0x17
727 #define TWL4030_VAUX1_DEDICATED 0x1A
728 #define TWL4030_VAUX2_DEV_GRP 0x1B
729 #define TWL4030_VAUX2_DEDICATED 0x1E
730 #define TWL4030_VAUX3_DEV_GRP 0x1F
731 #define TWL4030_VAUX3_DEDICATED 0x22
733 static inline int twl4030charger_usb_en(int enable) { return 0; }
735 /*----------------------------------------------------------------------*/
737 /* Linux-specific regulator identifiers ... for now, we only support
738 * the LDOs, and leave the three buck converters alone. VDD1 and VDD2
739 * need to tie into hardware based voltage scaling (cpufreq etc), while
740 * VIO is generally fixed.
743 /* TWL4030 SMPS/LDO's */
744 /* EXTERNAL dc-to-dc buck converters */
745 #define TWL4030_REG_VDD1 0
746 #define TWL4030_REG_VDD2 1
747 #define TWL4030_REG_VIO 2
750 #define TWL4030_REG_VDAC 3
751 #define TWL4030_REG_VPLL1 4
752 #define TWL4030_REG_VPLL2 5 /* not on all chips */
753 #define TWL4030_REG_VMMC1 6
754 #define TWL4030_REG_VMMC2 7 /* not on all chips */
755 #define TWL4030_REG_VSIM 8 /* not on all chips */
756 #define TWL4030_REG_VAUX1 9 /* not on all chips */
757 #define TWL4030_REG_VAUX2_4030 10 /* (twl4030-specific) */
758 #define TWL4030_REG_VAUX2 11 /* (twl5030 and newer) */
759 #define TWL4030_REG_VAUX3 12 /* not on all chips */
760 #define TWL4030_REG_VAUX4 13 /* not on all chips */
763 #define TWL4030_REG_VINTANA1 14
764 #define TWL4030_REG_VINTANA2 15
765 #define TWL4030_REG_VINTDIG 16
766 #define TWL4030_REG_VUSB1V5 17
767 #define TWL4030_REG_VUSB1V8 18
768 #define TWL4030_REG_VUSB3V1 19
770 /* TWL6030 SMPS/LDO's */
771 /* EXTERNAL dc-to-dc buck convertor controllable via SR */
772 #define TWL6030_REG_VDD1 30
773 #define TWL6030_REG_VDD2 31
774 #define TWL6030_REG_VDD3 32
776 /* Non SR compliant dc-to-dc buck convertors */
777 #define TWL6030_REG_VMEM 33
778 #define TWL6030_REG_V2V1 34
779 #define TWL6030_REG_V1V29 35
780 #define TWL6030_REG_V1V8 36
783 #define TWL6030_REG_VAUX1_6030 37
784 #define TWL6030_REG_VAUX2_6030 38
785 #define TWL6030_REG_VAUX3_6030 39
786 #define TWL6030_REG_VMMC 40
787 #define TWL6030_REG_VPP 41
788 #define TWL6030_REG_VUSIM 42
789 #define TWL6030_REG_VANA 43
790 #define TWL6030_REG_VCXIO 44
791 #define TWL6030_REG_VDAC 45
792 #define TWL6030_REG_VUSB 46
795 #define TWL6030_REG_VRTC 47
796 #define TWL6030_REG_CLK32KG 48
798 #endif /* End of __TWL4030_H */