2 * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59
16 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 * The full GNU General Public License is included in this distribution in the
19 * file called COPYING.
24 #include <linux/device.h>
25 #include <linux/uio.h>
26 #include <linux/kref.h>
27 #include <linux/completion.h>
28 #include <linux/rcupdate.h>
29 #include <linux/dma-mapping.h>
32 * enum dma_state - resource PNP/power management state
33 * @DMA_RESOURCE_SUSPEND: DMA device going into low power state
34 * @DMA_RESOURCE_RESUME: DMA device returning to full power
35 * @DMA_RESOURCE_AVAILABLE: DMA device available to the system
36 * @DMA_RESOURCE_REMOVED: DMA device removed from the system
41 DMA_RESOURCE_AVAILABLE,
46 * enum dma_state_client - state of the channel in the client
47 * @DMA_ACK: client would like to use, or was using this channel
48 * @DMA_DUP: client has already seen this channel, or is not using this channel
49 * @DMA_NAK: client does not want to see any more channels
51 enum dma_state_client {
58 * typedef dma_cookie_t - an opaque DMA cookie
60 * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code
62 typedef s32 dma_cookie_t;
64 #define dma_submit_error(cookie) ((cookie) < 0 ? 1 : 0)
67 * enum dma_status - DMA transaction status
68 * @DMA_SUCCESS: transaction completed successfully
69 * @DMA_IN_PROGRESS: transaction not yet processed
70 * @DMA_ERROR: transaction failed
79 * enum dma_transaction_type - DMA transaction types/indexes
81 enum dma_transaction_type {
96 /* last transaction type for creation of the capabilities mask */
97 #define DMA_TX_TYPE_END (DMA_SLAVE + 1)
101 * enum dma_ctrl_flags - DMA flags to augment operation preparation,
102 * control completion, and communicate status.
103 * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of
105 * @DMA_CTRL_ACK - the descriptor cannot be reused until the client
106 * acknowledges receipt, i.e. has has a chance to establish any
108 * @DMA_COMPL_SKIP_SRC_UNMAP - set to disable dma-unmapping the source buffer(s)
109 * @DMA_COMPL_SKIP_DEST_UNMAP - set to disable dma-unmapping the destination(s)
111 enum dma_ctrl_flags {
112 DMA_PREP_INTERRUPT = (1 << 0),
113 DMA_CTRL_ACK = (1 << 1),
114 DMA_COMPL_SKIP_SRC_UNMAP = (1 << 2),
115 DMA_COMPL_SKIP_DEST_UNMAP = (1 << 3),
119 * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t.
120 * See linux/cpumask.h
122 typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t;
125 * struct dma_chan_percpu - the per-CPU part of struct dma_chan
126 * @refcount: local_t used for open-coded "bigref" counting
127 * @memcpy_count: transaction counter
128 * @bytes_transferred: byte counter
131 struct dma_chan_percpu {
133 unsigned long memcpy_count;
134 unsigned long bytes_transferred;
138 * struct dma_chan - devices supply DMA channels, clients use them
139 * @device: ptr to the dma device who supplies this channel, always !%NULL
140 * @cookie: last cookie value returned to client
141 * @chan_id: channel ID for sysfs
142 * @class_dev: class device for sysfs
143 * @refcount: kref, used in "bigref" slow-mode
144 * @slow_ref: indicates that the DMA channel is free
145 * @rcu: the DMA channel's RCU head
146 * @device_node: used to add this to the device chan list
147 * @local: per-cpu pointer to a struct dma_chan_percpu
148 * @client-count: how many clients are using this channel
149 * @table_count: number of appearances in the mem-to-mem allocation table
152 struct dma_device *device;
159 struct kref refcount;
163 struct list_head device_node;
164 struct dma_chan_percpu *local;
169 #define to_dma_chan(p) container_of(p, struct dma_chan, dev)
171 void dma_chan_cleanup(struct kref *kref);
174 * typedef dma_event_callback - function pointer to a DMA event callback
175 * For each channel added to the system this routine is called for each client.
176 * If the client would like to use the channel it returns '1' to signal (ack)
177 * the dmaengine core to take out a reference on the channel and its
178 * corresponding device. A client must not 'ack' an available channel more
179 * than once. When a channel is removed all clients are notified. If a client
180 * is using the channel it must 'ack' the removal. A client must not 'ack' a
181 * removed channel more than once.
182 * @client - 'this' pointer for the client context
183 * @chan - channel to be acted upon
184 * @state - available or removed
187 typedef enum dma_state_client (*dma_event_callback) (struct dma_client *client,
188 struct dma_chan *chan, enum dma_state state);
191 * typedef dma_filter_fn - callback filter for dma_request_channel
192 * @chan: channel to be reviewed
193 * @filter_param: opaque parameter passed through dma_request_channel
195 * When this optional parameter is specified in a call to dma_request_channel a
196 * suitable channel is passed to this routine for further dispositioning before
197 * being returned. Where 'suitable' indicates a non-busy channel that
198 * satisfies the given capability mask.
200 typedef enum dma_state_client (*dma_filter_fn)(struct dma_chan *chan, void *filter_param);
203 * struct dma_client - info on the entity making use of DMA services
204 * @event_callback: func ptr to call when something happens
205 * @cap_mask: only return channels that satisfy the requested capabilities
206 * a value of zero corresponds to any capability
207 * @slave: data for preparing slave transfer. Must be non-NULL iff the
208 * DMA_SLAVE capability is requested.
209 * @global_node: list_head for global dma_client_list
212 dma_event_callback event_callback;
213 dma_cap_mask_t cap_mask;
214 struct list_head global_node;
217 typedef void (*dma_async_tx_callback)(void *dma_async_param);
219 * struct dma_async_tx_descriptor - async transaction descriptor
220 * ---dma generic offload fields---
221 * @cookie: tracking cookie for this transaction, set to -EBUSY if
222 * this tx is sitting on a dependency list
223 * @flags: flags to augment operation preparation, control completion, and
225 * @phys: physical address of the descriptor
226 * @tx_list: driver common field for operations that require multiple
228 * @chan: target channel for this operation
229 * @tx_submit: set the prepared descriptor(s) to be executed by the engine
230 * @callback: routine to call after this operation is complete
231 * @callback_param: general parameter to pass to the callback routine
232 * ---async_tx api specific fields---
233 * @next: at completion submit this descriptor
234 * @parent: pointer to the next level up in the dependency chain
235 * @lock: protect the parent and next pointers
237 struct dma_async_tx_descriptor {
239 enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */
241 struct list_head tx_list;
242 struct dma_chan *chan;
243 dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx);
244 dma_async_tx_callback callback;
245 void *callback_param;
246 struct dma_async_tx_descriptor *next;
247 struct dma_async_tx_descriptor *parent;
252 * struct dma_device - info on the entity supplying DMA services
253 * @chancnt: how many DMA channels are supported
254 * @channels: the list of struct dma_chan
255 * @global_node: list_head for global dma_device_list
256 * @cap_mask: one or more dma_capability flags
257 * @max_xor: maximum number of xor sources, 0 if no capability
258 * @refcount: reference count
259 * @done: IO completion struct
260 * @dev_id: unique device ID
261 * @dev: struct device reference for dma mapping api
262 * @device_alloc_chan_resources: allocate resources and return the
263 * number of allocated descriptors
264 * @device_free_chan_resources: release DMA channel's resources
265 * @device_prep_dma_memcpy: prepares a memcpy operation
266 * @device_prep_dma_xor: prepares a xor operation
267 * @device_prep_dma_zero_sum: prepares a zero_sum operation
268 * @device_prep_dma_memset: prepares a memset operation
269 * @device_prep_dma_interrupt: prepares an end of chain interrupt operation
270 * @device_prep_slave_sg: prepares a slave dma operation
271 * @device_terminate_all: terminate all pending operations
272 * @device_issue_pending: push pending transactions to hardware
276 unsigned int chancnt;
277 struct list_head channels;
278 struct list_head global_node;
279 dma_cap_mask_t cap_mask;
282 struct kref refcount;
283 struct completion done;
288 int (*device_alloc_chan_resources)(struct dma_chan *chan,
289 struct dma_client *client);
290 void (*device_free_chan_resources)(struct dma_chan *chan);
292 struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)(
293 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
294 size_t len, unsigned long flags);
295 struct dma_async_tx_descriptor *(*device_prep_dma_xor)(
296 struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
297 unsigned int src_cnt, size_t len, unsigned long flags);
298 struct dma_async_tx_descriptor *(*device_prep_dma_zero_sum)(
299 struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt,
300 size_t len, u32 *result, unsigned long flags);
301 struct dma_async_tx_descriptor *(*device_prep_dma_memset)(
302 struct dma_chan *chan, dma_addr_t dest, int value, size_t len,
303 unsigned long flags);
304 struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)(
305 struct dma_chan *chan, unsigned long flags);
307 struct dma_async_tx_descriptor *(*device_prep_slave_sg)(
308 struct dma_chan *chan, struct scatterlist *sgl,
309 unsigned int sg_len, enum dma_data_direction direction,
310 unsigned long flags);
311 void (*device_terminate_all)(struct dma_chan *chan);
313 enum dma_status (*device_is_tx_complete)(struct dma_chan *chan,
314 dma_cookie_t cookie, dma_cookie_t *last,
316 void (*device_issue_pending)(struct dma_chan *chan);
319 /* --- public DMA engine API --- */
321 void dma_async_client_register(struct dma_client *client);
322 void dma_async_client_unregister(struct dma_client *client);
323 void dma_async_client_chan_request(struct dma_client *client);
324 dma_cookie_t dma_async_memcpy_buf_to_buf(struct dma_chan *chan,
325 void *dest, void *src, size_t len);
326 dma_cookie_t dma_async_memcpy_buf_to_pg(struct dma_chan *chan,
327 struct page *page, unsigned int offset, void *kdata, size_t len);
328 dma_cookie_t dma_async_memcpy_pg_to_pg(struct dma_chan *chan,
329 struct page *dest_pg, unsigned int dest_off, struct page *src_pg,
330 unsigned int src_off, size_t len);
331 void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
332 struct dma_chan *chan);
334 static inline void async_tx_ack(struct dma_async_tx_descriptor *tx)
336 tx->flags |= DMA_CTRL_ACK;
339 static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx)
341 return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK;
344 #define first_dma_cap(mask) __first_dma_cap(&(mask))
345 static inline int __first_dma_cap(const dma_cap_mask_t *srcp)
347 return min_t(int, DMA_TX_TYPE_END,
348 find_first_bit(srcp->bits, DMA_TX_TYPE_END));
351 #define next_dma_cap(n, mask) __next_dma_cap((n), &(mask))
352 static inline int __next_dma_cap(int n, const dma_cap_mask_t *srcp)
354 return min_t(int, DMA_TX_TYPE_END,
355 find_next_bit(srcp->bits, DMA_TX_TYPE_END, n+1));
358 #define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask))
360 __dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
362 set_bit(tx_type, dstp->bits);
365 #define dma_cap_zero(mask) __dma_cap_zero(&(mask))
366 static inline void __dma_cap_zero(dma_cap_mask_t *dstp)
368 bitmap_zero(dstp->bits, DMA_TX_TYPE_END);
371 #define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask))
373 __dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp)
375 return test_bit(tx_type, srcp->bits);
378 #define for_each_dma_cap_mask(cap, mask) \
379 for ((cap) = first_dma_cap(mask); \
380 (cap) < DMA_TX_TYPE_END; \
381 (cap) = next_dma_cap((cap), (mask)))
384 * dma_async_issue_pending - flush pending transactions to HW
385 * @chan: target DMA channel
387 * This allows drivers to push copies to HW in batches,
388 * reducing MMIO writes where possible.
390 static inline void dma_async_issue_pending(struct dma_chan *chan)
392 chan->device->device_issue_pending(chan);
395 #define dma_async_memcpy_issue_pending(chan) dma_async_issue_pending(chan)
398 * dma_async_is_tx_complete - poll for transaction completion
400 * @cookie: transaction identifier to check status of
401 * @last: returns last completed cookie, can be NULL
402 * @used: returns last issued cookie, can be NULL
404 * If @last and @used are passed in, upon return they reflect the driver
405 * internal state and can be used with dma_async_is_complete() to check
406 * the status of multiple cookies without re-checking hardware state.
408 static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan,
409 dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used)
411 return chan->device->device_is_tx_complete(chan, cookie, last, used);
414 #define dma_async_memcpy_complete(chan, cookie, last, used)\
415 dma_async_is_tx_complete(chan, cookie, last, used)
418 * dma_async_is_complete - test a cookie against chan state
419 * @cookie: transaction identifier to test status of
420 * @last_complete: last know completed transaction
421 * @last_used: last cookie value handed out
423 * dma_async_is_complete() is used in dma_async_memcpy_complete()
424 * the test logic is separated for lightweight testing of multiple cookies
426 static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie,
427 dma_cookie_t last_complete, dma_cookie_t last_used)
429 if (last_complete <= last_used) {
430 if ((cookie <= last_complete) || (cookie > last_used))
433 if ((cookie <= last_complete) && (cookie > last_used))
436 return DMA_IN_PROGRESS;
439 enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie);
440 #ifdef CONFIG_DMA_ENGINE
441 enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx);
443 static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
449 /* --- DMA device --- */
451 int dma_async_device_register(struct dma_device *device);
452 void dma_async_device_unregister(struct dma_device *device);
453 void dma_run_dependencies(struct dma_async_tx_descriptor *tx);
454 struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type);
455 void dma_issue_pending_all(void);
456 #define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y)
457 struct dma_chan *__dma_request_channel(dma_cap_mask_t *mask, dma_filter_fn fn, void *fn_param);
458 void dma_release_channel(struct dma_chan *chan);
460 /* --- Helper iov-locking functions --- */
462 struct dma_page_list {
463 char __user *base_address;
468 struct dma_pinned_list {
470 struct dma_page_list page_list[0];
473 struct dma_pinned_list *dma_pin_iovec_pages(struct iovec *iov, size_t len);
474 void dma_unpin_iovec_pages(struct dma_pinned_list* pinned_list);
476 dma_cookie_t dma_memcpy_to_iovec(struct dma_chan *chan, struct iovec *iov,
477 struct dma_pinned_list *pinned_list, unsigned char *kdata, size_t len);
478 dma_cookie_t dma_memcpy_pg_to_iovec(struct dma_chan *chan, struct iovec *iov,
479 struct dma_pinned_list *pinned_list, struct page *page,
480 unsigned int offset, size_t len);
482 #endif /* DMAENGINE_H */