2 * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59
16 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 * The full GNU General Public License is included in this distribution in the
19 * file called COPYING.
24 #include <linux/device.h>
25 #include <linux/uio.h>
26 #include <linux/kref.h>
27 #include <linux/completion.h>
28 #include <linux/rcupdate.h>
29 #include <linux/dma-mapping.h>
32 * enum dma_state - resource PNP/power management state
33 * @DMA_RESOURCE_SUSPEND: DMA device going into low power state
34 * @DMA_RESOURCE_RESUME: DMA device returning to full power
35 * @DMA_RESOURCE_AVAILABLE: DMA device available to the system
36 * @DMA_RESOURCE_REMOVED: DMA device removed from the system
41 DMA_RESOURCE_AVAILABLE,
46 * enum dma_state_client - state of the channel in the client
47 * @DMA_ACK: client would like to use, or was using this channel
48 * @DMA_DUP: client has already seen this channel, or is not using this channel
49 * @DMA_NAK: client does not want to see any more channels
51 enum dma_state_client {
58 * typedef dma_cookie_t - an opaque DMA cookie
60 * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code
62 typedef s32 dma_cookie_t;
64 #define dma_submit_error(cookie) ((cookie) < 0 ? 1 : 0)
67 * enum dma_status - DMA transaction status
68 * @DMA_SUCCESS: transaction completed successfully
69 * @DMA_IN_PROGRESS: transaction not yet processed
70 * @DMA_ERROR: transaction failed
79 * enum dma_transaction_type - DMA transaction types/indexes
81 enum dma_transaction_type {
96 /* last transaction type for creation of the capabilities mask */
97 #define DMA_TX_TYPE_END (DMA_SLAVE + 1)
100 * enum dma_slave_width - DMA slave register access width.
101 * @DMA_SLAVE_WIDTH_8BIT: Do 8-bit slave register accesses
102 * @DMA_SLAVE_WIDTH_16BIT: Do 16-bit slave register accesses
103 * @DMA_SLAVE_WIDTH_32BIT: Do 32-bit slave register accesses
105 enum dma_slave_width {
106 DMA_SLAVE_WIDTH_8BIT,
107 DMA_SLAVE_WIDTH_16BIT,
108 DMA_SLAVE_WIDTH_32BIT,
112 * enum dma_ctrl_flags - DMA flags to augment operation preparation,
113 * control completion, and communicate status.
114 * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of
116 * @DMA_CTRL_ACK - the descriptor cannot be reused until the client
117 * acknowledges receipt, i.e. has has a chance to establish any
119 * @DMA_COMPL_SKIP_SRC_UNMAP - set to disable dma-unmapping the source buffer(s)
120 * @DMA_COMPL_SKIP_DEST_UNMAP - set to disable dma-unmapping the destination(s)
122 enum dma_ctrl_flags {
123 DMA_PREP_INTERRUPT = (1 << 0),
124 DMA_CTRL_ACK = (1 << 1),
125 DMA_COMPL_SKIP_SRC_UNMAP = (1 << 2),
126 DMA_COMPL_SKIP_DEST_UNMAP = (1 << 3),
130 * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t.
131 * See linux/cpumask.h
133 typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t;
136 * struct dma_slave - Information about a DMA slave
137 * @dev: device acting as DMA slave
138 * @dma_dev: required DMA master device. If non-NULL, the client can not be
139 * bound to other masters than this.
140 * @tx_reg: physical address of data register used for
141 * memory-to-peripheral transfers
142 * @rx_reg: physical address of data register used for
143 * peripheral-to-memory transfers
144 * @reg_width: peripheral register width
146 * If dma_dev is non-NULL, the client can not be bound to other DMA
147 * masters than the one corresponding to this device. The DMA master
148 * driver may use this to determine if there is controller-specific
149 * data wrapped around this struct. Drivers of platform code that sets
150 * the dma_dev field must therefore make sure to use an appropriate
151 * controller-specific dma slave structure wrapping this struct.
155 struct device *dma_dev;
158 enum dma_slave_width reg_width;
162 * struct dma_chan_percpu - the per-CPU part of struct dma_chan
163 * @refcount: local_t used for open-coded "bigref" counting
164 * @memcpy_count: transaction counter
165 * @bytes_transferred: byte counter
168 struct dma_chan_percpu {
170 unsigned long memcpy_count;
171 unsigned long bytes_transferred;
175 * struct dma_chan - devices supply DMA channels, clients use them
176 * @device: ptr to the dma device who supplies this channel, always !%NULL
177 * @cookie: last cookie value returned to client
178 * @chan_id: channel ID for sysfs
179 * @class_dev: class device for sysfs
180 * @refcount: kref, used in "bigref" slow-mode
181 * @slow_ref: indicates that the DMA channel is free
182 * @rcu: the DMA channel's RCU head
183 * @device_node: used to add this to the device chan list
184 * @local: per-cpu pointer to a struct dma_chan_percpu
185 * @client-count: how many clients are using this channel
186 * @table_count: number of appearances in the mem-to-mem allocation table
189 struct dma_device *device;
196 struct kref refcount;
200 struct list_head device_node;
201 struct dma_chan_percpu *local;
206 #define to_dma_chan(p) container_of(p, struct dma_chan, dev)
208 void dma_chan_cleanup(struct kref *kref);
211 * typedef dma_event_callback - function pointer to a DMA event callback
212 * For each channel added to the system this routine is called for each client.
213 * If the client would like to use the channel it returns '1' to signal (ack)
214 * the dmaengine core to take out a reference on the channel and its
215 * corresponding device. A client must not 'ack' an available channel more
216 * than once. When a channel is removed all clients are notified. If a client
217 * is using the channel it must 'ack' the removal. A client must not 'ack' a
218 * removed channel more than once.
219 * @client - 'this' pointer for the client context
220 * @chan - channel to be acted upon
221 * @state - available or removed
224 typedef enum dma_state_client (*dma_event_callback) (struct dma_client *client,
225 struct dma_chan *chan, enum dma_state state);
228 * typedef dma_filter_fn - callback filter for dma_request_channel
229 * @chan: channel to be reviewed
230 * @filter_param: opaque parameter passed through dma_request_channel
232 * When this optional parameter is specified in a call to dma_request_channel a
233 * suitable channel is passed to this routine for further dispositioning before
234 * being returned. Where 'suitable' indicates a non-busy channel that
235 * satisfies the given capability mask.
237 typedef enum dma_state_client (*dma_filter_fn)(struct dma_chan *chan, void *filter_param);
240 * struct dma_client - info on the entity making use of DMA services
241 * @event_callback: func ptr to call when something happens
242 * @cap_mask: only return channels that satisfy the requested capabilities
243 * a value of zero corresponds to any capability
244 * @slave: data for preparing slave transfer. Must be non-NULL iff the
245 * DMA_SLAVE capability is requested.
246 * @global_node: list_head for global dma_client_list
249 dma_event_callback event_callback;
250 dma_cap_mask_t cap_mask;
251 struct dma_slave *slave;
252 struct list_head global_node;
255 typedef void (*dma_async_tx_callback)(void *dma_async_param);
257 * struct dma_async_tx_descriptor - async transaction descriptor
258 * ---dma generic offload fields---
259 * @cookie: tracking cookie for this transaction, set to -EBUSY if
260 * this tx is sitting on a dependency list
261 * @flags: flags to augment operation preparation, control completion, and
263 * @phys: physical address of the descriptor
264 * @tx_list: driver common field for operations that require multiple
266 * @chan: target channel for this operation
267 * @tx_submit: set the prepared descriptor(s) to be executed by the engine
268 * @callback: routine to call after this operation is complete
269 * @callback_param: general parameter to pass to the callback routine
270 * ---async_tx api specific fields---
271 * @next: at completion submit this descriptor
272 * @parent: pointer to the next level up in the dependency chain
273 * @lock: protect the parent and next pointers
275 struct dma_async_tx_descriptor {
277 enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */
279 struct list_head tx_list;
280 struct dma_chan *chan;
281 dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx);
282 dma_async_tx_callback callback;
283 void *callback_param;
284 struct dma_async_tx_descriptor *next;
285 struct dma_async_tx_descriptor *parent;
290 * struct dma_device - info on the entity supplying DMA services
291 * @chancnt: how many DMA channels are supported
292 * @channels: the list of struct dma_chan
293 * @global_node: list_head for global dma_device_list
294 * @cap_mask: one or more dma_capability flags
295 * @max_xor: maximum number of xor sources, 0 if no capability
296 * @refcount: reference count
297 * @done: IO completion struct
298 * @dev_id: unique device ID
299 * @dev: struct device reference for dma mapping api
300 * @device_alloc_chan_resources: allocate resources and return the
301 * number of allocated descriptors
302 * @device_free_chan_resources: release DMA channel's resources
303 * @device_prep_dma_memcpy: prepares a memcpy operation
304 * @device_prep_dma_xor: prepares a xor operation
305 * @device_prep_dma_zero_sum: prepares a zero_sum operation
306 * @device_prep_dma_memset: prepares a memset operation
307 * @device_prep_dma_interrupt: prepares an end of chain interrupt operation
308 * @device_prep_slave_sg: prepares a slave dma operation
309 * @device_terminate_all: terminate all pending operations
310 * @device_issue_pending: push pending transactions to hardware
314 unsigned int chancnt;
315 struct list_head channels;
316 struct list_head global_node;
317 dma_cap_mask_t cap_mask;
320 struct kref refcount;
321 struct completion done;
326 int (*device_alloc_chan_resources)(struct dma_chan *chan,
327 struct dma_client *client);
328 void (*device_free_chan_resources)(struct dma_chan *chan);
330 struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)(
331 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
332 size_t len, unsigned long flags);
333 struct dma_async_tx_descriptor *(*device_prep_dma_xor)(
334 struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
335 unsigned int src_cnt, size_t len, unsigned long flags);
336 struct dma_async_tx_descriptor *(*device_prep_dma_zero_sum)(
337 struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt,
338 size_t len, u32 *result, unsigned long flags);
339 struct dma_async_tx_descriptor *(*device_prep_dma_memset)(
340 struct dma_chan *chan, dma_addr_t dest, int value, size_t len,
341 unsigned long flags);
342 struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)(
343 struct dma_chan *chan, unsigned long flags);
345 struct dma_async_tx_descriptor *(*device_prep_slave_sg)(
346 struct dma_chan *chan, struct scatterlist *sgl,
347 unsigned int sg_len, enum dma_data_direction direction,
348 unsigned long flags);
349 void (*device_terminate_all)(struct dma_chan *chan);
351 enum dma_status (*device_is_tx_complete)(struct dma_chan *chan,
352 dma_cookie_t cookie, dma_cookie_t *last,
354 void (*device_issue_pending)(struct dma_chan *chan);
357 /* --- public DMA engine API --- */
359 void dma_async_client_register(struct dma_client *client);
360 void dma_async_client_unregister(struct dma_client *client);
361 void dma_async_client_chan_request(struct dma_client *client);
362 dma_cookie_t dma_async_memcpy_buf_to_buf(struct dma_chan *chan,
363 void *dest, void *src, size_t len);
364 dma_cookie_t dma_async_memcpy_buf_to_pg(struct dma_chan *chan,
365 struct page *page, unsigned int offset, void *kdata, size_t len);
366 dma_cookie_t dma_async_memcpy_pg_to_pg(struct dma_chan *chan,
367 struct page *dest_pg, unsigned int dest_off, struct page *src_pg,
368 unsigned int src_off, size_t len);
369 void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
370 struct dma_chan *chan);
372 static inline void async_tx_ack(struct dma_async_tx_descriptor *tx)
374 tx->flags |= DMA_CTRL_ACK;
377 static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx)
379 return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK;
382 #define first_dma_cap(mask) __first_dma_cap(&(mask))
383 static inline int __first_dma_cap(const dma_cap_mask_t *srcp)
385 return min_t(int, DMA_TX_TYPE_END,
386 find_first_bit(srcp->bits, DMA_TX_TYPE_END));
389 #define next_dma_cap(n, mask) __next_dma_cap((n), &(mask))
390 static inline int __next_dma_cap(int n, const dma_cap_mask_t *srcp)
392 return min_t(int, DMA_TX_TYPE_END,
393 find_next_bit(srcp->bits, DMA_TX_TYPE_END, n+1));
396 #define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask))
398 __dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
400 set_bit(tx_type, dstp->bits);
403 #define dma_cap_zero(mask) __dma_cap_zero(&(mask))
404 static inline void __dma_cap_zero(dma_cap_mask_t *dstp)
406 bitmap_zero(dstp->bits, DMA_TX_TYPE_END);
409 #define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask))
411 __dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp)
413 return test_bit(tx_type, srcp->bits);
416 #define for_each_dma_cap_mask(cap, mask) \
417 for ((cap) = first_dma_cap(mask); \
418 (cap) < DMA_TX_TYPE_END; \
419 (cap) = next_dma_cap((cap), (mask)))
422 * dma_async_issue_pending - flush pending transactions to HW
423 * @chan: target DMA channel
425 * This allows drivers to push copies to HW in batches,
426 * reducing MMIO writes where possible.
428 static inline void dma_async_issue_pending(struct dma_chan *chan)
430 chan->device->device_issue_pending(chan);
433 #define dma_async_memcpy_issue_pending(chan) dma_async_issue_pending(chan)
436 * dma_async_is_tx_complete - poll for transaction completion
438 * @cookie: transaction identifier to check status of
439 * @last: returns last completed cookie, can be NULL
440 * @used: returns last issued cookie, can be NULL
442 * If @last and @used are passed in, upon return they reflect the driver
443 * internal state and can be used with dma_async_is_complete() to check
444 * the status of multiple cookies without re-checking hardware state.
446 static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan,
447 dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used)
449 return chan->device->device_is_tx_complete(chan, cookie, last, used);
452 #define dma_async_memcpy_complete(chan, cookie, last, used)\
453 dma_async_is_tx_complete(chan, cookie, last, used)
456 * dma_async_is_complete - test a cookie against chan state
457 * @cookie: transaction identifier to test status of
458 * @last_complete: last know completed transaction
459 * @last_used: last cookie value handed out
461 * dma_async_is_complete() is used in dma_async_memcpy_complete()
462 * the test logic is separated for lightweight testing of multiple cookies
464 static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie,
465 dma_cookie_t last_complete, dma_cookie_t last_used)
467 if (last_complete <= last_used) {
468 if ((cookie <= last_complete) || (cookie > last_used))
471 if ((cookie <= last_complete) && (cookie > last_used))
474 return DMA_IN_PROGRESS;
477 enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie);
478 #ifdef CONFIG_DMA_ENGINE
479 enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx);
481 static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
487 /* --- DMA device --- */
489 int dma_async_device_register(struct dma_device *device);
490 void dma_async_device_unregister(struct dma_device *device);
491 void dma_run_dependencies(struct dma_async_tx_descriptor *tx);
492 struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type);
493 void dma_issue_pending_all(void);
494 #define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y)
495 struct dma_chan *__dma_request_channel(dma_cap_mask_t *mask, dma_filter_fn fn, void *fn_param);
496 void dma_release_channel(struct dma_chan *chan);
498 /* --- Helper iov-locking functions --- */
500 struct dma_page_list {
501 char __user *base_address;
506 struct dma_pinned_list {
508 struct dma_page_list page_list[0];
511 struct dma_pinned_list *dma_pin_iovec_pages(struct iovec *iov, size_t len);
512 void dma_unpin_iovec_pages(struct dma_pinned_list* pinned_list);
514 dma_cookie_t dma_memcpy_to_iovec(struct dma_chan *chan, struct iovec *iov,
515 struct dma_pinned_list *pinned_list, unsigned char *kdata, size_t len);
516 dma_cookie_t dma_memcpy_pg_to_iovec(struct dma_chan *chan, struct iovec *iov,
517 struct dma_pinned_list *pinned_list, struct page *page,
518 unsigned int offset, size_t len);
520 #endif /* DMAENGINE_H */