2 * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59
16 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 * The full GNU General Public License is included in this distribution in the
19 * file called COPYING.
24 #include <linux/device.h>
25 #include <linux/uio.h>
26 #include <linux/kref.h>
27 #include <linux/completion.h>
28 #include <linux/rcupdate.h>
29 #include <linux/dma-mapping.h>
32 * typedef dma_cookie_t - an opaque DMA cookie
34 * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code
36 typedef s32 dma_cookie_t;
38 #define dma_submit_error(cookie) ((cookie) < 0 ? 1 : 0)
41 * enum dma_status - DMA transaction status
42 * @DMA_SUCCESS: transaction completed successfully
43 * @DMA_IN_PROGRESS: transaction not yet processed
44 * @DMA_ERROR: transaction failed
53 * enum dma_transaction_type - DMA transaction types/indexes
55 enum dma_transaction_type {
70 /* last transaction type for creation of the capabilities mask */
71 #define DMA_TX_TYPE_END (DMA_SLAVE + 1)
75 * enum dma_ctrl_flags - DMA flags to augment operation preparation,
76 * control completion, and communicate status.
77 * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of
79 * @DMA_CTRL_ACK - the descriptor cannot be reused until the client
80 * acknowledges receipt, i.e. has has a chance to establish any
82 * @DMA_COMPL_SKIP_SRC_UNMAP - set to disable dma-unmapping the source buffer(s)
83 * @DMA_COMPL_SKIP_DEST_UNMAP - set to disable dma-unmapping the destination(s)
86 DMA_PREP_INTERRUPT = (1 << 0),
87 DMA_CTRL_ACK = (1 << 1),
88 DMA_COMPL_SKIP_SRC_UNMAP = (1 << 2),
89 DMA_COMPL_SKIP_DEST_UNMAP = (1 << 3),
93 * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t.
96 typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t;
99 * struct dma_chan_percpu - the per-CPU part of struct dma_chan
100 * @refcount: local_t used for open-coded "bigref" counting
101 * @memcpy_count: transaction counter
102 * @bytes_transferred: byte counter
105 struct dma_chan_percpu {
107 unsigned long memcpy_count;
108 unsigned long bytes_transferred;
112 * struct dma_chan - devices supply DMA channels, clients use them
113 * @device: ptr to the dma device who supplies this channel, always !%NULL
114 * @cookie: last cookie value returned to client
115 * @chan_id: channel ID for sysfs
116 * @class_dev: class device for sysfs
117 * @refcount: kref, used in "bigref" slow-mode
118 * @slow_ref: indicates that the DMA channel is free
119 * @rcu: the DMA channel's RCU head
120 * @device_node: used to add this to the device chan list
121 * @local: per-cpu pointer to a struct dma_chan_percpu
122 * @client-count: how many clients are using this channel
123 * @table_count: number of appearances in the mem-to-mem allocation table
126 struct dma_device *device;
133 struct list_head device_node;
134 struct dma_chan_percpu *local;
139 #define to_dma_chan(p) container_of(p, struct dma_chan, dev)
141 void dma_chan_cleanup(struct kref *kref);
144 * typedef dma_filter_fn - callback filter for dma_request_channel
145 * @chan: channel to be reviewed
146 * @filter_param: opaque parameter passed through dma_request_channel
148 * When this optional parameter is specified in a call to dma_request_channel a
149 * suitable channel is passed to this routine for further dispositioning before
150 * being returned. Where 'suitable' indicates a non-busy channel that
151 * satisfies the given capability mask. It returns 'true' to indicate that the
152 * channel is suitable.
154 typedef bool (*dma_filter_fn)(struct dma_chan *chan, void *filter_param);
156 typedef void (*dma_async_tx_callback)(void *dma_async_param);
158 * struct dma_async_tx_descriptor - async transaction descriptor
159 * ---dma generic offload fields---
160 * @cookie: tracking cookie for this transaction, set to -EBUSY if
161 * this tx is sitting on a dependency list
162 * @flags: flags to augment operation preparation, control completion, and
164 * @phys: physical address of the descriptor
165 * @tx_list: driver common field for operations that require multiple
167 * @chan: target channel for this operation
168 * @tx_submit: set the prepared descriptor(s) to be executed by the engine
169 * @callback: routine to call after this operation is complete
170 * @callback_param: general parameter to pass to the callback routine
171 * ---async_tx api specific fields---
172 * @next: at completion submit this descriptor
173 * @parent: pointer to the next level up in the dependency chain
174 * @lock: protect the parent and next pointers
176 struct dma_async_tx_descriptor {
178 enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */
180 struct list_head tx_list;
181 struct dma_chan *chan;
182 dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx);
183 dma_async_tx_callback callback;
184 void *callback_param;
185 struct dma_async_tx_descriptor *next;
186 struct dma_async_tx_descriptor *parent;
191 * struct dma_device - info on the entity supplying DMA services
192 * @chancnt: how many DMA channels are supported
193 * @channels: the list of struct dma_chan
194 * @global_node: list_head for global dma_device_list
195 * @cap_mask: one or more dma_capability flags
196 * @max_xor: maximum number of xor sources, 0 if no capability
197 * @refcount: reference count
198 * @done: IO completion struct
199 * @dev_id: unique device ID
200 * @dev: struct device reference for dma mapping api
201 * @device_alloc_chan_resources: allocate resources and return the
202 * number of allocated descriptors
203 * @device_free_chan_resources: release DMA channel's resources
204 * @device_prep_dma_memcpy: prepares a memcpy operation
205 * @device_prep_dma_xor: prepares a xor operation
206 * @device_prep_dma_zero_sum: prepares a zero_sum operation
207 * @device_prep_dma_memset: prepares a memset operation
208 * @device_prep_dma_interrupt: prepares an end of chain interrupt operation
209 * @device_prep_slave_sg: prepares a slave dma operation
210 * @device_terminate_all: terminate all pending operations
211 * @device_issue_pending: push pending transactions to hardware
215 unsigned int chancnt;
216 struct list_head channels;
217 struct list_head global_node;
218 dma_cap_mask_t cap_mask;
224 int (*device_alloc_chan_resources)(struct dma_chan *chan);
225 void (*device_free_chan_resources)(struct dma_chan *chan);
227 struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)(
228 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
229 size_t len, unsigned long flags);
230 struct dma_async_tx_descriptor *(*device_prep_dma_xor)(
231 struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
232 unsigned int src_cnt, size_t len, unsigned long flags);
233 struct dma_async_tx_descriptor *(*device_prep_dma_zero_sum)(
234 struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt,
235 size_t len, u32 *result, unsigned long flags);
236 struct dma_async_tx_descriptor *(*device_prep_dma_memset)(
237 struct dma_chan *chan, dma_addr_t dest, int value, size_t len,
238 unsigned long flags);
239 struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)(
240 struct dma_chan *chan, unsigned long flags);
242 struct dma_async_tx_descriptor *(*device_prep_slave_sg)(
243 struct dma_chan *chan, struct scatterlist *sgl,
244 unsigned int sg_len, enum dma_data_direction direction,
245 unsigned long flags);
246 void (*device_terminate_all)(struct dma_chan *chan);
248 enum dma_status (*device_is_tx_complete)(struct dma_chan *chan,
249 dma_cookie_t cookie, dma_cookie_t *last,
251 void (*device_issue_pending)(struct dma_chan *chan);
254 /* --- public DMA engine API --- */
256 void dmaengine_get(void);
257 void dmaengine_put(void);
258 dma_cookie_t dma_async_memcpy_buf_to_buf(struct dma_chan *chan,
259 void *dest, void *src, size_t len);
260 dma_cookie_t dma_async_memcpy_buf_to_pg(struct dma_chan *chan,
261 struct page *page, unsigned int offset, void *kdata, size_t len);
262 dma_cookie_t dma_async_memcpy_pg_to_pg(struct dma_chan *chan,
263 struct page *dest_pg, unsigned int dest_off, struct page *src_pg,
264 unsigned int src_off, size_t len);
265 void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
266 struct dma_chan *chan);
268 static inline void async_tx_ack(struct dma_async_tx_descriptor *tx)
270 tx->flags |= DMA_CTRL_ACK;
273 static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx)
275 return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK;
278 #define first_dma_cap(mask) __first_dma_cap(&(mask))
279 static inline int __first_dma_cap(const dma_cap_mask_t *srcp)
281 return min_t(int, DMA_TX_TYPE_END,
282 find_first_bit(srcp->bits, DMA_TX_TYPE_END));
285 #define next_dma_cap(n, mask) __next_dma_cap((n), &(mask))
286 static inline int __next_dma_cap(int n, const dma_cap_mask_t *srcp)
288 return min_t(int, DMA_TX_TYPE_END,
289 find_next_bit(srcp->bits, DMA_TX_TYPE_END, n+1));
292 #define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask))
294 __dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
296 set_bit(tx_type, dstp->bits);
299 #define dma_cap_zero(mask) __dma_cap_zero(&(mask))
300 static inline void __dma_cap_zero(dma_cap_mask_t *dstp)
302 bitmap_zero(dstp->bits, DMA_TX_TYPE_END);
305 #define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask))
307 __dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp)
309 return test_bit(tx_type, srcp->bits);
312 #define for_each_dma_cap_mask(cap, mask) \
313 for ((cap) = first_dma_cap(mask); \
314 (cap) < DMA_TX_TYPE_END; \
315 (cap) = next_dma_cap((cap), (mask)))
318 * dma_async_issue_pending - flush pending transactions to HW
319 * @chan: target DMA channel
321 * This allows drivers to push copies to HW in batches,
322 * reducing MMIO writes where possible.
324 static inline void dma_async_issue_pending(struct dma_chan *chan)
326 chan->device->device_issue_pending(chan);
329 #define dma_async_memcpy_issue_pending(chan) dma_async_issue_pending(chan)
332 * dma_async_is_tx_complete - poll for transaction completion
334 * @cookie: transaction identifier to check status of
335 * @last: returns last completed cookie, can be NULL
336 * @used: returns last issued cookie, can be NULL
338 * If @last and @used are passed in, upon return they reflect the driver
339 * internal state and can be used with dma_async_is_complete() to check
340 * the status of multiple cookies without re-checking hardware state.
342 static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan,
343 dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used)
345 return chan->device->device_is_tx_complete(chan, cookie, last, used);
348 #define dma_async_memcpy_complete(chan, cookie, last, used)\
349 dma_async_is_tx_complete(chan, cookie, last, used)
352 * dma_async_is_complete - test a cookie against chan state
353 * @cookie: transaction identifier to test status of
354 * @last_complete: last know completed transaction
355 * @last_used: last cookie value handed out
357 * dma_async_is_complete() is used in dma_async_memcpy_complete()
358 * the test logic is separated for lightweight testing of multiple cookies
360 static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie,
361 dma_cookie_t last_complete, dma_cookie_t last_used)
363 if (last_complete <= last_used) {
364 if ((cookie <= last_complete) || (cookie > last_used))
367 if ((cookie <= last_complete) && (cookie > last_used))
370 return DMA_IN_PROGRESS;
373 enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie);
374 #ifdef CONFIG_DMA_ENGINE
375 enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx);
377 static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
383 /* --- DMA device --- */
385 int dma_async_device_register(struct dma_device *device);
386 void dma_async_device_unregister(struct dma_device *device);
387 void dma_run_dependencies(struct dma_async_tx_descriptor *tx);
388 struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type);
389 void dma_issue_pending_all(void);
390 #define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y)
391 struct dma_chan *__dma_request_channel(dma_cap_mask_t *mask, dma_filter_fn fn, void *fn_param);
392 void dma_release_channel(struct dma_chan *chan);
394 /* --- Helper iov-locking functions --- */
396 struct dma_page_list {
397 char __user *base_address;
402 struct dma_pinned_list {
404 struct dma_page_list page_list[0];
407 struct dma_pinned_list *dma_pin_iovec_pages(struct iovec *iov, size_t len);
408 void dma_unpin_iovec_pages(struct dma_pinned_list* pinned_list);
410 dma_cookie_t dma_memcpy_to_iovec(struct dma_chan *chan, struct iovec *iov,
411 struct dma_pinned_list *pinned_list, unsigned char *kdata, size_t len);
412 dma_cookie_t dma_memcpy_pg_to_iovec(struct dma_chan *chan, struct iovec *iov,
413 struct dma_pinned_list *pinned_list, struct page *page,
414 unsigned int offset, size_t len);
416 #endif /* DMAENGINE_H */