2 * AMD CS5535/CS5536 definitions
3 * Copyright (C) 2006 Advanced Micro Devices, Inc.
4 * Copyright (C) 2009 Andres Salomon <dilinger@collabora.co.uk>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of version 2 of the GNU General Public License
8 * as published by the Free Software Foundation.
17 #define MSR_GLIU_P2D_RO0 0x10000029
19 #define MSR_LX_GLD_MSR_CONFIG 0x48002001
20 #define MSR_LX_MSR_PADSEL 0x48002011 /* NOT 0x48000011; the data
21 * sheet has the wrong value */
22 #define MSR_GLCP_SYS_RSTPLL 0x4C000014
23 #define MSR_GLCP_DOTPLL 0x4C000015
25 #define MSR_LBAR_SMB 0x5140000B
26 #define MSR_LBAR_GPIO 0x5140000C
27 #define MSR_LBAR_MFGPT 0x5140000D
28 #define MSR_LBAR_ACPI 0x5140000E
29 #define MSR_LBAR_PMS 0x5140000F
31 #define MSR_DIVIL_SOFT_RESET 0x51400017
33 #define MSR_PIC_YSEL_LOW 0x51400020
34 #define MSR_PIC_YSEL_HIGH 0x51400021
35 #define MSR_PIC_ZSEL_LOW 0x51400022
36 #define MSR_PIC_ZSEL_HIGH 0x51400023
37 #define MSR_PIC_IRQM_LPC 0x51400025
39 #define MSR_MFGPT_IRQ 0x51400028
40 #define MSR_MFGPT_NR 0x51400029
41 #define MSR_MFGPT_SETUP 0x5140002B
43 #define MSR_LX_SPARE_MSR 0x80000011 /* DC-specific */
45 #define MSR_GX_GLD_MSR_CONFIG 0xC0002001
46 #define MSR_GX_MSR_PADSEL 0xC0002011
48 static inline int cs5535_pic_unreqz_select_high(unsigned int group,
53 rdmsr(MSR_PIC_ZSEL_HIGH, lo, hi);
54 lo &= ~(0xF << (group * 4));
55 lo |= (irq & 0xF) << (group * 4);
56 wrmsr(MSR_PIC_ZSEL_HIGH, lo, hi);
61 #define CS5536_PIC_INT_SEL1 0x4d0
62 #define CS5536_PIC_INT_SEL2 0x4d1
65 #define LBAR_GPIO_SIZE 0xFF
66 #define LBAR_MFGPT_SIZE 0x40
67 #define LBAR_ACPI_SIZE 0x40
68 #define LBAR_PMS_SIZE 0x80
71 * PMC registers (PMS block)
72 * It is only safe to access these registers as dword accesses.
73 * See CS5536 Specification Update erratas 17 & 18
75 #define CS5536_PM_SCLK 0x10
76 #define CS5536_PM_IN_SLPCTL 0x20
77 #define CS5536_PM_WKXD 0x34
78 #define CS5536_PM_WKD 0x30
79 #define CS5536_PM_SSC 0x54
82 * PM registers (ACPI block)
83 * It is only safe to access these registers as dword accesses.
84 * See CS5536 Specification Update erratas 17 & 18
86 #define CS5536_PM1_STS 0x00
87 #define CS5536_PM1_EN 0x02
88 #define CS5536_PM1_CNT 0x08
89 #define CS5536_PM_GPE0_STS 0x18
90 #define CS5536_PM_GPE0_EN 0x1c
92 /* CS5536_PM1_STS bits */
93 #define CS5536_WAK_FLAG (1 << 15)
94 #define CS5536_PWRBTN_FLAG (1 << 8)
96 /* CS5536_PM1_EN bits */
97 #define CS5536_PM_PWRBTN (1 << 8)
99 /* CS5536_PM_GPE0_STS bits */
100 #define CS5536_GPIOM7_PME_FLAG (1 << 31)
101 #define CS5536_GPIOM6_PME_FLAG (1 << 30)
103 /* CS5536_PM_GPE0_EN bits */
104 #define CS5536_GPIOM7_PME_EN (1 << 31)
105 #define CS5536_GPIOM6_PME_EN (1 << 30)
107 /* VSA2 magic values */
108 #define VSA_VRC_INDEX 0xAC1C
109 #define VSA_VRC_DATA 0xAC1E
110 #define VSA_VR_UNLOCK 0xFC53 /* unlock virtual register */
111 #define VSA_VR_SIGNATURE 0x0003
112 #define VSA_VR_MEM_SIZE 0x0200
113 #define AMD_VSA_SIG 0x4132 /* signature is ascii 'VSA2' */
114 #define GSW_VSA_SIG 0x534d /* General Software signature */
116 #include <linux/io.h>
118 static inline int cs5535_has_vsa2(void)
120 static int has_vsa2 = -1;
122 if (has_vsa2 == -1) {
126 * The VSA has virtual registers that we can query for a
129 outw(VSA_VR_UNLOCK, VSA_VRC_INDEX);
130 outw(VSA_VR_SIGNATURE, VSA_VRC_INDEX);
132 val = inw(VSA_VRC_DATA);
133 has_vsa2 = (val == AMD_VSA_SIG || val == GSW_VSA_SIG);
140 #define GPIO_OUTPUT_VAL 0x00
141 #define GPIO_OUTPUT_ENABLE 0x04
142 #define GPIO_OUTPUT_OPEN_DRAIN 0x08
143 #define GPIO_OUTPUT_INVERT 0x0C
144 #define GPIO_OUTPUT_AUX1 0x10
145 #define GPIO_OUTPUT_AUX2 0x14
146 #define GPIO_PULL_UP 0x18
147 #define GPIO_PULL_DOWN 0x1C
148 #define GPIO_INPUT_ENABLE 0x20
149 #define GPIO_INPUT_INVERT 0x24
150 #define GPIO_INPUT_FILTER 0x28
151 #define GPIO_INPUT_EVENT_COUNT 0x2C
152 #define GPIO_READ_BACK 0x30
153 #define GPIO_INPUT_AUX1 0x34
154 #define GPIO_EVENTS_ENABLE 0x38
155 #define GPIO_LOCK_ENABLE 0x3C
156 #define GPIO_POSITIVE_EDGE_EN 0x40
157 #define GPIO_NEGATIVE_EDGE_EN 0x44
158 #define GPIO_POSITIVE_EDGE_STS 0x48
159 #define GPIO_NEGATIVE_EDGE_STS 0x4C
161 #define GPIO_FLTR7_AMOUNT 0xD8
163 #define GPIO_MAP_X 0xE0
164 #define GPIO_MAP_Y 0xE4
165 #define GPIO_MAP_Z 0xE8
166 #define GPIO_MAP_W 0xEC
168 #define GPIO_FE7_SEL 0xF7
170 void cs5535_gpio_set(unsigned offset, unsigned int reg);
171 void cs5535_gpio_clear(unsigned offset, unsigned int reg);
172 int cs5535_gpio_isset(unsigned offset, unsigned int reg);
173 int cs5535_gpio_set_irq(unsigned group, unsigned irq);
174 void cs5535_gpio_setup_event(unsigned offset, int pair, int pme);
178 #define MFGPT_MAX_TIMERS 8
179 #define MFGPT_TIMER_ANY (-1)
181 #define MFGPT_DOMAIN_WORKING 1
182 #define MFGPT_DOMAIN_STANDBY 2
183 #define MFGPT_DOMAIN_ANY (MFGPT_DOMAIN_WORKING | MFGPT_DOMAIN_STANDBY)
188 #define MFGPT_EVENT_IRQ 0
189 #define MFGPT_EVENT_NMI 1
190 #define MFGPT_EVENT_RESET 3
192 #define MFGPT_REG_CMP1 0
193 #define MFGPT_REG_CMP2 2
194 #define MFGPT_REG_COUNTER 4
195 #define MFGPT_REG_SETUP 6
197 #define MFGPT_SETUP_CNTEN (1 << 15)
198 #define MFGPT_SETUP_CMP2 (1 << 14)
199 #define MFGPT_SETUP_CMP1 (1 << 13)
200 #define MFGPT_SETUP_SETUP (1 << 12)
201 #define MFGPT_SETUP_STOPEN (1 << 11)
202 #define MFGPT_SETUP_EXTEN (1 << 10)
203 #define MFGPT_SETUP_REVEN (1 << 5)
204 #define MFGPT_SETUP_CLKSEL (1 << 4)
206 struct cs5535_mfgpt_timer;
208 extern uint16_t cs5535_mfgpt_read(struct cs5535_mfgpt_timer *timer,
210 extern void cs5535_mfgpt_write(struct cs5535_mfgpt_timer *timer, uint16_t reg,
213 extern int cs5535_mfgpt_toggle_event(struct cs5535_mfgpt_timer *timer, int cmp,
214 int event, int enable);
215 extern int cs5535_mfgpt_set_irq(struct cs5535_mfgpt_timer *timer, int cmp,
216 int *irq, int enable);
217 extern struct cs5535_mfgpt_timer *cs5535_mfgpt_alloc_timer(int timer,
219 extern void cs5535_mfgpt_free_timer(struct cs5535_mfgpt_timer *timer);
221 static inline int cs5535_mfgpt_setup_irq(struct cs5535_mfgpt_timer *timer,
224 return cs5535_mfgpt_set_irq(timer, cmp, irq, 1);
227 static inline int cs5535_mfgpt_release_irq(struct cs5535_mfgpt_timer *timer,
230 return cs5535_mfgpt_set_irq(timer, cmp, irq, 0);