1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2014 Freescale Semiconductor
11 #include <linux/bitops.h>
13 #define MC_CCSR_BASE_ADDR \
14 ((struct mc_ccsr_registers __iomem *)0x8340000)
16 #define GCR1_P1_STOP BIT(31)
17 #define GCR1_P2_STOP BIT(30)
18 #define GCR1_P1_DE_RST BIT(23)
19 #define GCR1_P2_DE_RST BIT(22)
20 #define GCR1_M1_DE_RST BIT(15)
21 #define GCR1_M2_DE_RST BIT(14)
22 #define GCR1_M_ALL_DE_RST (GCR1_M1_DE_RST | GCR1_M2_DE_RST)
23 #define GSR_FS_MASK 0x3fffffff
25 #define SOC_MC_PORTALS_BASE_ADDR ((void __iomem *)0x00080C000000)
26 #define SOC_QBMAN_PORTALS_BASE_ADDR ((void __iomem *)0x000818000000)
27 #define SOC_MC_PORTAL_STRIDE 0x10000
29 #define SOC_MC_PORTAL_ADDR(_portal_id) \
30 ((void __iomem *)((uintptr_t)SOC_MC_PORTALS_BASE_ADDR + \
31 (_portal_id) * SOC_MC_PORTAL_STRIDE))
33 #define MC_PORTAL_OFFSET_TO_PORTAL_ID(_portal_offset) \
34 ((_portal_offset) / SOC_MC_PORTAL_STRIDE)
36 struct mc_ccsr_registers {
64 void fdt_fsl_mc_fixup_iommu_map_entry(void *blob);
65 int get_mc_boot_status(void);
66 int get_dpl_apply_status(void);
67 int is_lazy_dpl_addr_valid(void);
68 void fdt_fixup_mc_ddr(u64 *base, u64 *size);
69 #ifdef CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
70 int get_aiop_apply_status(void);
72 u64 mc_get_dram_addr(void);
73 unsigned long mc_get_dram_block_size(void);
74 int fsl_mc_ldpaa_init(struct bd_info *bis);
75 int fsl_mc_ldpaa_exit(struct bd_info *bd);
76 void mc_env_boot(void);