1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2020 Hitachi Power Grids. All rights reserved.
6 #ifndef __CONFIG_PG_WCOM_LS102XA_H
7 #define __CONFIG_PG_WCOM_LS102XA_H
9 #define CONFIG_SYS_FSL_CLK
11 #define CONFIG_SKIP_LOWLEVEL_INIT
13 /* include common defines/options for all Keymile boards */
14 #include "keymile-common.h"
17 * Size of malloc() pool
19 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
21 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
22 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
24 #define CONFIG_SYS_CLK_FREQ 66666666
26 * Take into account default implementation where DDR_FDBK_MULTI is consider as
27 * configured for DDR_PLL = 2*MEM_PLL_RAT.
28 * In our case DDR_FDBK_MULTI is 2, means DDR_PLL = MEM_PLL_RAT.
30 #define CONFIG_DDR_CLK_FREQ (100000000 >> 1)
32 #define PHYS_SDRAM 0x80000000
33 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
35 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
36 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
38 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
39 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
41 #define CONFIG_DDR_SPD
43 #define CONFIG_SYS_SPD_BUS_NUM 0
44 #define SPD_EEPROM_ADDRESS 0x54
49 /* NOR Flash Definitions */
50 #define CONFIG_FSL_IFC
51 #define CONFIG_SYS_FLASH_BASE 0x60000000
52 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
54 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
55 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
60 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(64 * 1024 * 1024)
62 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_AVD_TGL_PGM_EN | \
63 CSOR_NOR_ADM_SHIFT(0x4) | \
64 CSOR_NOR_NOR_MODE_ASYNC_NOR | \
67 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
68 FTIM0_NOR_TEADC(0x7) | \
69 FTIM0_NOR_TAVDS(0x0) | \
71 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \
72 FTIM1_NOR_TRAD_NOR(0x21) | \
73 FTIM1_NOR_TSEQRAD_NOR(0x21))
74 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) | \
75 FTIM2_NOR_TCH(0x1) | \
76 FTIM2_NOR_TWPH(0x6) | \
78 #define CONFIG_SYS_NOR_FTIM3 0
80 #define CONFIG_SYS_FLASH_QUIET_TEST
81 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
83 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
84 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
85 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
86 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
88 #define CONFIG_SYS_FLASH_EMPTY_INFO
89 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
91 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
92 #define CONFIG_SYS_WRITE_SWAPPED_DATA
94 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
95 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
96 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
97 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
98 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
99 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
100 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
101 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
103 /* NAND Flash Definitions */
104 #define CONFIG_NAND_FSL_IFC
105 #define CONFIG_SYS_NAND_BASE 0x68000000
106 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
108 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
109 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE) | \
114 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
115 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN \
116 | CSOR_NAND_ECC_DEC_EN \
117 | CSOR_NAND_ECC_MODE_4 \
120 | CSOR_NAND_SPRZ_64 \
122 | CSOR_NAND_TRHZ_40 \
125 #define CONFIG_SYS_NAND_ONFI_DETECTION
127 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x3) | \
128 FTIM0_NAND_TWP(0x8) | \
129 FTIM0_NAND_TWCHT(0x3) | \
131 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1e) | \
132 FTIM1_NAND_TWBE(0x1e) | \
133 FTIM1_NAND_TRR(0x6) | \
135 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x9) | \
136 FTIM2_NAND_TREH(0x5) | \
137 FTIM2_NAND_TWHRE(0x3c))
138 #define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x1e))
140 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
141 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
142 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
143 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
144 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
145 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
146 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
147 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
149 #define CONFIG_SYS_MAX_NAND_DEVICE 1
150 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
151 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
153 /* QRIO FPGA Definitions */
154 #define CONFIG_SYS_QRIO_BASE 0x70000000
155 #define CONFIG_SYS_QRIO_BASE_PHYS CONFIG_SYS_QRIO_BASE
157 #define CONFIG_SYS_CSPR2_EXT (0x00)
158 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE) | \
163 #define CONFIG_SYS_AMASK2 IFC_AMASK(64 * 1024)
164 #define CONFIG_SYS_CSOR2 (CSOR_GPCM_ADM_SHIFT(0x4) | \
165 CSOR_GPCM_TRHZ_20 | \
167 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x2) | \
168 FTIM0_GPCM_TEADC(0x8) | \
169 FTIM0_GPCM_TEAHC(0x2))
170 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x2) | \
171 FTIM1_GPCM_TRAD(0x6))
172 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x1) | \
173 FTIM2_GPCM_TCH(0x1) | \
175 #define CONFIG_SYS_CS2_FTIM3 0x04000000
180 #define CONFIG_SYS_NS16550_SERIAL
181 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
186 #define CONFIG_SYS_I2C
187 #define CONFIG_SYS_I2C_INIT_BOARD
188 #define CONFIG_SYS_I2C_SPEED 100000
190 #define CONFIG_I2C_MULTI_BUS
191 #define CONFIG_SYS_I2C_MAX_HOPS 1
192 #define CONFIG_SYS_NUM_I2C_BUSES 3
193 #define I2C_MUX_PCA_ADDR 0x70
194 #define I2C_MUX_CH_DEFAULT 0x0
195 #define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \
196 {0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \
197 {1, {I2C_NULL_HOP} }, \
203 #ifdef CONFIG_TSEC_ENET
204 #define CONFIG_ETHPRIME "ethernet@2d90000"
207 #define CONFIG_LAYERSCAPE_NS_ACCESS
208 #define CONFIG_SMP_PEN_ADDR 0x01ee0200
209 #define COUNTER_FREQUENCY 12500000
211 #define CONFIG_HWCONFIG
212 #define HWCONFIG_BUFFER_SIZE 256
213 #define CONFIG_FSL_DEVICE_DISABLE
216 * Miscellaneous configurable options
219 #define CONFIG_SYS_LOAD_ADDR 0x82000000
221 #define CONFIG_LS102XA_STREAM_ID
223 #define CONFIG_SYS_INIT_SP_OFFSET \
224 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
225 #define CONFIG_SYS_INIT_SP_ADDR \
226 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
228 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
229 #define CONFIG_SYS_MONITOR_LEN 0x100000 /* 1Mbyte */
230 #define CONFIG_SYS_QE_FW_ADDR 0x60020000
232 #define CONFIG_SYS_BOOTCOUNT_BE
238 #define CONFIG_ENV_TOTAL_SIZE 0x40000
239 #define ENV_DEL_ADDR CONFIG_ENV_ADDR_REDUND /* direct for newenv */
241 #ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */
242 #define CONFIG_KM_DEF_ENV
245 #ifndef CONFIG_KM_DEF_BOOT_ARGS_CPU
246 #define CONFIG_KM_DEF_BOOT_ARGS_CPU ""
249 #define CONFIG_KM_DEF_ENV_CPU \
250 "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \
252 "cramfsload ${fdt_addr_r} " \
253 "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \
254 "u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0" \
255 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
256 " +${filesize} && " \
257 "erase " __stringify(CONFIG_SYS_MONITOR_BASE) \
258 " +${filesize} && " \
259 "cp.b ${load_addr_r} " \
260 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize} && " \
261 "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \
263 "update-nor=protect off " __stringify(CONFIG_SYS_FLASH_BASE) \
264 " +${filesize} && " \
265 "erase " __stringify(CONFIG_SYS_FLASH_BASE) \
266 " +${filesize} && " \
267 "cp.b ${load_addr_r} " \
268 __stringify(CONFIG_SYS_FLASH_BASE) " ${filesize} && " \
269 "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \
270 " +" __stringify(CONFIG_SYS_MONITOR_LEN)"\0" \
271 "set_fdthigh=true\0" \
275 #define CONFIG_KM_NEW_ENV \
276 "newenv=protect off " __stringify(ENV_DEL_ADDR) \
277 " +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && " \
278 "erase " __stringify(ENV_DEL_ADDR) \
279 " +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && " \
280 "protect on " __stringify(ENV_DEL_ADDR) \
281 " +" __stringify(CONFIG_ENV_TOTAL_SIZE) "\0"
283 #define CONFIG_EXTRA_ENV_SETTINGS \
286 "EEprom_ivm=pca9547:70:9\0" \
289 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
290 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Increase map for Linux */