2 * (C) Copyright 2003-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * High Level Configuration Options
32 #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
33 #define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
34 #define CONFIG_INKA4X0 1 /* INKA4x0 board */
36 #define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
38 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
39 #define BOOTFLAG_WARM 0x02 /* Software reboot */
41 #define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
42 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
43 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
47 * Serial console configuration
49 #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
50 #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
51 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
56 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP)
58 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
59 #include <cmd_confdefs.h>
61 #if (TEXT_BASE == 0xFFE00000) /* Boot low */
62 # define CFG_LOWBOOT 1
68 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
70 #define CONFIG_PREBOOT "echo;" \
71 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
74 #undef CONFIG_BOOTARGS
76 #define CONFIG_EXTRA_ENV_SETTINGS \
78 "nfsargs=setenv bootargs root=/dev/nfs rw " \
79 "nfsroot=$(serverip):$(rootpath)\0" \
80 "ramargs=setenv bootargs root=/dev/ram rw\0" \
81 "addip=setenv bootargs $(bootargs) " \
82 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
83 ":$(hostname):$(netdev):off panic=1\0" \
84 "flash_nfs=run nfsargs addip;" \
85 "bootm $(kernel_addr)\0" \
86 "flash_self=run ramargs addip;" \
87 "bootm $(kernel_addr) $(ramdisk_addr)\0" \
88 "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
89 "rootpath=/opt/eldk3.0_ppc/ppc_82xx\0" \
91 "serverip=192.168.1.1\0" \
92 "ipaddr=192.168.160.2\0" \
93 "ethaddr=00:00:1A:1B:CE:AF\0" \
94 "dk=tftp 100000 inka4x0/u-boot.dk;protect off all;erase ffe00000 ffe2ffff;cp.b 100000 ffe00000 $(filesize)\0" \
97 #define CONFIG_BOOTCOMMAND "run net_nfs"
100 * IPB Bus clocking configuration.
102 #define CFG_IPBSPEED_133 /* define for 133MHz speed */
105 * Flash configuration
107 #define CFG_FLASH_BASE 0xFFE00000
109 #define CFG_FLASH_SIZE 0x00200000 /* 2 MByte */
110 #define CFG_MAX_FLASH_SECT 35 /* max num of sects on one chip */
112 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x4000) /* second sector */
113 #define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks
115 #define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
116 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
119 * Environment settings
121 #define CFG_ENV_IS_IN_FLASH 1
122 #define CFG_ENV_SIZE 0x2000
123 #define CFG_ENV_SECT_SIZE 0x2000
124 #define CONFIG_ENV_OVERWRITE 1
129 #define CFG_MBAR 0xF0000000
130 #define CFG_SDRAM_BASE 0x00000000
131 #define CFG_DEFAULT_MBAR 0x80000000
133 #define CONFIG_MPC5200_DDR
135 /* Use ON-Chip SRAM until RAM will be available */
136 #define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
138 /* preserve space for the post_word at end of on-chip SRAM */
139 #define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
141 #define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE
145 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
146 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
147 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
149 #define CFG_MONITOR_BASE TEXT_BASE
150 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
151 # define CFG_RAMBOOT 1
154 #define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
155 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
156 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
159 * Ethernet configuration
161 #define CONFIG_MPC5xxx_FEC 1
163 * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
165 /* #define CONFIG_FEC_10MBIT 1 */
166 #define CONFIG_PHY_ADDR 0x00
171 * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1):
172 * Bit 0 (mask: 0x80000000): 1
173 * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
174 * 00 -> No Alternatives, I2C1 is used for onboard EEPROM
175 * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1 do not use on TQM5200 with onboard
177 * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
178 * use PSC6_1 and PSC6_3 as GPIO: Bits 9:11 (mask: 0x07000000):
179 * 011 -> PSC6 could not be used as UART or CODEC. IrDA still possible.
180 * GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
183 #if defined (CONFIG_MINIFAP)
184 #define CFG_GPS_PORT_CONFIG 0x93000004
186 #define CFG_GPS_PORT_CONFIG 0x83000004
192 #define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
195 * Miscellaneous configurable options
197 #define CFG_LONGHELP /* undef to save memory */
198 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
199 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
200 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
202 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
204 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
205 #define CFG_MAXARGS 16 /* max number of command args */
206 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
208 /* Enable an alternate, more extensive memory test */
209 #define CFG_ALT_MEMTEST
211 #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
212 #define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
214 #define CFG_LOAD_ADDR 0x100000 /* default load address */
216 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
219 * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
220 * which is normally part of the default commands (CFV_CMD_DFL)
225 * Various low-level settings
227 #if defined(CONFIG_MPC5200)
228 #define CFG_HID0_INIT HID0_ICE | HID0_ICFI
229 #define CFG_HID0_FINAL HID0_ICE
231 #define CFG_HID0_INIT 0
232 #define CFG_HID0_FINAL 0
235 #define CFG_BOOTCS_START CFG_FLASH_BASE
236 #define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
237 #define CFG_BOOTCS_CFG 0x00087800 /* for pci_clk = 66 MHz */
238 #define CFG_CS0_START CFG_FLASH_BASE
239 #define CFG_CS0_SIZE CFG_FLASH_SIZE
241 #define CFG_CS_BURST 0x00000000
242 #define CFG_CS_DEADCYCLE 0x33333333
244 #endif /* __CONFIG_H */