2 * Copyright (C) 2011 Andes Technology Corporation
3 * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
4 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
6 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch-ae3xx/ae3xx.h>
15 * CPU and Board Configuration Options
17 #define CONFIG_USE_INTERRUPT
19 #define CONFIG_SKIP_LOWLEVEL_INIT
21 #define CONFIG_SKIP_TRUNOFF_WATCHDOG
23 #define CONFIG_ARCH_MAP_SYSMEM
25 #define CONFIG_BOOTP_SEND_HOSTNAME
26 #define CONFIG_BOOTP_SERVERIP
28 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
29 #ifdef CONFIG_OF_CONTROL
30 #undef CONFIG_OF_SEPARATE
31 #define CONFIG_OF_EMBED
38 #define CONFIG_SYS_CLK_FREQ 39062500
39 #define VERSION_CLOCK CONFIG_SYS_CLK_FREQ
42 * Use Externel CLOCK or PCLK
44 #undef CONFIG_FTRTC010_EXTCLK
46 #ifndef CONFIG_FTRTC010_EXTCLK
47 #define CONFIG_FTRTC010_PCLK
50 #ifdef CONFIG_FTRTC010_EXTCLK
51 #define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */
53 #define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */
56 #define TIMER_LOAD_VAL 0xffffffff
61 #define CONFIG_RTC_FTRTC010
64 * Real Time Clock Divider
65 * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ)
67 #define OSC_5MHZ (5*1000000)
68 #define OSC_CLK (4*OSC_5MHZ)
69 #define RTC_DIV_COUNT (0.5) /* Why?? */
72 * Serial console configuration
75 /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
76 #define CONFIG_SYS_NS16550_SERIAL
77 #define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE
78 #ifndef CONFIG_DM_SERIAL
79 #define CONFIG_SYS_NS16550_REG_SIZE -4
81 #define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */
86 #define CONFIG_FTSDC010_NUMBER 1
87 #define CONFIG_FTSDC010_SDIO
90 * Miscellaneous configurable options
94 * Size of malloc() pool
96 /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
97 #define CONFIG_SYS_MALLOC_LEN (512 << 10)
100 * Physical Memory Map
102 #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
104 #define PHYS_SDRAM_1 \
105 (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */
107 #define CONFIG_NR_DRAM_BANKS 2 /* we have 2 bank of DRAM */
109 #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */
110 #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */
112 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0
114 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
115 GENERATED_GBL_DATA_SIZE)
118 * Load address and memory test area should agree with
119 * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself.
121 #define CONFIG_SYS_LOAD_ADDR 0x300000
123 /* memtest works on 63 MB in DRAM */
124 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0
125 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000)
128 * Static memory controller configuration
130 #define CONFIG_FTSMC020
132 #ifdef CONFIG_FTSMC020
133 #include <faraday/ftsmc020.h>
135 #define CONFIG_SYS_FTSMC020_CONFIGS { \
136 { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \
137 { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \
140 #ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */
141 #define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \
142 FTSMC020_BANK_SIZE_32M | \
143 FTSMC020_BANK_MBW_32)
145 #define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \
146 FTSMC020_TPR_AST(1) | \
147 FTSMC020_TPR_CTW(1) | \
148 FTSMC020_TPR_ATI(1) | \
149 FTSMC020_TPR_AT2(1) | \
150 FTSMC020_TPR_WTC(1) | \
151 FTSMC020_TPR_AHT(1) | \
152 FTSMC020_TPR_TRNA(1))
156 * FLASH on ADP_AG101P is connected to BANK0
157 * Just disalbe the other BANK to avoid detection error.
159 #define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \
160 FTSMC020_BANK_BASE(PHYS_FLASH_1) | \
161 FTSMC020_BANK_SIZE_32M | \
162 FTSMC020_BANK_MBW_32)
164 #define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \
165 FTSMC020_TPR_CTW(3) | \
166 FTSMC020_TPR_ATI(0xf) | \
167 FTSMC020_TPR_AT2(3) | \
168 FTSMC020_TPR_WTC(3) | \
169 FTSMC020_TPR_AHT(3) | \
170 FTSMC020_TPR_TRNA(0xf))
172 #define FTSMC020_BANK1_CONFIG (0x00)
173 #define FTSMC020_BANK1_TIMING (0x00)
174 #endif /* CONFIG_FTSMC020 */
177 * FLASH and environment organization
179 /* use CFI framework */
180 #define CONFIG_SYS_FLASH_CFI
181 #define CONFIG_FLASH_CFI_DRIVER
183 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
184 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
185 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL
188 #ifdef CONFIG_CFI_FLASH
189 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
192 /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
193 #define PHYS_FLASH_1 0x88000000 /* BANK 0 */
194 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
195 #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, }
196 #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
198 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */
199 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */
201 /* max number of memory banks */
203 * There are 4 banks supported for this Controller,
204 * but we have only 1 bank connected to flash on board
206 #ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT
207 #define CONFIG_SYS_MAX_FLASH_BANKS 1
209 #define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
211 /* max number of sectors on one chip */
212 #define CONFIG_FLASH_SECTOR_SIZE (0x10000*2)
213 #define CONFIG_SYS_MAX_FLASH_SECT 512
216 #define CONFIG_ENV_SPI_BUS 0
217 #define CONFIG_ENV_SPI_CS 0
218 #define CONFIG_ENV_SPI_MAX_HZ 50000000
219 #define CONFIG_ENV_SPI_MODE 0
220 #define CONFIG_ENV_SECT_SIZE 0x1000
221 #define CONFIG_ENV_OFFSET 0x140000
222 #define CONFIG_ENV_SIZE 8192
223 #define CONFIG_ENV_OVERWRITE
227 #define CONFIG_SF_DEFAULT_BUS 0
228 #define CONFIG_SF_DEFAULT_CS 0
229 #define CONFIG_SF_DEFAULT_SPEED 1000000
230 #define CONFIG_SF_DEFAULT_MODE 0
233 * For booting Linux, the board info and command line data
234 * have to be in the first 16 MB of memory, since this is
235 * the maximum mapped by the Linux kernel during initialization.
238 /* Initial Memory map for Linux*/
239 #define CONFIG_SYS_BOOTMAPSZ (64 << 20)
240 /* Increase max gunzip size */
241 #define CONFIG_SYS_BOOTM_LEN (64 << 20)
243 #endif /* __CONFIG_H */