2 * (C) Copyright 2000-2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
32 * High Level Configuration Options
36 #define CONFIG_MPC866 1 /* This is a MPC866 CPU */
37 #define CONFIG_TQM866M 1 /* ...on a TQM8xxM module */
39 #define CFG_866_OSCCLK 10000000 /* 10 MHz - PLL input clock */
40 #define CFG_866_CPUCLK_MIN 40000000 /* 40 MHz - CPU minimum clock */
41 #define CFG_866_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */
42 #define CFG_866_CPUCLK_DEFAULT 100000000 /* 100 MHz - CPU default clock */
43 /* (it will be used if there is no */
44 /* 'cpuclk' variable with valid value) */
46 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
47 #undef CONFIG_8xx_CONS_SMC2
48 #undef CONFIG_8xx_CONS_NONE
50 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
52 #define CONFIG_BOOTCOUNT_LIMIT
54 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
56 #define CONFIG_BOARD_TYPES 1 /* support board types */
58 #define CONFIG_PREBOOT "echo;" \
59 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
62 #undef CONFIG_BOOTARGS
64 #define CONFIG_EXTRA_ENV_SETTINGS \
66 "nfsargs=setenv bootargs root=/dev/nfs rw " \
67 "nfsroot=$(serverip):$(rootpath)\0" \
68 "ramargs=setenv bootargs root=/dev/ram rw\0" \
69 "addip=setenv bootargs $(bootargs) " \
70 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
71 ":$(hostname):$(netdev):off panic=1\0" \
72 "flash_nfs=run nfsargs addip;" \
73 "bootm $(kernel_addr)\0" \
74 "flash_self=run ramargs addip;" \
75 "bootm $(kernel_addr) $(ramdisk_addr)\0" \
76 "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
77 "rootpath=/opt/eldk/ppc_8xx\0" \
78 "bootfile=/tftpboot/TQM855M/uImage\0" \
79 "kernel_addr=40080000\0" \
80 "ramdisk_addr=40180000\0" \
82 #define CONFIG_BOOTCOMMAND "run flash_self"
84 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
85 #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
87 #undef CONFIG_WATCHDOG /* watchdog disabled */
89 #define CONFIG_STATUS_LED 1 /* Status LED enabled */
91 #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
93 /* enable I2C and select the hardware/software driver */
94 #undef CONFIG_HARD_I2C /* I2C with hardware support */
95 #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
97 #define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */
98 #define CFG_I2C_SLAVE 0xFE
100 #ifdef CONFIG_SOFT_I2C
102 * Software (bit-bang) I2C driver configuration
104 #define PB_SCL 0x00000020 /* PB 26 */
105 #define PB_SDA 0x00000010 /* PB 27 */
107 #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
108 #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
109 #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
110 #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
111 #define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
112 else immr->im_cpm.cp_pbdat &= ~PB_SDA
113 #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
114 else immr->im_cpm.cp_pbdat &= ~PB_SCL
115 #define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
116 #endif /* CONFIG_SOFT_I2C */
118 #define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C256 */
119 #define CFG_I2C_EEPROM_ADDR_LEN 2 /* two byte address */
120 #define CFG_EEPROM_PAGE_WRITE_BITS 4
121 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
123 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
125 #define CONFIG_MAC_PARTITION
126 #define CONFIG_DOS_PARTITION
128 #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
130 #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
138 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
139 #include <cmd_confdefs.h>
142 * Miscellaneous configurable options
144 #define CFG_LONGHELP /* undef to save memory */
145 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
148 #define CFG_HUSH_PARSER 1 /* use "hush" command parser */
150 #ifdef CFG_HUSH_PARSER
151 #define CFG_PROMPT_HUSH_PS2 "> "
154 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
155 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
157 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
159 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
160 #define CFG_MAXARGS 16 /* max number of command args */
161 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
163 #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
164 #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
166 #define CFG_LOAD_ADDR 0x100000 /* default load address */
168 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
170 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
173 * Low Level Configuration Settings
174 * (address mappings, register initial values, etc.)
175 * You should know what you are doing if you make changes here.
177 /*-----------------------------------------------------------------------
178 * Internal Memory Mapped Register
180 #define CFG_IMMR 0xFFF00000
182 /*-----------------------------------------------------------------------
183 * Definitions for initial stack pointer and data area (in DPRAM)
185 #define CFG_INIT_RAM_ADDR CFG_IMMR
186 #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
187 #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
188 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
189 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
191 /*-----------------------------------------------------------------------
192 * Start addresses for the final memory configuration
193 * (Set up by the startup code)
194 * Please note that CFG_SDRAM_BASE _must_ start at 0
196 #define CFG_SDRAM_BASE 0x00000000
197 #define CFG_FLASH_BASE 0x40000000
198 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
199 #define CFG_MONITOR_BASE CFG_FLASH_BASE
200 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
203 * For booting Linux, the board info and command line data
204 * have to be in the first 8 MB of memory, since this is
205 * the maximum mapped by the Linux kernel during initialization.
207 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
209 /*-----------------------------------------------------------------------
212 #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
213 #define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
215 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
216 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
218 #define CFG_ENV_IS_IN_FLASH 1
219 #define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
220 #define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */
221 #define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
223 /* Address and size of Redundant Environment Sector */
224 #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
225 #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
227 /*-----------------------------------------------------------------------
228 * Hardware Information Block
230 #define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
231 #define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
232 #define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
234 /*-----------------------------------------------------------------------
235 * Cache Configuration
237 #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
238 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
239 #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
242 /*-----------------------------------------------------------------------
243 * SYPCR - System Protection Control 11-9
244 * SYPCR can only be written once after reset!
245 *-----------------------------------------------------------------------
246 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
248 #if defined(CONFIG_WATCHDOG)
249 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
250 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
252 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
255 /*-----------------------------------------------------------------------
256 * SIUMCR - SIU Module Configuration 11-6
257 *-----------------------------------------------------------------------
258 * PCMCIA config., multi-function pin tri-state
260 #ifndef CONFIG_CAN_DRIVER
261 #define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
262 #else /* we must activate GPL5 in the SIUMCR for CAN */
263 #define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
264 #endif /* CONFIG_CAN_DRIVER */
266 /*-----------------------------------------------------------------------
267 * TBSCR - Time Base Status and Control 11-26
268 *-----------------------------------------------------------------------
269 * Clear Reference Interrupt Status, Timebase freezing enabled
271 #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
273 /*-----------------------------------------------------------------------
274 * RTCSC - Real-Time Clock Status and Control Register 11-27
275 *-----------------------------------------------------------------------
277 #define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
279 /*-----------------------------------------------------------------------
280 * PISCR - Periodic Interrupt Status and Control 11-31
281 *-----------------------------------------------------------------------
282 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
284 #define CFG_PISCR (PISCR_PS | PISCR_PITF)
286 /*-----------------------------------------------------------------------
287 * SCCR - System Clock and reset Control Register 15-27
288 *-----------------------------------------------------------------------
289 * Set clock output, timebase and RTC source and divider,
290 * power management and some other internal clocks
292 #define SCCR_MASK SCCR_EBDF11
293 #define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
294 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
297 /*-----------------------------------------------------------------------
299 *-----------------------------------------------------------------------
302 #define CFG_PCMCIA_MEM_ADDR (0xE0000000)
303 #define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
304 #define CFG_PCMCIA_DMA_ADDR (0xE4000000)
305 #define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
306 #define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
307 #define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
308 #define CFG_PCMCIA_IO_ADDR (0xEC000000)
309 #define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
311 /*-----------------------------------------------------------------------
312 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
313 *-----------------------------------------------------------------------
316 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
318 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
319 #undef CONFIG_IDE_LED /* LED for ide not supported */
320 #undef CONFIG_IDE_RESET /* reset for ide not supported */
322 #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
323 #define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
325 #define CFG_ATA_IDE0_OFFSET 0x0000
327 #define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
329 /* Offset for data I/O */
330 #define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
332 /* Offset for normal register accesses */
333 #define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
335 /* Offset for alternate registers */
336 #define CFG_ATA_ALT_OFFSET 0x0100
338 /*-----------------------------------------------------------------------
340 *-----------------------------------------------------------------------
346 * Init Memory Controller:
348 * BR0/1 and OR0/1 (FLASH)
351 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
352 #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
354 /* used to re-map FLASH both when starting from SRAM or FLASH:
355 * restrict access enough to keep SRAM working (if any)
356 * but not too much to meddle with FLASH accesses
358 #define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
359 #define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
362 * FLASH timing: Default value of OR0 after reset
364 #define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \
365 OR_SCY_15_CLK | OR_TRLX)
367 #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
368 #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
369 #define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
371 #define CFG_OR1_REMAP CFG_OR0_REMAP
372 #define CFG_OR1_PRELIM CFG_OR0_PRELIM
373 #define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
376 * BR2/3 and OR2/3 (SDRAM)
379 #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
380 #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
381 #define SDRAM_MAX_SIZE (256 << 20) /* max 256 MB per bank */
383 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
384 #define CFG_OR_TIMING_SDRAM 0x00000A00
386 #define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
387 #define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
389 #ifndef CONFIG_CAN_DRIVER
390 #define CFG_OR3_PRELIM CFG_OR2_PRELIM
391 #define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
392 #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
393 #define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
394 #define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
395 #define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI)
396 #define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \
397 BR_PS_8 | BR_MS_UPMB | BR_V )
398 #endif /* CONFIG_CAN_DRIVER */
402 * 4096 Rows from SDRAM example configuration
403 * 1000 factor s -> ms
404 * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
405 * 4 Number of refresh cycles per period
406 * 64 Refresh cycle in ms per number of rows
408 #define CFG_866_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
411 * Memory Periodic Timer Prescaler
412 * Periodic timer for refresh, start with refresh rate for 40 MHz clock
413 * (CFG_866_CPUCLK_MIN / CFG_866_PTA_PER_CLK)
415 #define CFG_MAMR_PTA 39
418 * For 16 MBit, refresh rates could be 31.3 us
419 * (= 64 ms / 2K = 125 / quad bursts).
420 * For a simpler initialization, 15.6 us is used instead.
422 * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
423 * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
425 #define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
426 #define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
428 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
429 #define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
430 #define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
433 * MAMR settings for SDRAM
437 #define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
438 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
439 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
441 #define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
442 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
443 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
444 /* 10 column SDRAM */
445 #define CFG_MAMR_10COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
446 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \
447 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
450 * Internal Definitions
454 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
455 #define BOOTFLAG_WARM 0x02 /* Software reboot */
457 #define CONFIG_SCC1_ENET
458 #define CONFIG_FEC_ENET
459 #define CONFIG_ETHPRIME "SCC ETHERNET"
461 #endif /* __CONFIG_H */