1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Configuation settings for the Motorola MC5282EVB board.
5 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
9 * board/config.h - configuration options, board specific
12 #ifndef _CONFIG_M5282EVB_H
13 #define _CONFIG_M5282EVB_H
16 * High Level Configuration Options
20 #define CFG_SYS_UART_PORT (0)
22 #undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
24 /* Configuration for environment
25 * Environment is embedded in u-boot in the second sector of the flash
28 #define LDS_BOARD_TEXT \
29 . = DEFINED(env_offset) ? env_offset : .; \
30 env/embedded.o(.text*);
33 # define CONFIG_IPADDR 192.162.1.2
34 # define CONFIG_NETMASK 255.255.255.0
35 # define CONFIG_SERVERIP 192.162.1.1
36 # define CONFIG_GATEWAYIP 192.162.1.1
37 #endif /* CONFIG_MCFFEC */
39 #define CONFIG_HOSTNAME "M5282EVB"
40 #define CONFIG_EXTRA_ENV_SETTINGS \
43 "u-boot=u-boot.bin\0" \
44 "load=tftp ${loadaddr) ${u-boot}\0" \
45 "upd=run load; run prog\0" \
46 "prog=prot off ffe00000 ffe3ffff;" \
47 "era ffe00000 ffe3ffff;" \
48 "cp.b ${loadaddr} ffe00000 ${filesize};"\
52 #define CFG_SYS_CLK 64000000
54 /* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */
56 #define CFG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */
57 #define CFG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */
60 * Low Level Configuration Settings
61 * (address mappings, register initial values, etc.)
62 * You should know what you are doing if you make changes here.
64 #define CFG_SYS_MBAR 0x40000000
66 /*-----------------------------------------------------------------------
67 * Definitions for initial stack pointer and data area (in DPRAM)
69 #define CFG_SYS_INIT_RAM_ADDR 0x20000000
70 #define CFG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
72 /*-----------------------------------------------------------------------
73 * Start addresses for the final memory configuration
74 * (Set up by the startup code)
75 * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
77 #define CFG_SYS_SDRAM_BASE 0x00000000
78 #define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
79 #define CFG_SYS_FLASH_BASE CFG_SYS_CS0_BASE
80 #define CFG_SYS_INT_FLASH_BASE 0xf0000000
81 #define CFG_SYS_INT_FLASH_ENABLE 0x21
84 * For booting Linux, the board info and command line data
85 * have to be in the first 8 MB of memory, since this is
86 * the maximum mapped by the Linux kernel during initialization ??
88 #define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
90 /*-----------------------------------------------------------------------
93 #ifdef CONFIG_SYS_FLASH_CFI
95 # define CFG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
96 # define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE }
99 /*-----------------------------------------------------------------------
100 * Cache Configuration
103 #define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
104 CFG_SYS_INIT_RAM_SIZE - 8)
105 #define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
106 CFG_SYS_INIT_RAM_SIZE - 4)
107 #define CFG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM)
108 #define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
109 CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
110 CF_ACR_EN | CF_ACR_SM_ALL)
111 #define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \
112 CF_CACR_CEIB | CF_CACR_DBWE | \
115 /*-----------------------------------------------------------------------
116 * Memory bank definitions
118 #define CFG_SYS_CS0_BASE 0xFFE00000
119 #define CFG_SYS_CS0_CTRL 0x00001980
120 #define CFG_SYS_CS0_MASK 0x001F0001
122 /*-----------------------------------------------------------------------
125 #define CFG_SYS_PACNT 0x0000000 /* Port A D[31:24] */
126 #define CFG_SYS_PADDR 0x0000000
127 #define CFG_SYS_PADAT 0x0000000
129 #define CFG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */
130 #define CFG_SYS_PBDDR 0x0000000
131 #define CFG_SYS_PBDAT 0x0000000
133 #define CFG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */
135 #define CFG_SYS_PEHLPAR 0xC0
136 #define CFG_SYS_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */
137 #define CFG_SYS_DDRUA 0x05
138 #define CFG_SYS_PJPAR 0xFF
140 #endif /* _CONFIG_M5282EVB_H */