include/asm-x86/system_64.h

   1 #ifndef __ASM_SYSTEM_H
   2 #define __ASM_SYSTEM_H
   3
   4 #include <linux/kernel.h>
   5 #include <asm/segment.h>
   6 #include <asm/cmpxchg.h>
   7
   8 #ifdef __KERNEL__
   9
  10 /* entries in ARCH_DLINFO: */
  11 #ifdef CONFIG_IA32_EMULATION
  12 # define AT_VECTOR_SIZE_ARCH 2
  13 #else
  14 # define AT_VECTOR_SIZE_ARCH 1
  15 #endif
  16
  17 #define __SAVE(reg,offset) "movq %%" #reg ",(14-" #offset ")*8(%%rsp)\n\t"
  18 #define __RESTORE(reg,offset) "movq (14-" #offset ")*8(%%rsp),%%" #reg "\n\t"
  19
  20 /* frame pointer must be last for get_wchan */
  21 #define SAVE_CONTEXT    "pushf ; pushq %%rbp ; movq %%rsi,%%rbp\n\t"
  22 #define RESTORE_CONTEXT "movq %%rbp,%%rsi ; popq %%rbp ; popf\t"
  23
  24 #define __EXTRA_CLOBBER  \
  25         ,"rcx","rbx","rdx","r8","r9","r10","r11","r12","r13","r14","r15"
  26
  27 /* Save restore flags to clear handle leaking NT */
  28 #define switch_to(prev,next,last) \
  29         asm volatile(SAVE_CONTEXT                                                   \
  30                      "movq %%rsp,%P[threadrsp](%[prev])\n\t" /* save RSP */       \
  31                      "movq %P[threadrsp](%[next]),%%rsp\n\t" /* restore RSP */    \
  32                      "call __switch_to\n\t"                                       \
  33                      ".globl thread_return\n"                                   \
  34                      "thread_return:\n\t"                                           \
  35                      "movq %%gs:%P[pda_pcurrent],%%rsi\n\t"                       \
  36                      "movq %P[thread_info](%%rsi),%%r8\n\t"                       \
  37                      LOCK_PREFIX "btr  %[tif_fork],%P[ti_flags](%%r8)\n\t"        \
  38                      "movq %%rax,%%rdi\n\t"                                       \
  39                      "jc   ret_from_fork\n\t"                                     \
  40                      RESTORE_CONTEXT                                                \
  41                      : "=a" (last)                                                \
  42                      : [next] "S" (next), [prev] "D" (prev),                      \
  43                        [threadrsp] "i" (offsetof(struct task_struct, thread.sp)), \
  44                        [ti_flags] "i" (offsetof(struct thread_info, flags)),\
  45                        [tif_fork] "i" (TIF_FORK),                         \
  46                        [thread_info] "i" (offsetof(struct task_struct, stack)), \
  47                        [pda_pcurrent] "i" (offsetof(struct x8664_pda, pcurrent))   \
  48                      : "memory", "cc" __EXTRA_CLOBBER)
  49
  50 extern void load_gs_index(unsigned);
  51
  52 /*
  53  * Clear and set 'TS' bit respectively
  54  */
  55 #define clts() __asm__ __volatile__ ("clts")
  56
  57 static inline unsigned long read_cr0(void)
  58 {
  59         unsigned long cr0;
  60         asm volatile("movq %%cr0,%0" : "=r" (cr0));
  61         return cr0;
  62 }
  63
  64 static inline void write_cr0(unsigned long val)
  65 {
  66         asm volatile("movq %0,%%cr0" :: "r" (val));
  67 }
  68
  69 static inline unsigned long read_cr2(void)
  70 {
  71         unsigned long cr2;
  72         asm volatile("movq %%cr2,%0" : "=r" (cr2));
  73         return cr2;
  74 }
  75
  76 static inline void write_cr2(unsigned long val)
  77 {
  78         asm volatile("movq %0,%%cr2" :: "r" (val));
  79 }
  80
  81 static inline unsigned long read_cr3(void)
  82 {
  83         unsigned long cr3;
  84         asm volatile("movq %%cr3,%0" : "=r" (cr3));
  85         return cr3;
  86 }
  87
  88 static inline void write_cr3(unsigned long val)
  89 {
  90         asm volatile("movq %0,%%cr3" :: "r" (val) : "memory");
  91 }
  92
  93 static inline unsigned long read_cr4(void)
  94 {
  95         unsigned long cr4;
  96         asm volatile("movq %%cr4,%0" : "=r" (cr4));
  97         return cr4;
  98 }
  99
 100 static inline void write_cr4(unsigned long val)
 101 {
 102         asm volatile("movq %0,%%cr4" :: "r" (val) : "memory");
 103 }
 104
 105 static inline unsigned long read_cr8(void)
 106 {
 107         unsigned long cr8;
 108         asm volatile("movq %%cr8,%0" : "=r" (cr8));
 109         return cr8;
 110 }
 111
 112 static inline void write_cr8(unsigned long val)
 113 {
 114         asm volatile("movq %0,%%cr8" :: "r" (val) : "memory");
 115 }
 116
 117 #define stts() write_cr0(8 | read_cr0())
 118
 119 #define wbinvd() \
 120         __asm__ __volatile__ ("wbinvd": : :"memory")
 121
 122 #endif  /* __KERNEL__ */
 123
 124 #ifdef CONFIG_SMP
 125 #define smp_mb()        mb()
 126 #define smp_rmb()       barrier()
 127 #define smp_wmb()       barrier()
 128 #define smp_read_barrier_depends()      do {} while(0)
 129 #else
 130 #define smp_mb()        barrier()
 131 #define smp_rmb()       barrier()
 132 #define smp_wmb()       barrier()
 133 #define smp_read_barrier_depends()      do {} while(0)
 134 #endif
 135
 136
 137 /*
 138  * Force strict CPU ordering.
 139  * And yes, this is required on UP too when we're talking
 140  * to devices.
 141  */
 142 #define mb()    asm volatile("mfence":::"memory")
 143 #define rmb()   asm volatile("lfence":::"memory")
 144 #define wmb()   asm volatile("sfence" ::: "memory")
 145
 146 #define read_barrier_depends()  do {} while(0)
 147 #define set_mb(var, value) do { (void) xchg(&var, value); } while (0)
 148
 149 #define warn_if_not_ulong(x) do { unsigned long foo; (void) (&(x) == &foo); } while (0)
 150
 151 #include <linux/irqflags.h>
 152
 153 #endif