6 * linux/include/asm-sh/irq.h
8 * Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
9 * Copyright (C) 2000 Kazumoto Kojima
10 * Copyright (C) 2003 Paul Mundt
14 #include <asm/machvec.h>
15 #include <asm/ptrace.h> /* for pt_regs */
17 #if defined(CONFIG_SH_HP6XX) || \
18 defined(CONFIG_SH_RTS7751R2D) || \
19 defined(CONFIG_SH_HS7751RVOIP) || \
20 defined(CONFIG_SH_HS7751RVOIP) || \
21 defined(CONFIG_SH_SH03) || \
22 defined(CONFIG_SH_R7780RP) || \
23 defined(CONFIG_SH_LANDISK)
24 #include <asm/mach/ide.h>
27 #ifndef CONFIG_CPU_SUBTYPE_SH7780
29 #define INTC_DMAC0_MSK 0
31 #if defined(CONFIG_CPU_SH3)
32 #define INTC_IPRA 0xfffffee2UL
33 #define INTC_IPRB 0xfffffee4UL
34 #elif defined(CONFIG_CPU_SH4)
35 #define INTC_IPRA 0xffd00004UL
36 #define INTC_IPRB 0xffd00008UL
37 #define INTC_IPRC 0xffd0000cUL
38 #define INTC_IPRD 0xffd00010UL
43 # define IRQ_CFCARD 14
46 # define IRQ_PCMCIA 15
51 #define TIMER_IPR_ADDR INTC_IPRA
52 #define TIMER_IPR_POS 3
53 #define TIMER_PRIORITY 2
56 #define TIMER1_IPR_ADDR INTC_IPRA
57 #define TIMER1_IPR_POS 2
58 #define TIMER1_PRIORITY 4
61 #define RTC_IPR_ADDR INTC_IPRA
63 #define RTC_PRIORITY TIMER_PRIORITY
65 #if defined(CONFIG_CPU_SH3)
70 #define DMA_IPR_ADDR INTC_IPRE
72 #define DMA_PRIORITY 7
73 #if defined(CONFIG_CPU_SUBTYPE_SH7300)
76 #define TIMER2_IPR_ADDR INTC_IPRA
77 #define TIMER2_IPR_POS 1
78 #define TIMER2_PRIORITY 2
82 #define WDT_IPR_ADDR INTC_IPRB
84 #define WDT_PRIORITY 2
86 /* SIM (SIM Card Module) */
87 #define SIM_ERI_IRQ 23
88 #define SIM_RXI_IRQ 24
89 #define SIM_TXI_IRQ 25
90 #define SIM_TEND_IRQ 26
91 #define SIM_IPR_ADDR INTC_IPRB
93 #define SIM_PRIORITY 2
97 #define VIO_IPR_ADDR INTC_IPRE
99 #define VIO_PRIORITY 2
101 /* MFI (Multi Functional Interface) */
103 #define MFI_IPR_ADDR INTC_IPRE
104 #define MFI_IPR_POS 1
105 #define MFI_PRIORITY 2
107 /* VPU (Video Processing Unit) */
109 #define VPU_IPR_ADDR INTC_IPRE
110 #define VPU_IPR_POS 0
111 #define VPU_PRIORITY 2
113 /* KEY (Key Scan Interface) */
115 #define KEY_IPR_ADDR INTC_IPRF
116 #define KEY_IPR_POS 3
117 #define KEY_PRIORITY 2
119 /* CMT (Compare Match Timer) */
121 #define CMT_IPR_ADDR INTC_IPRF
122 #define CMT_IPR_POS 0
123 #define CMT_PRIORITY 2
130 #define DMA1_IPR_ADDR INTC_IPRE
131 #define DMA1_IPR_POS 3
132 #define DMA1_PRIORITY 7
137 #define DMA2_IPR_ADDR INTC_IPRF
138 #define DMA2_IPR_POS 2
139 #define DMA2_PRIORITY 7
143 #define SIOF0_IPR_ADDR INTC_IPRH
144 #define SIOF0_IPR_POS 3
145 #define SIOF0_PRIORITY 3
147 /* FLCTL (Flash Memory Controller) */
149 #define FLTEND_IRQ 93
150 #define FLTRQ0_IRQ 94
151 #define FLTRQ1_IRQ 95
152 #define FLCTL_IPR_ADDR INTC_IPRH
153 #define FLCTL_IPR_POS 1
154 #define FLCTL_PRIORITY 3
156 /* IIC (IIC Bus Interface) */
157 #define IIC_ALI_IRQ 96
158 #define IIC_TACKI_IRQ 97
159 #define IIC_WAITI_IRQ 98
160 #define IIC_DTEI_IRQ 99
161 #define IIC_IPR_ADDR INTC_IPRH
162 #define IIC_IPR_POS 0
163 #define IIC_PRIORITY 3
167 #define SIO0_IPR_ADDR INTC_IPRI
168 #define SIO0_IPR_POS 3
169 #define SIO0_PRIORITY 3
171 /* SIU (Sound Interface Unit) */
173 #define SIU_IPR_ADDR INTC_IPRJ
174 #define SIU_IPR_POS 1
175 #define SIU_PRIORITY 3
178 #elif defined(CONFIG_CPU_SH4)
183 #define DMTE4_IRQ 44 /* 7751R only */
184 #define DMTE5_IRQ 45 /* 7751R only */
185 #define DMTE6_IRQ 46 /* 7751R only */
186 #define DMTE7_IRQ 47 /* 7751R only */
188 #define DMA_IPR_ADDR INTC_IPRC
189 #define DMA_IPR_POS 2
190 #define DMA_PRIORITY 7
193 #if defined (CONFIG_CPU_SUBTYPE_SH7707) || defined (CONFIG_CPU_SUBTYPE_SH7708) || \
194 defined (CONFIG_CPU_SUBTYPE_SH7709) || defined (CONFIG_CPU_SUBTYPE_SH7750) || \
195 defined (CONFIG_CPU_SUBTYPE_SH7751)
196 #define SCI_ERI_IRQ 23
197 #define SCI_RXI_IRQ 24
198 #define SCI_TXI_IRQ 25
199 #define SCI_IPR_ADDR INTC_IPRB
200 #define SCI_IPR_POS 1
201 #define SCI_PRIORITY 3
204 #if defined(CONFIG_CPU_SUBTYPE_SH7300)
206 #define SCIF0_IPR_ADDR INTC_IPRG
207 #define SCIF0_IPR_POS 3
208 #define SCIF0_PRIORITY 3
209 #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
210 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
211 defined(CONFIG_CPU_SUBTYPE_SH7709)
212 #define SCIF_ERI_IRQ 56
213 #define SCIF_RXI_IRQ 57
214 #define SCIF_BRI_IRQ 58
215 #define SCIF_TXI_IRQ 59
216 #define SCIF_IPR_ADDR INTC_IPRE
217 #define SCIF_IPR_POS 1
218 #define SCIF_PRIORITY 3
220 #define IRDA_ERI_IRQ 52
221 #define IRDA_RXI_IRQ 53
222 #define IRDA_BRI_IRQ 54
223 #define IRDA_TXI_IRQ 55
224 #define IRDA_IPR_ADDR INTC_IPRE
225 #define IRDA_IPR_POS 2
226 #define IRDA_PRIORITY 3
227 #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || \
228 defined(CONFIG_CPU_SUBTYPE_ST40STB1) || defined(CONFIG_CPU_SUBTYPE_SH4_202)
229 #define SCIF_ERI_IRQ 40
230 #define SCIF_RXI_IRQ 41
231 #define SCIF_BRI_IRQ 42
232 #define SCIF_TXI_IRQ 43
233 #define SCIF_IPR_ADDR INTC_IPRC
234 #define SCIF_IPR_POS 1
235 #define SCIF_PRIORITY 3
236 #if defined(CONFIG_CPU_SUBTYPE_ST40STB1)
237 #define SCIF1_ERI_IRQ 23
238 #define SCIF1_RXI_IRQ 24
239 #define SCIF1_BRI_IRQ 25
240 #define SCIF1_TXI_IRQ 26
241 #define SCIF1_IPR_ADDR INTC_IPRB
242 #define SCIF1_IPR_POS 1
243 #define SCIF1_PRIORITY 3
244 #endif /* ST40STB1 */
246 #endif /* 775x / SH4-202 / ST40STB1 */
249 /* NR_IRQS is made from three components:
250 * 1. ONCHIP_NR_IRQS - number of IRLS + on-chip peripherial modules
251 * 2. PINT_NR_IRQS - number of PINT interrupts
252 * 3. OFFCHIP_NR_IRQS - numbe of IRQs from off-chip peripherial modules
255 /* 1. ONCHIP_NR_IRQS */
256 #if defined(CONFIG_CPU_SUBTYPE_SH7604)
257 # define ONCHIP_NR_IRQS 24 // Actually 21
258 #elif defined(CONFIG_CPU_SUBTYPE_SH7707)
259 # define ONCHIP_NR_IRQS 64
260 # define PINT_NR_IRQS 16
261 #elif defined(CONFIG_CPU_SUBTYPE_SH7708)
262 # define ONCHIP_NR_IRQS 32
263 #elif defined(CONFIG_CPU_SUBTYPE_SH7709) || \
264 defined(CONFIG_CPU_SUBTYPE_SH7705)
265 # define ONCHIP_NR_IRQS 64 // Actually 61
266 # define PINT_NR_IRQS 16
267 #elif defined(CONFIG_CPU_SUBTYPE_SH7750)
268 # define ONCHIP_NR_IRQS 48 // Actually 44
269 #elif defined(CONFIG_CPU_SUBTYPE_SH7751)
270 # define ONCHIP_NR_IRQS 72
271 #elif defined(CONFIG_CPU_SUBTYPE_SH7760)
272 # define ONCHIP_NR_IRQS 112 /* XXX */
273 #elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
274 # define ONCHIP_NR_IRQS 72
275 #elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
276 # define ONCHIP_NR_IRQS 144
277 #elif defined(CONFIG_CPU_SUBTYPE_SH7300) || \
278 defined(CONFIG_CPU_SUBTYPE_SH73180)
279 # define ONCHIP_NR_IRQS 109
280 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
281 # define ONCHIP_NR_IRQS 111
282 #elif defined(CONFIG_SH_UNKNOWN) /* Most be last */
283 # define ONCHIP_NR_IRQS 144
286 /* 2. PINT_NR_IRQS */
287 #ifdef CONFIG_SH_UNKNOWN
288 # define PINT_NR_IRQS 16
290 # ifndef PINT_NR_IRQS
291 # define PINT_NR_IRQS 0
296 # define PINT_IRQ_BASE ONCHIP_NR_IRQS
299 /* 3. OFFCHIP_NR_IRQS */
300 #if defined(CONFIG_HD64461)
301 # define OFFCHIP_NR_IRQS 18
302 #elif defined (CONFIG_SH_BIGSUR) /* must be before CONFIG_HD64465 */
303 # define OFFCHIP_NR_IRQS 48
304 #elif defined(CONFIG_HD64465)
305 # define OFFCHIP_NR_IRQS 16
306 #elif defined (CONFIG_SH_EC3104)
307 # define OFFCHIP_NR_IRQS 16
308 #elif defined (CONFIG_SH_DREAMCAST)
309 # define OFFCHIP_NR_IRQS 96
310 #elif defined (CONFIG_SH_TITAN)
311 # define OFFCHIP_NR_IRQS 4
312 #elif defined(CONFIG_SH_R7780RP)
313 # define OFFCHIP_NR_IRQS 16
314 #elif defined(CONFIG_SH_UNKNOWN)
315 # define OFFCHIP_NR_IRQS 16 /* Must also be last */
317 # define OFFCHIP_NR_IRQS 0
320 #if OFFCHIP_NR_IRQS > 0
321 # define OFFCHIP_IRQ_BASE (ONCHIP_NR_IRQS + PINT_NR_IRQS)
325 #define NR_IRQS (ONCHIP_NR_IRQS + PINT_NR_IRQS + OFFCHIP_NR_IRQS)
327 extern void disable_irq(unsigned int);
328 extern void disable_irq_nosync(unsigned int);
329 extern void enable_irq(unsigned int);
332 * Simple Mask Register Support
334 extern void make_maskreg_irq(unsigned int irq);
335 extern unsigned short *irq_mask_register;
340 void init_IRQ_pint(void);
343 * Function for "on chip support modules".
345 extern void make_ipr_irq(unsigned int irq, unsigned int addr,
346 int pos, int priority);
347 extern void make_imask_irq(unsigned int irq);
349 #if defined(CONFIG_CPU_SUBTYPE_SH7300)
352 #define INTC_IPRA 0xA414FEE2UL
353 #define INTC_IPRB 0xA414FEE4UL
354 #define INTC_IPRC 0xA4140016UL
355 #define INTC_IPRD 0xA4140018UL
356 #define INTC_IPRE 0xA414001AUL
357 #define INTC_IPRF 0xA4080000UL
358 #define INTC_IPRG 0xA4080002UL
359 #define INTC_IPRH 0xA4080004UL
360 #define INTC_IPRI 0xA4080006UL
361 #define INTC_IPRJ 0xA4080008UL
363 #define INTC_IMR0 0xA4080040UL
364 #define INTC_IMR1 0xA4080042UL
365 #define INTC_IMR2 0xA4080044UL
366 #define INTC_IMR3 0xA4080046UL
367 #define INTC_IMR4 0xA4080048UL
368 #define INTC_IMR5 0xA408004AUL
369 #define INTC_IMR6 0xA408004CUL
370 #define INTC_IMR7 0xA408004EUL
371 #define INTC_IMR8 0xA4080050UL
372 #define INTC_IMR9 0xA4080052UL
373 #define INTC_IMR10 0xA4080054UL
375 #define INTC_IMCR0 0xA4080060UL
376 #define INTC_IMCR1 0xA4080062UL
377 #define INTC_IMCR2 0xA4080064UL
378 #define INTC_IMCR3 0xA4080066UL
379 #define INTC_IMCR4 0xA4080068UL
380 #define INTC_IMCR5 0xA408006AUL
381 #define INTC_IMCR6 0xA408006CUL
382 #define INTC_IMCR7 0xA408006EUL
383 #define INTC_IMCR8 0xA4080070UL
384 #define INTC_IMCR9 0xA4080072UL
385 #define INTC_IMCR10 0xA4080074UL
387 #define INTC_ICR0 0xA414FEE0UL
388 #define INTC_ICR1 0xA4140010UL
390 #define INTC_IRR0 0xA4140004UL
392 #define PORT_PACR 0xA4050100UL
393 #define PORT_PBCR 0xA4050102UL
394 #define PORT_PCCR 0xA4050104UL
395 #define PORT_PDCR 0xA4050106UL
396 #define PORT_PECR 0xA4050108UL
397 #define PORT_PFCR 0xA405010AUL
398 #define PORT_PGCR 0xA405010CUL
399 #define PORT_PHCR 0xA405010EUL
400 #define PORT_PJCR 0xA4050110UL
401 #define PORT_PKCR 0xA4050112UL
402 #define PORT_PLCR 0xA4050114UL
403 #define PORT_SCPCR 0xA4050116UL
404 #define PORT_PMCR 0xA4050118UL
405 #define PORT_PNCR 0xA405011AUL
406 #define PORT_PQCR 0xA405011CUL
408 #define PORT_PSELA 0xA4050140UL
409 #define PORT_PSELB 0xA4050142UL
410 #define PORT_PSELC 0xA4050144UL
412 #define PORT_HIZCRA 0xA4050146UL
413 #define PORT_HIZCRB 0xA4050148UL
414 #define PORT_DRVCR 0xA4050150UL
416 #define PORT_PADR 0xA4050120UL
417 #define PORT_PBDR 0xA4050122UL
418 #define PORT_PCDR 0xA4050124UL
419 #define PORT_PDDR 0xA4050126UL
420 #define PORT_PEDR 0xA4050128UL
421 #define PORT_PFDR 0xA405012AUL
422 #define PORT_PGDR 0xA405012CUL
423 #define PORT_PHDR 0xA405012EUL
424 #define PORT_PJDR 0xA4050130UL
425 #define PORT_PKDR 0xA4050132UL
426 #define PORT_PLDR 0xA4050134UL
427 #define PORT_SCPDR 0xA4050136UL
428 #define PORT_PMDR 0xA4050138UL
429 #define PORT_PNDR 0xA405013AUL
430 #define PORT_PQDR 0xA405013CUL
439 #define IRQ0_IPR_ADDR INTC_IPRC
440 #define IRQ1_IPR_ADDR INTC_IPRC
441 #define IRQ2_IPR_ADDR INTC_IPRC
442 #define IRQ3_IPR_ADDR INTC_IPRC
443 #define IRQ4_IPR_ADDR INTC_IPRD
444 #define IRQ5_IPR_ADDR INTC_IPRD
446 #define IRQ0_IPR_POS 0
447 #define IRQ1_IPR_POS 1
448 #define IRQ2_IPR_POS 2
449 #define IRQ3_IPR_POS 3
450 #define IRQ4_IPR_POS 0
451 #define IRQ5_IPR_POS 1
453 #define IRQ0_PRIORITY 1
454 #define IRQ1_PRIORITY 1
455 #define IRQ2_PRIORITY 1
456 #define IRQ3_PRIORITY 1
457 #define IRQ4_PRIORITY 1
458 #define IRQ5_PRIORITY 1
460 extern int ipr_irq_demux(int irq);
461 #define __irq_demux(irq) ipr_irq_demux(irq)
463 #elif defined(CONFIG_CPU_SUBTYPE_SH7604)
464 #define INTC_IPRA 0xfffffee2UL
465 #define INTC_IPRB 0xfffffe60UL
467 #define INTC_VCRA 0xfffffe62UL
468 #define INTC_VCRB 0xfffffe64UL
469 #define INTC_VCRC 0xfffffe66UL
470 #define INTC_VCRD 0xfffffe68UL
472 #define INTC_VCRWDT 0xfffffee4UL
473 #define INTC_VCRDIV 0xffffff0cUL
474 #define INTC_VCRDMA0 0xffffffa0UL
475 #define INTC_VCRDMA1 0xffffffa8UL
477 #define INTC_ICR 0xfffffee0UL
478 #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
479 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
480 defined(CONFIG_CPU_SUBTYPE_SH7709)
481 #define INTC_IRR0 0xa4000004UL
482 #define INTC_IRR1 0xa4000006UL
483 #define INTC_IRR2 0xa4000008UL
485 #define INTC_ICR0 0xfffffee0UL
486 #define INTC_ICR1 0xa4000010UL
487 #define INTC_ICR2 0xa4000012UL
488 #define INTC_INTER 0xa4000014UL
490 #define INTC_IPRC 0xa4000016UL
491 #define INTC_IPRD 0xa4000018UL
492 #define INTC_IPRE 0xa400001aUL
493 #if defined(CONFIG_CPU_SUBTYPE_SH7707)
494 #define INTC_IPRF 0xa400001cUL
495 #elif defined(CONFIG_CPU_SUBTYPE_SH7705)
496 #define INTC_IPRF 0xa4080000UL
497 #define INTC_IPRG 0xa4080002UL
498 #define INTC_IPRH 0xa4080004UL
501 #define PORT_PACR 0xa4000100UL
502 #define PORT_PBCR 0xa4000102UL
503 #define PORT_PCCR 0xa4000104UL
504 #define PORT_PFCR 0xa400010aUL
505 #define PORT_PADR 0xa4000120UL
506 #define PORT_PBDR 0xa4000122UL
507 #define PORT_PCDR 0xa4000124UL
508 #define PORT_PFDR 0xa400012aUL
517 #define IRQ0_IPR_ADDR INTC_IPRC
518 #define IRQ1_IPR_ADDR INTC_IPRC
519 #define IRQ2_IPR_ADDR INTC_IPRC
520 #define IRQ3_IPR_ADDR INTC_IPRC
521 #define IRQ4_IPR_ADDR INTC_IPRD
522 #define IRQ5_IPR_ADDR INTC_IPRD
524 #define IRQ0_IPR_POS 0
525 #define IRQ1_IPR_POS 1
526 #define IRQ2_IPR_POS 2
527 #define IRQ3_IPR_POS 3
528 #define IRQ4_IPR_POS 0
529 #define IRQ5_IPR_POS 1
531 #define IRQ0_PRIORITY 1
532 #define IRQ1_PRIORITY 1
533 #define IRQ2_PRIORITY 1
534 #define IRQ3_PRIORITY 1
535 #define IRQ4_PRIORITY 1
536 #define IRQ5_PRIORITY 1
541 #define PINT0_IPR_ADDR INTC_IPRD
542 #define PINT8_IPR_ADDR INTC_IPRD
544 #define PINT0_IPR_POS 3
545 #define PINT8_IPR_POS 2
546 #define PINT0_PRIORITY 2
547 #define PINT8_PRIORITY 2
549 extern int ipr_irq_demux(int irq);
550 #define __irq_demux(irq) ipr_irq_demux(irq)
551 #endif /* CONFIG_CPU_SUBTYPE_SH7707 || CONFIG_CPU_SUBTYPE_SH7709 */
553 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || \
554 defined(CONFIG_CPU_SUBTYPE_ST40STB1) || defined(CONFIG_CPU_SUBTYPE_SH4_202)
555 #define INTC_ICR 0xffd00000
556 #define INTC_ICR_NMIL (1<<15)
557 #define INTC_ICR_MAI (1<<14)
558 #define INTC_ICR_NMIB (1<<9)
559 #define INTC_ICR_NMIE (1<<8)
560 #define INTC_ICR_IRLM (1<<7)
563 #ifdef CONFIG_CPU_SUBTYPE_SH7780
564 #include <asm/irq-sh7780.h>
567 /* SH with INTC2-style interrupts */
568 #ifdef CONFIG_CPU_HAS_INTC2_IRQ
569 #if defined(CONFIG_CPU_SUBTYPE_ST40STB1)
570 #define INTC2_BASE 0xfe080000
571 #define INTC2_FIRST_IRQ 64
572 #define INTC2_INTREQ_OFFSET 0x20
573 #define INTC2_INTMSK_OFFSET 0x40
574 #define INTC2_INTMSKCLR_OFFSET 0x60
575 #define NR_INTC2_IRQS 25
576 #elif defined(CONFIG_CPU_SUBTYPE_SH7760)
577 #define INTC2_BASE 0xfe080000
578 #define INTC2_FIRST_IRQ 48 /* INTEVT 0x800 */
579 #define INTC2_INTREQ_OFFSET 0x20
580 #define INTC2_INTMSK_OFFSET 0x40
581 #define INTC2_INTMSKCLR_OFFSET 0x60
582 #define NR_INTC2_IRQS 64
583 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
584 #define INTC2_BASE 0xffd40000
585 #define INTC2_FIRST_IRQ 21
586 #define INTC2_INTMSK_OFFSET (0x38)
587 #define INTC2_INTMSKCLR_OFFSET (0x3c)
588 #define NR_INTC2_IRQS 60
591 #define INTC2_INTPRI_OFFSET 0x00
593 void make_intc2_irq(unsigned int irq,
594 unsigned int ipr_offset, unsigned int ipr_shift,
595 unsigned int msk_offset, unsigned int msk_shift,
596 unsigned int priority);
597 void init_IRQ_intc2(void);
598 void intc2_add_clear_irq(int irq, int (*fn)(int));
602 static inline int generic_irq_demux(int irq)
608 #define __irq_demux(irq) (irq)
610 #define irq_canonicalize(irq) (irq)
611 #define irq_demux(irq) __irq_demux(sh_mv.mv_irq_demux(irq))
613 #if defined(CONFIG_CPU_SUBTYPE_SH73180)
614 #include <asm/irq-sh73180.h>
617 #endif /* __ASM_SH_IRQ_H */