1 #ifndef _ASM_POWERPC_PTRACE_H
2 #define _ASM_POWERPC_PTRACE_H
5 * Copyright (C) 2001 PPC64 Team, IBM Corp
7 * This struct defines the way the registers are stored on the
8 * kernel stack during a system call or other kernel entry.
10 * this should only contain volatile regs
11 * since we can keep non-volatile in the thread_struct
12 * should set this up when only volatiles are saved
15 * Since this is going on the stack, *CARE MUST BE TAKEN* to insure
16 * that the overall structure is a multiple of 16 bytes in length.
18 * Note that the offsets of the fields in this struct correspond with
19 * the PT_* values below. This simplifies arch/powerpc/kernel/ptrace.c.
21 * This program is free software; you can redistribute it and/or
22 * modify it under the terms of the GNU General Public License
23 * as published by the Free Software Foundation; either version
24 * 2 of the License, or (at your option) any later version.
30 unsigned long gpr[32];
33 unsigned long orig_gpr3; /* Used for restarting system calls */
39 unsigned long softe; /* Soft enabled/disabled */
41 unsigned long mq; /* 601 only (not used at present) */
42 /* Used on APUS to hold IPL value. */
44 unsigned long trap; /* Reason for being here */
45 /* N.B. for critical exceptions on 4xx, the dar and dsisr
46 fields are overloaded to hold srr0 and srr1. */
47 unsigned long dar; /* Fault registers */
48 unsigned long dsisr; /* on 4xx/Book-E used for ESR */
49 unsigned long result; /* Result of a system call */
52 #endif /* __ASSEMBLY__ */
58 #define STACK_FRAME_OVERHEAD 112 /* size of minimum stack frame */
60 /* Size of dummy stack frame allocated when calling signal handler. */
61 #define __SIGNAL_FRAMESIZE 128
62 #define __SIGNAL_FRAMESIZE32 64
64 #else /* __powerpc64__ */
66 #define STACK_FRAME_OVERHEAD 16 /* size of minimum stack frame */
68 /* Size of stack frame allocated when calling signal handler. */
69 #define __SIGNAL_FRAMESIZE 64
71 #endif /* __powerpc64__ */
75 #define instruction_pointer(regs) ((regs)->nip)
77 extern unsigned long profile_pc(struct pt_regs *regs);
79 #define profile_pc(regs) instruction_pointer(regs)
83 #define user_mode(regs) ((((regs)->msr) >> MSR_PR_LG) & 0x1)
85 #define user_mode(regs) (((regs)->msr & MSR_PR) != 0)
88 #define force_successful_syscall_return() \
90 current_thread_info()->syscall_noerror = 1; \
94 * We use the least-significant bit of the trap field to indicate
95 * whether we have saved the full set of registers, or only a
96 * partial set. A 1 there means the partial set.
97 * On 4xx we use the next bit to indicate whether the exception
98 * is a critical exception (1 means it is).
100 #define FULL_REGS(regs) (((regs)->trap & 1) == 0)
101 #ifndef __powerpc64__
102 #define IS_CRITICAL_EXC(regs) (((regs)->trap & 2) == 0)
103 #endif /* ! __powerpc64__ */
104 #define TRAP(regs) ((regs)->trap & ~0xF)
106 #define CHECK_FULL_REGS(regs) BUG_ON(regs->trap & 1)
108 #define CHECK_FULL_REGS(regs) \
110 if ((regs)->trap & 1) \
111 printk(KERN_CRIT "%s: partial register set\n", __FUNCTION__); \
113 #endif /* __powerpc64__ */
115 #endif /* __ASSEMBLY__ */
117 #endif /* __KERNEL__ */
120 * Offsets used by 'ptrace' system call interface.
121 * These can't be changed without breaking binary compatibility
160 #define PT_ORIG_R3 34
166 #ifndef __powerpc64__
176 #define PT_FPR0 48 /* each FP reg occupies 2 slots in this space */
178 #ifndef __powerpc64__
180 #define PT_FPR31 (PT_FPR0 + 2*31)
181 #define PT_FPSCR (PT_FPR0 + 2*32 + 1)
183 #else /* __powerpc64__ */
185 #define PT_FPSCR (PT_FPR0 + 32) /* each FP reg occupies 1 slot in 64-bit space */
188 #define PT_FPSCR32 (PT_FPR0 + 2*32 + 1) /* each FP reg occupies 2 32-bit userspace slots */
191 #define PT_VR0 82 /* each Vector reg occupies 2 slots in 64-bit */
192 #define PT_VSCR (PT_VR0 + 32*2 + 1)
193 #define PT_VRSAVE (PT_VR0 + 33*2)
196 #define PT_VR0_32 164 /* each Vector reg occupies 4 slots in 32-bit */
197 #define PT_VSCR_32 (PT_VR0 + 32*4 + 3)
198 #define PT_VRSAVE_32 (PT_VR0 + 33*4)
201 #endif /* __powerpc64__ */
204 * Get/set all the altivec registers vr0..vr31, vscr, vrsave, in one go.
205 * The transfer totals 34 quadword. Quadwords 0-31 contain the
206 * corresponding vector registers. Quadword 32 contains the vscr as the
207 * last word (offset 12) within that quadword. Quadword 33 contains the
208 * vrsave as the first word (offset 0) within the quadword.
210 * This definition of the VMX state is compatible with the current PPC32
211 * ptrace interface. This allows signal handling and ptrace to use the same
212 * structures. This also simplifies the implementation of a bi-arch
213 * (combined (32- and 64-bit) gdb.
215 #define PTRACE_GETVRREGS 18
216 #define PTRACE_SETVRREGS 19
218 #ifndef __powerpc64__
219 /* Get/set all the upper 32-bits of the SPE registers, accumulator, and
220 * spefscr, in one go */
221 #define PTRACE_GETEVRREGS 20
222 #define PTRACE_SETEVRREGS 21
223 #endif /* __powerpc64__ */
226 * Get or set a debug register. The first 16 are DABR registers and the
227 * second 16 are IABR registers.
229 #define PTRACE_GET_DEBUGREG 25
230 #define PTRACE_SET_DEBUGREG 26
233 /* Additional PTRACE requests implemented on PowerPC. */
234 #define PPC_PTRACE_GETREGS 0x99 /* Get GPRs 0 - 31 */
235 #define PPC_PTRACE_SETREGS 0x98 /* Set GPRs 0 - 31 */
236 #define PPC_PTRACE_GETFPREGS 0x97 /* Get FPRs 0 - 31 */
237 #define PPC_PTRACE_SETFPREGS 0x96 /* Set FPRs 0 - 31 */
239 /* Calls to trace a 64bit program from a 32bit program */
240 #define PPC_PTRACE_PEEKTEXT_3264 0x95
241 #define PPC_PTRACE_PEEKDATA_3264 0x94
242 #define PPC_PTRACE_POKETEXT_3264 0x93
243 #define PPC_PTRACE_POKEDATA_3264 0x92
244 #define PPC_PTRACE_PEEKUSR_3264 0x91
245 #define PPC_PTRACE_POKEUSR_3264 0x90
246 #endif /* __powerpc64__ */
248 #endif /* _ASM_POWERPC_PTRACE_H */