1 #ifndef _ASM_POWERPC_PCI_BRIDGE_H
2 #define _ASM_POWERPC_PCI_BRIDGE_H
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
10 #include <linux/pci.h>
11 #include <linux/list.h>
12 #include <linux/ioport.h>
15 * Structure of a PCI controller (host bridge)
17 struct pci_controller {
24 struct list_head list_node;
25 struct device *parent;
33 void __iomem *io_base_virt;
37 resource_size_t io_base_phys;
39 /* Some machines (PReP) have a non 1:1 mapping of
40 * the PCI memory space in the CPU bus space
42 resource_size_t pci_mem_offset;
44 unsigned long pci_io_size;
48 volatile unsigned int __iomem *cfg_addr;
49 volatile void __iomem *cfg_data;
53 * Used for variants of PCI indirect handling and possible quirks:
54 * SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
55 * EXT_REG - provides access to PCI-e extended registers
56 * SURPRESS_PRIMARY_BUS - we surpress the setting of PCI_PRIMARY_BUS
57 * on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
58 * to determine which bus number to match on when generating type0
60 * NO_PCIE_LINK - the Freescale PCI-e controllers have issues with
61 * hanging if we don't have link and try to do config cycles to
62 * anything but the PHB. Only allow talking to the PHB if this is
64 * BIG_ENDIAN - cfg_addr is a big endian register
66 #define PPC_INDIRECT_TYPE_SET_CFG_TYPE 0x00000001
67 #define PPC_INDIRECT_TYPE_EXT_REG 0x00000002
68 #define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS 0x00000004
69 #define PPC_INDIRECT_TYPE_NO_PCIE_LINK 0x00000008
70 #define PPC_INDIRECT_TYPE_BIG_ENDIAN 0x00000010
72 #endif /* !CONFIG_PPC64 */
73 /* Currently, we limit ourselves to 1 IO range and 3 mem
74 * ranges since the common pci_bus structure can't handle more
76 struct resource io_resource;
77 struct resource mem_resources[3];
78 int global_number; /* PCI domain number */
81 unsigned long dma_window_base_cur;
82 unsigned long dma_window_size;
85 #endif /* CONFIG_PPC64 */
90 static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus)
95 static inline int isa_vaddr_is_ioport(void __iomem *address)
97 /* No specific ISA handling on ppc32 at this stage, it
98 * all goes through PCI
103 /* These are used for config access before all the PCI probing
105 extern int early_read_config_byte(struct pci_controller *hose, int bus,
106 int dev_fn, int where, u8 *val);
107 extern int early_read_config_word(struct pci_controller *hose, int bus,
108 int dev_fn, int where, u16 *val);
109 extern int early_read_config_dword(struct pci_controller *hose, int bus,
110 int dev_fn, int where, u32 *val);
111 extern int early_write_config_byte(struct pci_controller *hose, int bus,
112 int dev_fn, int where, u8 val);
113 extern int early_write_config_word(struct pci_controller *hose, int bus,
114 int dev_fn, int where, u16 val);
115 extern int early_write_config_dword(struct pci_controller *hose, int bus,
116 int dev_fn, int where, u32 val);
118 extern int early_find_capability(struct pci_controller *hose, int bus,
119 int dev_fn, int cap);
121 extern void setup_indirect_pci(struct pci_controller* hose,
122 resource_size_t cfg_addr,
123 resource_size_t cfg_data, u32 flags);
124 extern void setup_grackle(struct pci_controller *hose);
125 extern void __init update_bridge_resource(struct pci_dev *dev,
126 struct resource *res);
128 #else /* CONFIG_PPC64 */
131 * PCI stuff, for nodes representing PCI devices, pointed to
132 * by device_node->data.
138 int busno; /* pci bus number */
139 int bussubno; /* pci subordinate bus number */
140 int devfn; /* pci device and function number */
141 int class_code; /* pci device class */
143 struct pci_controller *phb; /* for pci devices */
144 struct iommu_table *iommu_table; /* for phb's or bridges */
145 struct pci_dev *pcidev; /* back-pointer to the pci device */
146 struct device_node *node; /* back-pointer to the device_node */
148 int pci_ext_config_space; /* for pci devices */
151 int eeh_mode; /* See eeh.h for possible EEH_MODEs */
153 int eeh_pe_config_addr; /* new-style partition endpoint address */
154 int eeh_check_count; /* # times driver ignored error */
155 int eeh_freeze_count; /* # times this device froze up. */
156 int eeh_false_positives; /* # times this device reported #ff's */
157 u32 config_space[16]; /* saved PCI config space */
161 /* Get the pointer to a device_node's pci_dn */
162 #define PCI_DN(dn) ((struct pci_dn *) (dn)->data)
164 extern struct device_node *fetch_dev_dn(struct pci_dev *dev);
166 /* Get a device_node from a pci_dev. This code must be fast except
167 * in the case where the sysdata is incorrect and needs to be fixed
168 * up (this will only happen once).
169 * In this case the sysdata will have been inherited from a PCI host
170 * bridge or a PCI-PCI bridge further up the tree, so it will point
171 * to a valid struct pci_dn, just not the one we want.
173 static inline struct device_node *pci_device_to_OF_node(struct pci_dev *dev)
175 struct device_node *dn = dev->sysdata;
176 struct pci_dn *pdn = dn->data;
178 if (pdn && pdn->devfn == dev->devfn && pdn->busno == dev->bus->number)
179 return dn; /* fast path. sysdata is good */
180 return fetch_dev_dn(dev);
183 static inline int pci_device_from_OF_node(struct device_node *np,
188 *bus = PCI_DN(np)->busno;
189 *devfn = PCI_DN(np)->devfn;
193 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
196 return pci_device_to_OF_node(bus->self);
198 return bus->sysdata; /* Must be root bus (PHB) */
201 /** Find the bus corresponding to the indicated device node */
202 extern struct pci_bus *pcibios_find_pci_bus(struct device_node *dn);
204 /** Remove all of the PCI devices under this bus */
205 extern void pcibios_remove_pci_devices(struct pci_bus *bus);
207 /** Discover new pci devices under this bus, and add them */
208 extern void pcibios_add_pci_devices(struct pci_bus *bus);
209 extern void pcibios_fixup_new_pci_devices(struct pci_bus *bus, int fix_bus);
211 extern int pcibios_remove_root_bus(struct pci_controller *phb);
213 static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus)
215 struct device_node *busdn = bus->sysdata;
217 BUG_ON(busdn == NULL);
218 return PCI_DN(busdn)->phb;
222 extern void isa_bridge_find_early(struct pci_controller *hose);
224 static inline int isa_vaddr_is_ioport(void __iomem *address)
226 /* Check if address hits the reserved legacy IO range */
227 unsigned long ea = (unsigned long)address;
228 return ea >= ISA_IO_BASE && ea < ISA_IO_END;
231 extern int pcibios_unmap_io_space(struct pci_bus *bus);
232 extern int pcibios_map_io_space(struct pci_bus *bus);
234 /* Return values for ppc_md.pci_probe_mode function */
235 #define PCI_PROBE_NONE -1 /* Don't look at this bus at all */
236 #define PCI_PROBE_NORMAL 0 /* Do normal PCI probing */
237 #define PCI_PROBE_DEVTREE 1 /* Instantiate from device tree */
240 #define PHB_SET_NODE(PHB, NODE) ((PHB)->node = (NODE))
242 #define PHB_SET_NODE(PHB, NODE) ((PHB)->node = -1)
245 #endif /* CONFIG_PPC64 */
247 /* Get the PCI host controller for an OF device */
248 extern struct pci_controller *pci_find_hose_for_OF_device(
249 struct device_node* node);
251 /* Fill up host controller resources from the OF node */
252 extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
253 struct device_node *dev, int primary);
255 /* Allocate & free a PCI host bridge structure */
256 extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev);
257 extern void pcibios_free_controller(struct pci_controller *phb);
260 extern unsigned long pci_address_to_pio(phys_addr_t address);
261 extern int pcibios_vaddr_is_ioport(void __iomem *address);
263 static inline unsigned long pci_address_to_pio(phys_addr_t address)
265 return (unsigned long)-1;
267 static inline int pcibios_vaddr_is_ioport(void __iomem *address)
271 #endif /* CONFIG_PCI */
273 #endif /* __KERNEL__ */
274 #endif /* _ASM_POWERPC_PCI_BRIDGE_H */