include/asm-powerpc/cputable.h

   1 #ifndef __ASM_POWERPC_CPUTABLE_H
   2 #define __ASM_POWERPC_CPUTABLE_H
   3
   4 #include <asm/asm-compat.h>
   5
   6 #define PPC_FEATURE_32                  0x80000000
   7 #define PPC_FEATURE_64                  0x40000000
   8 #define PPC_FEATURE_601_INSTR           0x20000000
   9 #define PPC_FEATURE_HAS_ALTIVEC         0x10000000
  10 #define PPC_FEATURE_HAS_FPU             0x08000000
  11 #define PPC_FEATURE_HAS_MMU             0x04000000
  12 #define PPC_FEATURE_HAS_4xxMAC          0x02000000
  13 #define PPC_FEATURE_UNIFIED_CACHE       0x01000000
  14 #define PPC_FEATURE_HAS_SPE             0x00800000
  15 #define PPC_FEATURE_HAS_EFP_SINGLE      0x00400000
  16 #define PPC_FEATURE_HAS_EFP_DOUBLE      0x00200000
  17 #define PPC_FEATURE_NO_TB               0x00100000
  18 #define PPC_FEATURE_POWER4              0x00080000
  19 #define PPC_FEATURE_POWER5              0x00040000
  20 #define PPC_FEATURE_POWER5_PLUS         0x00020000
  21 #define PPC_FEATURE_CELL                0x00010000
  22
  23 #ifdef __KERNEL__
  24 #ifndef __ASSEMBLY__
  25
  26 /* This structure can grow, it's real size is used by head.S code
  27  * via the mkdefs mechanism.
  28  */
  29 struct cpu_spec;
  30
  31 typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
  32
  33 enum powerpc_oprofile_type {
  34         INVALID = 0,
  35         RS64 = 1,
  36         POWER4 = 2,
  37         G4 = 3,
  38         BOOKE = 4,
  39 };
  40
  41 struct cpu_spec {
  42         /* CPU is matched via (PVR & pvr_mask) == pvr_value */
  43         unsigned int    pvr_mask;
  44         unsigned int    pvr_value;
  45
  46         char            *cpu_name;
  47         unsigned long   cpu_features;           /* Kernel features */
  48         unsigned int    cpu_user_features;      /* Userland features */
  49
  50         /* cache line sizes */
  51         unsigned int    icache_bsize;
  52         unsigned int    dcache_bsize;
  53
  54         /* number of performance monitor counters */
  55         unsigned int    num_pmcs;
  56
  57         /* this is called to initialize various CPU bits like L1 cache,
  58          * BHT, SPD, etc... from head.S before branching to identify_machine
  59          */
  60         cpu_setup_t     cpu_setup;
  61
  62         /* Used by oprofile userspace to select the right counters */
  63         char            *oprofile_cpu_type;
  64
  65         /* Processor specific oprofile operations */
  66         enum powerpc_oprofile_type oprofile_type;
  67 };
  68
  69 extern struct cpu_spec          *cur_cpu_spec;
  70
  71 extern void identify_cpu(unsigned long offset, unsigned long cpu);
  72 extern void do_cpu_ftr_fixups(unsigned long offset);
  73
  74 #endif /* __ASSEMBLY__ */
  75
  76 /* CPU kernel features */
  77
  78 /* Retain the 32b definitions all use bottom half of word */
  79 #define CPU_FTR_SPLIT_ID_CACHE          ASM_CONST(0x0000000000000001)
  80 #define CPU_FTR_L2CR                    ASM_CONST(0x0000000000000002)
  81 #define CPU_FTR_SPEC7450                ASM_CONST(0x0000000000000004)
  82 #define CPU_FTR_ALTIVEC                 ASM_CONST(0x0000000000000008)
  83 #define CPU_FTR_TAU                     ASM_CONST(0x0000000000000010)
  84 #define CPU_FTR_CAN_DOZE                ASM_CONST(0x0000000000000020)
  85 #define CPU_FTR_USE_TB                  ASM_CONST(0x0000000000000040)
  86 #define CPU_FTR_604_PERF_MON            ASM_CONST(0x0000000000000080)
  87 #define CPU_FTR_601                     ASM_CONST(0x0000000000000100)
  88 #define CPU_FTR_HPTE_TABLE              ASM_CONST(0x0000000000000200)
  89 #define CPU_FTR_CAN_NAP                 ASM_CONST(0x0000000000000400)
  90 #define CPU_FTR_L3CR                    ASM_CONST(0x0000000000000800)
  91 #define CPU_FTR_L3_DISABLE_NAP          ASM_CONST(0x0000000000001000)
  92 #define CPU_FTR_NAP_DISABLE_L2_PR       ASM_CONST(0x0000000000002000)
  93 #define CPU_FTR_DUAL_PLL_750FX          ASM_CONST(0x0000000000004000)
  94 #define CPU_FTR_NO_DPM                  ASM_CONST(0x0000000000008000)
  95 #define CPU_FTR_HAS_HIGH_BATS           ASM_CONST(0x0000000000010000)
  96 #define CPU_FTR_NEED_COHERENT           ASM_CONST(0x0000000000020000)
  97 #define CPU_FTR_NO_BTIC                 ASM_CONST(0x0000000000040000)
  98 #define CPU_FTR_BIG_PHYS                ASM_CONST(0x0000000000080000)
  99 #define CPU_FTR_NODSISRALIGN            ASM_CONST(0x0000000000100000)
 100
 101 #ifdef __powerpc64__
 102 /* Add the 64b processor unique features in the top half of the word */
 103 #define CPU_FTR_SLB                     ASM_CONST(0x0000000100000000)
 104 #define CPU_FTR_16M_PAGE                ASM_CONST(0x0000000200000000)
 105 #define CPU_FTR_TLBIEL                  ASM_CONST(0x0000000400000000)
 106 #define CPU_FTR_NOEXECUTE               ASM_CONST(0x0000000800000000)
 107 #define CPU_FTR_IABR                    ASM_CONST(0x0000002000000000)
 108 #define CPU_FTR_MMCRA                   ASM_CONST(0x0000004000000000)
 109 #define CPU_FTR_CTRL                    ASM_CONST(0x0000008000000000)
 110 #define CPU_FTR_SMT                     ASM_CONST(0x0000010000000000)
 111 #define CPU_FTR_COHERENT_ICACHE         ASM_CONST(0x0000020000000000)
 112 #define CPU_FTR_LOCKLESS_TLBIE          ASM_CONST(0x0000040000000000)
 113 #define CPU_FTR_MMCRA_SIHV              ASM_CONST(0x0000080000000000)
 114 #define CPU_FTR_CI_LARGE_PAGE           ASM_CONST(0x0000100000000000)
 115 #define CPU_FTR_PAUSE_ZERO              ASM_CONST(0x0000200000000000)
 116 #else
 117 /* ensure on 32b processors the flags are available for compiling but
 118  * don't do anything */
 119 #define CPU_FTR_SLB                     ASM_CONST(0x0)
 120 #define CPU_FTR_16M_PAGE                ASM_CONST(0x0)
 121 #define CPU_FTR_TLBIEL                  ASM_CONST(0x0)
 122 #define CPU_FTR_NOEXECUTE               ASM_CONST(0x0)
 123 #define CPU_FTR_IABR                    ASM_CONST(0x0)
 124 #define CPU_FTR_MMCRA                   ASM_CONST(0x0)
 125 #define CPU_FTR_CTRL                    ASM_CONST(0x0)
 126 #define CPU_FTR_SMT                     ASM_CONST(0x0)
 127 #define CPU_FTR_COHERENT_ICACHE         ASM_CONST(0x0)
 128 #define CPU_FTR_LOCKLESS_TLBIE          ASM_CONST(0x0)
 129 #define CPU_FTR_MMCRA_SIHV              ASM_CONST(0x0)
 130 #define CPU_FTR_CI_LARGE_PAGE           ASM_CONST(0x0)
 131 #endif
 132
 133 #ifndef __ASSEMBLY__
 134
 135 #define CPU_FTR_PPCAS_ARCH_V2_BASE (CPU_FTR_SLB | \
 136                                         CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
 137                                         CPU_FTR_NODSISRALIGN | CPU_FTR_CTRL)
 138
 139 /* iSeries doesn't support large pages */
 140 #ifdef CONFIG_PPC_ISERIES
 141 #define CPU_FTR_PPCAS_ARCH_V2   (CPU_FTR_PPCAS_ARCH_V2_BASE)
 142 #else
 143 #define CPU_FTR_PPCAS_ARCH_V2   (CPU_FTR_PPCAS_ARCH_V2_BASE | CPU_FTR_16M_PAGE)
 144 #endif /* CONFIG_PPC_ISERIES */
 145
 146 /* We only set the altivec features if the kernel was compiled with altivec
 147  * support
 148  */
 149 #ifdef CONFIG_ALTIVEC
 150 #define CPU_FTR_ALTIVEC_COMP    CPU_FTR_ALTIVEC
 151 #define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
 152 #else
 153 #define CPU_FTR_ALTIVEC_COMP    0
 154 #define PPC_FEATURE_HAS_ALTIVEC_COMP    0
 155 #endif
 156
 157 /* We need to mark all pages as being coherent if we're SMP or we
 158  * have a 74[45]x and an MPC107 host bridge.
 159  */
 160 #if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE)
 161 #define CPU_FTR_COMMON                  CPU_FTR_NEED_COHERENT
 162 #else
 163 #define CPU_FTR_COMMON                  0
 164 #endif
 165
 166 /* The powersave features NAP & DOZE seems to confuse BDI when
 167    debugging. So if a BDI is used, disable theses
 168  */
 169 #ifndef CONFIG_BDI_SWITCH
 170 #define CPU_FTR_MAYBE_CAN_DOZE  CPU_FTR_CAN_DOZE
 171 #define CPU_FTR_MAYBE_CAN_NAP   CPU_FTR_CAN_NAP
 172 #else
 173 #define CPU_FTR_MAYBE_CAN_DOZE  0
 174 #define CPU_FTR_MAYBE_CAN_NAP   0
 175 #endif
 176
 177 #define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
 178                      !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
 179                      !defined(CONFIG_BOOKE))
 180
 181 enum {
 182         CPU_FTRS_PPC601 = CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE,
 183         CPU_FTRS_603 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
 184             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
 185             CPU_FTR_MAYBE_CAN_NAP,
 186         CPU_FTRS_604 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
 187             CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE,
 188         CPU_FTRS_740_NOTAU = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
 189             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
 190             CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
 191         CPU_FTRS_740 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
 192             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
 193             CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
 194         CPU_FTRS_750 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
 195             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
 196             CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
 197         CPU_FTRS_750FX1 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
 198             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
 199             CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
 200             CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM,
 201         CPU_FTRS_750FX2 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
 202             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
 203             CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
 204             CPU_FTR_NO_DPM,
 205         CPU_FTRS_750FX = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
 206             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
 207             CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
 208             CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS,
 209         CPU_FTRS_750GX = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
 210             CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
 211             CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
 212             CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS,
 213         CPU_FTRS_7400_NOTAU = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
 214             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
 215             CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
 216             CPU_FTR_MAYBE_CAN_NAP,
 217         CPU_FTRS_7400 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
 218             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
 219             CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
 220             CPU_FTR_MAYBE_CAN_NAP,
 221         CPU_FTRS_7450_20 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
 222             CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
 223             CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
 224             CPU_FTR_NEED_COHERENT,
 225         CPU_FTRS_7450_21 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
 226             CPU_FTR_USE_TB |
 227             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
 228             CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
 229             CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP |
 230             CPU_FTR_NEED_COHERENT,
 231         CPU_FTRS_7450_23 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
 232             CPU_FTR_USE_TB |
 233             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
 234             CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
 235             CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT,
 236         CPU_FTRS_7455_1 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
 237             CPU_FTR_USE_TB |
 238             CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
 239             CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS |
 240             CPU_FTR_NEED_COHERENT,
 241         CPU_FTRS_7455_20 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
 242             CPU_FTR_USE_TB |
 243             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
 244             CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
 245             CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP |
 246             CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS,
 247         CPU_FTRS_7455 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
 248             CPU_FTR_USE_TB |
 249             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
 250             CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
 251             CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
 252             CPU_FTR_NEED_COHERENT,
 253         CPU_FTRS_7447_10 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
 254             CPU_FTR_USE_TB |
 255             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
 256             CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
 257             CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
 258             CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
 259         CPU_FTRS_7447 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
 260             CPU_FTR_USE_TB |
 261             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
 262             CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
 263             CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
 264             CPU_FTR_NEED_COHERENT,
 265         CPU_FTRS_7447A = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
 266             CPU_FTR_USE_TB |
 267             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
 268             CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
 269             CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
 270             CPU_FTR_NEED_COHERENT,
 271         CPU_FTRS_82XX = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
 272             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB,
 273         CPU_FTRS_G2_LE = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
 274             CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS,
 275         CPU_FTRS_E300 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
 276             CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS,
 277         CPU_FTRS_CLASSIC32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
 278             CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
 279         CPU_FTRS_POWER3_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
 280             CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
 281         CPU_FTRS_POWER4_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
 282             CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_NODSISRALIGN,
 283         CPU_FTRS_970_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
 284             CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_ALTIVEC_COMP |
 285             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN,
 286         CPU_FTRS_8XX = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 287         CPU_FTRS_40X = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
 288             CPU_FTR_NODSISRALIGN,
 289         CPU_FTRS_44X = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
 290             CPU_FTR_NODSISRALIGN,
 291         CPU_FTRS_E200 = CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN,
 292         CPU_FTRS_E500 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
 293             CPU_FTR_NODSISRALIGN,
 294         CPU_FTRS_E500_2 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
 295             CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN,
 296         CPU_FTRS_GENERIC_32 = CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN,
 297 #ifdef __powerpc64__
 298         CPU_FTRS_POWER3 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
 299             CPU_FTR_HPTE_TABLE | CPU_FTR_IABR,
 300         CPU_FTRS_RS64 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
 301             CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
 302             CPU_FTR_MMCRA | CPU_FTR_CTRL,
 303         CPU_FTRS_POWER4 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
 304             CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA,
 305         CPU_FTRS_PPC970 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
 306             CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 |
 307             CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA,
 308         CPU_FTRS_POWER5 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
 309             CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 |
 310             CPU_FTR_MMCRA | CPU_FTR_SMT |
 311             CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE |
 312             CPU_FTR_MMCRA_SIHV,
 313         CPU_FTRS_CELL = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
 314             CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 |
 315             CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT |
 316             CPU_FTR_CTRL | CPU_FTR_PAUSE_ZERO,
 317         CPU_FTRS_COMPATIBLE = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
 318             CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2,
 319 #endif
 320
 321         CPU_FTRS_POSSIBLE =
 322 #ifdef __powerpc64__
 323             CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 |
 324             CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_CELL |
 325             CPU_FTR_CI_LARGE_PAGE |
 326 #else
 327 #if CLASSIC_PPC
 328             CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
 329             CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
 330             CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
 331             CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
 332             CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
 333             CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
 334             CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
 335             CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_CLASSIC32 |
 336 #else
 337             CPU_FTRS_GENERIC_32 |
 338 #endif
 339 #ifdef CONFIG_PPC64BRIDGE
 340             CPU_FTRS_POWER3_32 |
 341 #endif
 342 #ifdef CONFIG_POWER4
 343             CPU_FTRS_POWER4_32 | CPU_FTRS_970_32 |
 344 #endif
 345 #ifdef CONFIG_8xx
 346             CPU_FTRS_8XX |
 347 #endif
 348 #ifdef CONFIG_40x
 349             CPU_FTRS_40X |
 350 #endif
 351 #ifdef CONFIG_44x
 352             CPU_FTRS_44X |
 353 #endif
 354 #ifdef CONFIG_E200
 355             CPU_FTRS_E200 |
 356 #endif
 357 #ifdef CONFIG_E500
 358             CPU_FTRS_E500 | CPU_FTRS_E500_2 |
 359 #endif
 360 #endif /* __powerpc64__ */
 361             0,
 362
 363         CPU_FTRS_ALWAYS =
 364 #ifdef __powerpc64__
 365             CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 &
 366             CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_CELL &
 367 #else
 368 #if CLASSIC_PPC
 369             CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
 370             CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
 371             CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
 372             CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
 373             CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
 374             CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
 375             CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
 376             CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_CLASSIC32 &
 377 #else
 378             CPU_FTRS_GENERIC_32 &
 379 #endif
 380 #ifdef CONFIG_PPC64BRIDGE
 381             CPU_FTRS_POWER3_32 &
 382 #endif
 383 #ifdef CONFIG_POWER4
 384             CPU_FTRS_POWER4_32 & CPU_FTRS_970_32 &
 385 #endif
 386 #ifdef CONFIG_8xx
 387             CPU_FTRS_8XX &
 388 #endif
 389 #ifdef CONFIG_40x
 390             CPU_FTRS_40X &
 391 #endif
 392 #ifdef CONFIG_44x
 393             CPU_FTRS_44X &
 394 #endif
 395 #ifdef CONFIG_E200
 396             CPU_FTRS_E200 &
 397 #endif
 398 #ifdef CONFIG_E500
 399             CPU_FTRS_E500 & CPU_FTRS_E500_2 &
 400 #endif
 401 #endif /* __powerpc64__ */
 402             CPU_FTRS_POSSIBLE,
 403 };
 404
 405 static inline int cpu_has_feature(unsigned long feature)
 406 {
 407         return (CPU_FTRS_ALWAYS & feature) ||
 408                (CPU_FTRS_POSSIBLE
 409                 & cur_cpu_spec->cpu_features
 410                 & feature);
 411 }
 412
 413 #endif /* !__ASSEMBLY__ */
 414
 415 #ifdef __ASSEMBLY__
 416
 417 #define BEGIN_FTR_SECTION               98:
 418
 419 #ifndef __powerpc64__
 420 #define END_FTR_SECTION(msk, val)               \
 421 99:                                             \
 422         .section __ftr_fixup,"a";               \
 423         .align 2;                               \
 424         .long msk;                              \
 425         .long val;                              \
 426         .long 98b;                              \
 427         .long 99b;                              \
 428         .previous
 429 #else /* __powerpc64__ */
 430 #define END_FTR_SECTION(msk, val)               \
 431 99:                                             \
 432         .section __ftr_fixup,"a";               \
 433         .align 3;                               \
 434         .llong msk;                             \
 435         .llong val;                             \
 436         .llong 98b;                             \
 437         .llong 99b;                             \
 438         .previous
 439 #endif /* __powerpc64__ */
 440
 441 #define END_FTR_SECTION_IFSET(msk)      END_FTR_SECTION((msk), (msk))
 442 #define END_FTR_SECTION_IFCLR(msk)      END_FTR_SECTION((msk), 0)
 443 #endif /* __ASSEMBLY__ */
 444
 445 #endif /* __KERNEL__ */
 446 #endif /* __ASM_POWERPC_CPUTABLE_H */