include/asm-mips/sibyte/sb1250_regs.h

   1 /*  *********************************************************************
   2     *  SB1250 Board Support Package
   3     *
   4     *  Register Definitions                     File: sb1250_regs.h
   5     *
   6     *  This module contains the addresses of the on-chip peripherals
   7     *  on the SB1250.
   8     *
   9     *  SB1250 specification level:  01/02/2002
  10     *
  11     *********************************************************************
  12     *
  13     *  Copyright 2000,2001,2002,2003
  14     *  Broadcom Corporation. All rights reserved.
  15     *
  16     *  This program is free software; you can redistribute it and/or
  17     *  modify it under the terms of the GNU General Public License as
  18     *  published by the Free Software Foundation; either version 2 of
  19     *  the License, or (at your option) any later version.
  20     *
  21     *  This program is distributed in the hope that it will be useful,
  22     *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  23     *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  24     *  GNU General Public License for more details.
  25     *
  26     *  You should have received a copy of the GNU General Public License
  27     *  along with this program; if not, write to the Free Software
  28     *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  29     *  MA 02111-1307 USA
  30     ********************************************************************* */
  31
  32
  33 #ifndef _SB1250_REGS_H
  34 #define _SB1250_REGS_H
  35
  36 #include "sb1250_defs.h"
  37
  38
  39 /*  *********************************************************************
  40     *  Some general notes:
  41     *
  42     *  For the most part, when there is more than one peripheral
  43     *  of the same type on the SOC, the constants below will be
  44     *  offsets from the base of each peripheral.  For example,
  45     *  the MAC registers are described as offsets from the first
  46     *  MAC register, and there will be a MAC_REGISTER() macro
  47     *  to calculate the base address of a given MAC.
  48     *
  49     *  The information in this file is based on the SB1250 SOC
  50     *  manual version 0.2, July 2000.
  51     ********************************************************************* */
  52
  53
  54 /*  *********************************************************************
  55     * Memory Controller Registers
  56     ********************************************************************* */
  57
  58 /*
  59  * XXX: can't remove MC base 0 if 112x, since it's used by other macros,
  60  * since there is one reg there (but it could get its addr/offset constant).
  61  */
  62
  63 #if SIBYTE_HDR_FEATURE_1250_112x                /* This MC only on 1250 & 112x */
  64 #define A_MC_BASE_0                 0x0010051000
  65 #define A_MC_BASE_1                 0x0010052000
  66 #define MC_REGISTER_SPACING         0x1000
  67
  68 #define A_MC_BASE(ctlid)            ((ctlid)*MC_REGISTER_SPACING+A_MC_BASE_0)
  69 #define A_MC_REGISTER(ctlid,reg)    (A_MC_BASE(ctlid)+(reg))
  70
  71 #define R_MC_CONFIG                 0x0000000100
  72 #define R_MC_DRAMCMD                0x0000000120
  73 #define R_MC_DRAMMODE               0x0000000140
  74 #define R_MC_TIMING1                0x0000000160
  75 #define R_MC_TIMING2                0x0000000180
  76 #define R_MC_CS_START               0x00000001A0
  77 #define R_MC_CS_END                 0x00000001C0
  78 #define R_MC_CS_INTERLEAVE          0x00000001E0
  79 #define S_MC_CS_STARTEND            16
  80
  81 #define R_MC_CSX_BASE               0x0000000200
  82 #define R_MC_CSX_ROW                0x0000000000        /* relative to CSX_BASE, above */
  83 #define R_MC_CSX_COL                0x0000000020        /* relative to CSX_BASE, above */
  84 #define R_MC_CSX_BA                 0x0000000040        /* relative to CSX_BASE, above */
  85 #define MC_CSX_SPACING              0x0000000060        /* relative to CSX_BASE, above */
  86
  87 #define R_MC_CS0_ROW                0x0000000200
  88 #define R_MC_CS0_COL                0x0000000220
  89 #define R_MC_CS0_BA                 0x0000000240
  90 #define R_MC_CS1_ROW                0x0000000260
  91 #define R_MC_CS1_COL                0x0000000280
  92 #define R_MC_CS1_BA                 0x00000002A0
  93 #define R_MC_CS2_ROW                0x00000002C0
  94 #define R_MC_CS2_COL                0x00000002E0
  95 #define R_MC_CS2_BA                 0x0000000300
  96 #define R_MC_CS3_ROW                0x0000000320
  97 #define R_MC_CS3_COL                0x0000000340
  98 #define R_MC_CS3_BA                 0x0000000360
  99 #define R_MC_CS_ATTR                0x0000000380
 100 #define R_MC_TEST_DATA              0x0000000400
 101 #define R_MC_TEST_ECC               0x0000000420
 102 #define R_MC_MCLK_CFG               0x0000000500
 103
 104 #endif  /* 1250 & 112x */
 105
 106 /*  *********************************************************************
 107     * L2 Cache Control Registers
 108     ********************************************************************* */
 109
 110 #if SIBYTE_HDR_FEATURE_1250_112x        /* This L2C only on 1250/112x */
 111
 112 #define A_L2_READ_TAG               0x0010040018
 113 #define A_L2_ECC_TAG                0x0010040038
 114 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
 115 #define A_L2_READ_MISC              0x0010040058
 116 #endif /* 1250 PASS3 || 112x PASS1 */
 117 #define A_L2_WAY_DISABLE            0x0010041000
 118 #define A_L2_MAKEDISABLE(x)         (A_L2_WAY_DISABLE | (((~(x))&0x0F) << 8))
 119 #define A_L2_MGMT_TAG_BASE          0x00D0000000
 120
 121 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
 122 #define A_L2_CACHE_DISABLE         0x0010042000
 123 #define A_L2_MAKECACHEDISABLE(x)   (A_L2_CACHE_DISABLE | (((x)&0x0F) << 8))
 124 #define A_L2_MISC_CONFIG           0x0010043000
 125 #endif /* 1250 PASS2 || 112x PASS1 */
 126
 127 /* Backward-compatibility definitions.  */
 128 /* XXX: discourage people from using these constants.  */
 129 #define A_L2_READ_ADDRESS           A_L2_READ_TAG
 130 #define A_L2_EEC_ADDRESS            A_L2_ECC_TAG
 131
 132 #endif
 133
 134
 135 /*  *********************************************************************
 136     * PCI Interface Registers
 137     ********************************************************************* */
 138
 139 #if SIBYTE_HDR_FEATURE_1250_112x        /* This PCI/HT only on 1250/112x */
 140 #define A_PCI_TYPE00_HEADER         0x00DE000000
 141 #define A_PCI_TYPE01_HEADER         0x00DE000800
 142 #endif
 143
 144
 145 /*  *********************************************************************
 146     * Ethernet DMA and MACs
 147     ********************************************************************* */
 148
 149 #define A_MAC_BASE_0                0x0010064000
 150 #define A_MAC_BASE_1                0x0010065000
 151 #if SIBYTE_HDR_FEATURE_CHIP(1250)
 152 #define A_MAC_BASE_2                0x0010066000
 153 #endif /* 1250 */
 154
 155 #define MAC_SPACING                 0x1000
 156 #define MAC_DMA_TXRX_SPACING        0x0400
 157 #define MAC_DMA_CHANNEL_SPACING     0x0100
 158 #define DMA_RX                      0
 159 #define DMA_TX                      1
 160 #define MAC_NUM_DMACHAN             2               /* channels per direction */
 161
 162 /* XXX: not correct; depends on SOC type.  */
 163 #define MAC_NUM_PORTS               3
 164
 165 #define A_MAC_CHANNEL_BASE(macnum)                  \
 166             (A_MAC_BASE_0 +                         \
 167              MAC_SPACING*(macnum))
 168
 169 #define A_MAC_REGISTER(macnum,reg)                  \
 170             (A_MAC_BASE_0 +                         \
 171              MAC_SPACING*(macnum) + (reg))
 172
 173
 174 #define R_MAC_DMA_CHANNELS              0x800 /* Relative to A_MAC_CHANNEL_BASE */
 175
 176 #define A_MAC_DMA_CHANNEL_BASE(macnum,txrx,chan)    \
 177              ((A_MAC_CHANNEL_BASE(macnum)) +        \
 178              R_MAC_DMA_CHANNELS +                   \
 179              (MAC_DMA_TXRX_SPACING*(txrx)) +        \
 180              (MAC_DMA_CHANNEL_SPACING*(chan)))
 181
 182 #define R_MAC_DMA_CHANNEL_BASE(txrx,chan)    \
 183              (R_MAC_DMA_CHANNELS +                   \
 184              (MAC_DMA_TXRX_SPACING*(txrx)) +        \
 185              (MAC_DMA_CHANNEL_SPACING*(chan)))
 186
 187 #define A_MAC_DMA_REGISTER(macnum,txrx,chan,reg)           \
 188             (A_MAC_DMA_CHANNEL_BASE(macnum,txrx,chan) +    \
 189             (reg))
 190
 191 #define R_MAC_DMA_REGISTER(txrx,chan,reg)           \
 192             (R_MAC_DMA_CHANNEL_BASE(txrx,chan) +    \
 193             (reg))
 194
 195 /*
 196  * DMA channel registers, relative to A_MAC_DMA_CHANNEL_BASE
 197  */
 198
 199 #define R_MAC_DMA_CONFIG0               0x00000000
 200 #define R_MAC_DMA_CONFIG1               0x00000008
 201 #define R_MAC_DMA_DSCR_BASE             0x00000010
 202 #define R_MAC_DMA_DSCR_CNT              0x00000018
 203 #define R_MAC_DMA_CUR_DSCRA             0x00000020
 204 #define R_MAC_DMA_CUR_DSCRB             0x00000028
 205 #define R_MAC_DMA_CUR_DSCRADDR          0x00000030
 206 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
 207 #define R_MAC_DMA_OODPKTLOST_RX         0x00000038      /* rx only */
 208 #endif /* 1250 PASS3 || 112x PASS1 */
 209
 210 /*
 211  * RMON Counters
 212  */
 213
 214 #define R_MAC_RMON_TX_BYTES             0x00000000
 215 #define R_MAC_RMON_COLLISIONS           0x00000008
 216 #define R_MAC_RMON_LATE_COL             0x00000010
 217 #define R_MAC_RMON_EX_COL               0x00000018
 218 #define R_MAC_RMON_FCS_ERROR            0x00000020
 219 #define R_MAC_RMON_TX_ABORT             0x00000028
 220 /* Counter #6 (0x30) now reserved */
 221 #define R_MAC_RMON_TX_BAD               0x00000038
 222 #define R_MAC_RMON_TX_GOOD              0x00000040
 223 #define R_MAC_RMON_TX_RUNT              0x00000048
 224 #define R_MAC_RMON_TX_OVERSIZE          0x00000050
 225 #define R_MAC_RMON_RX_BYTES             0x00000080
 226 #define R_MAC_RMON_RX_MCAST             0x00000088
 227 #define R_MAC_RMON_RX_BCAST             0x00000090
 228 #define R_MAC_RMON_RX_BAD               0x00000098
 229 #define R_MAC_RMON_RX_GOOD              0x000000A0
 230 #define R_MAC_RMON_RX_RUNT              0x000000A8
 231 #define R_MAC_RMON_RX_OVERSIZE          0x000000B0
 232 #define R_MAC_RMON_RX_FCS_ERROR         0x000000B8
 233 #define R_MAC_RMON_RX_LENGTH_ERROR      0x000000C0
 234 #define R_MAC_RMON_RX_CODE_ERROR        0x000000C8
 235 #define R_MAC_RMON_RX_ALIGN_ERROR       0x000000D0
 236
 237 /* Updated to spec 0.2 */
 238 #define R_MAC_CFG                       0x00000100
 239 #define R_MAC_THRSH_CFG                 0x00000108
 240 #define R_MAC_VLANTAG                   0x00000110
 241 #define R_MAC_FRAMECFG                  0x00000118
 242 #define R_MAC_EOPCNT                    0x00000120
 243 #define R_MAC_FIFO_PTRS                 0x00000128
 244 #define R_MAC_ADFILTER_CFG              0x00000200
 245 #define R_MAC_ETHERNET_ADDR             0x00000208
 246 #define R_MAC_PKT_TYPE                  0x00000210
 247 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 248 #define R_MAC_ADMASK0                   0x00000218
 249 #define R_MAC_ADMASK1                   0x00000220
 250 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 251 #define R_MAC_HASH_BASE                 0x00000240
 252 #define R_MAC_ADDR_BASE                 0x00000280
 253 #define R_MAC_CHLO0_BASE                0x00000300
 254 #define R_MAC_CHUP0_BASE                0x00000320
 255 #define R_MAC_ENABLE                    0x00000400
 256 #define R_MAC_STATUS                    0x00000408
 257 #define R_MAC_INT_MASK                  0x00000410
 258 #define R_MAC_TXD_CTL                   0x00000420
 259 #define R_MAC_MDIO                      0x00000428
 260 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 261 #define R_MAC_STATUS1                   0x00000430
 262 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */
 263 #define R_MAC_DEBUG_STATUS              0x00000448
 264
 265 #define MAC_HASH_COUNT                  8
 266 #define MAC_ADDR_COUNT                  8
 267 #define MAC_CHMAP_COUNT                 4
 268
 269
 270 /*  *********************************************************************
 271     * DUART Registers
 272     ********************************************************************* */
 273
 274
 275 #if SIBYTE_HDR_FEATURE_1250_112x                /* This MC only on 1250 & 112x */
 276 #define R_DUART_NUM_PORTS           2
 277
 278 #define A_DUART                     0x0010060000
 279
 280 #define DUART_CHANREG_SPACING       0x100
 281 #define A_DUART_CHANREG(chan,reg)   (A_DUART + DUART_CHANREG_SPACING*(chan) + (reg))
 282 #define R_DUART_CHANREG(chan,reg)   (DUART_CHANREG_SPACING*(chan) + (reg))
 283 #endif  /* 1250 & 112x */
 284
 285 #define R_DUART_MODE_REG_1          0x100
 286 #define R_DUART_MODE_REG_2          0x110
 287 #define R_DUART_STATUS              0x120
 288 #define R_DUART_CLK_SEL             0x130
 289 #define R_DUART_CMD                 0x150
 290 #define R_DUART_RX_HOLD             0x160
 291 #define R_DUART_TX_HOLD             0x170
 292
 293 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 294 #define R_DUART_FULL_CTL            0x140
 295 #define R_DUART_OPCR_X              0x180
 296 #define R_DUART_AUXCTL_X            0x190
 297 #endif /* 1250 PASS2 || 112x PASS1 || 1480*/
 298
 299
 300 /*
 301  * The IMR and ISR can't be addressed with A_DUART_CHANREG,
 302  * so use this macro instead.
 303  */
 304
 305 #define R_DUART_AUX_CTRL            0x310
 306 #define R_DUART_ISR_A               0x320
 307 #define R_DUART_IMR_A               0x330
 308 #define R_DUART_ISR_B               0x340
 309 #define R_DUART_IMR_B               0x350
 310 #define R_DUART_OUT_PORT            0x360
 311 #define R_DUART_OPCR                0x370
 312 #define R_DUART_IN_PORT             0x380
 313
 314 #define R_DUART_SET_OPR             0x3B0
 315 #define R_DUART_CLEAR_OPR           0x3C0
 316
 317 #define DUART_IMRISR_SPACING        0x20
 318
 319 #if SIBYTE_HDR_FEATURE_1250_112x                /* This MC only on 1250 & 112x */
 320 #define R_DUART_IMRREG(chan)        (R_DUART_IMR_A + (chan)*DUART_IMRISR_SPACING)
 321 #define R_DUART_ISRREG(chan)        (R_DUART_ISR_A + (chan)*DUART_IMRISR_SPACING)
 322
 323 #define A_DUART_IMRREG(chan)        (A_DUART + R_DUART_IMRREG(chan))
 324 #define A_DUART_ISRREG(chan)        (A_DUART + R_DUART_ISRREG(chan))
 325 #endif  /* 1250 & 112x */
 326
 327
 328
 329
 330 /*
 331  * These constants are the absolute addresses.
 332  */
 333
 334 #define A_DUART_MODE_REG_1_A        0x0010060100
 335 #define A_DUART_MODE_REG_2_A        0x0010060110
 336 #define A_DUART_STATUS_A            0x0010060120
 337 #define A_DUART_CLK_SEL_A           0x0010060130
 338 #define A_DUART_CMD_A               0x0010060150
 339 #define A_DUART_RX_HOLD_A           0x0010060160
 340 #define A_DUART_TX_HOLD_A           0x0010060170
 341
 342 #define A_DUART_MODE_REG_1_B        0x0010060200
 343 #define A_DUART_MODE_REG_2_B        0x0010060210
 344 #define A_DUART_STATUS_B            0x0010060220
 345 #define A_DUART_CLK_SEL_B           0x0010060230
 346 #define A_DUART_CMD_B               0x0010060250
 347 #define A_DUART_RX_HOLD_B           0x0010060260
 348 #define A_DUART_TX_HOLD_B           0x0010060270
 349
 350 #define A_DUART_INPORT_CHNG         0x0010060300
 351 #define A_DUART_AUX_CTRL            0x0010060310
 352 #define A_DUART_ISR_A               0x0010060320
 353 #define A_DUART_IMR_A               0x0010060330
 354 #define A_DUART_ISR_B               0x0010060340
 355 #define A_DUART_IMR_B               0x0010060350
 356 #define A_DUART_OUT_PORT            0x0010060360
 357 #define A_DUART_OPCR                0x0010060370
 358 #define A_DUART_IN_PORT             0x0010060380
 359 #define A_DUART_ISR                 0x0010060390
 360 #define A_DUART_IMR                 0x00100603A0
 361 #define A_DUART_SET_OPR             0x00100603B0
 362 #define A_DUART_CLEAR_OPR           0x00100603C0
 363 #define A_DUART_INPORT_CHNG_A       0x00100603D0
 364 #define A_DUART_INPORT_CHNG_B       0x00100603E0
 365
 366 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
 367 #define A_DUART_FULL_CTL_A          0x0010060140
 368 #define A_DUART_FULL_CTL_B          0x0010060240
 369
 370 #define A_DUART_OPCR_A              0x0010060180
 371 #define A_DUART_OPCR_B              0x0010060280
 372
 373 #define A_DUART_INPORT_CHNG_DEBUG   0x00100603F0
 374 #endif /* 1250 PASS2 || 112x PASS1 */
 375
 376
 377 /*  *********************************************************************
 378     * Synchronous Serial Registers
 379     ********************************************************************* */
 380
 381
 382 #if SIBYTE_HDR_FEATURE_1250_112x        /* sync serial only on 1250/112x */
 383
 384 #define A_SER_BASE_0                0x0010060400
 385 #define A_SER_BASE_1                0x0010060800
 386 #define SER_SPACING                 0x400
 387
 388 #define SER_DMA_TXRX_SPACING        0x80
 389
 390 #define SER_NUM_PORTS               2
 391
 392 #define A_SER_CHANNEL_BASE(sernum)                  \
 393             (A_SER_BASE_0 +                         \
 394              SER_SPACING*(sernum))
 395
 396 #define A_SER_REGISTER(sernum,reg)                  \
 397             (A_SER_BASE_0 +                         \
 398              SER_SPACING*(sernum) + (reg))
 399
 400
 401 #define R_SER_DMA_CHANNELS              0   /* Relative to A_SER_BASE_x */
 402
 403 #define A_SER_DMA_CHANNEL_BASE(sernum,txrx)    \
 404              ((A_SER_CHANNEL_BASE(sernum)) +        \
 405              R_SER_DMA_CHANNELS +                   \
 406              (SER_DMA_TXRX_SPACING*(txrx)))
 407
 408 #define A_SER_DMA_REGISTER(sernum,txrx,reg)           \
 409             (A_SER_DMA_CHANNEL_BASE(sernum,txrx) +    \
 410             (reg))
 411
 412
 413 /*
 414  * DMA channel registers, relative to A_SER_DMA_CHANNEL_BASE
 415  */
 416
 417 #define R_SER_DMA_CONFIG0           0x00000000
 418 #define R_SER_DMA_CONFIG1           0x00000008
 419 #define R_SER_DMA_DSCR_BASE         0x00000010
 420 #define R_SER_DMA_DSCR_CNT          0x00000018
 421 #define R_SER_DMA_CUR_DSCRA         0x00000020
 422 #define R_SER_DMA_CUR_DSCRB         0x00000028
 423 #define R_SER_DMA_CUR_DSCRADDR      0x00000030
 424
 425 #define R_SER_DMA_CONFIG0_RX        0x00000000
 426 #define R_SER_DMA_CONFIG1_RX        0x00000008
 427 #define R_SER_DMA_DSCR_BASE_RX      0x00000010
 428 #define R_SER_DMA_DSCR_COUNT_RX     0x00000018
 429 #define R_SER_DMA_CUR_DSCR_A_RX     0x00000020
 430 #define R_SER_DMA_CUR_DSCR_B_RX     0x00000028
 431 #define R_SER_DMA_CUR_DSCR_ADDR_RX  0x00000030
 432
 433 #define R_SER_DMA_CONFIG0_TX        0x00000080
 434 #define R_SER_DMA_CONFIG1_TX        0x00000088
 435 #define R_SER_DMA_DSCR_BASE_TX      0x00000090
 436 #define R_SER_DMA_DSCR_COUNT_TX     0x00000098
 437 #define R_SER_DMA_CUR_DSCR_A_TX     0x000000A0
 438 #define R_SER_DMA_CUR_DSCR_B_TX     0x000000A8
 439 #define R_SER_DMA_CUR_DSCR_ADDR_TX  0x000000B0
 440
 441 #define R_SER_MODE                  0x00000100
 442 #define R_SER_MINFRM_SZ             0x00000108
 443 #define R_SER_MAXFRM_SZ             0x00000110
 444 #define R_SER_ADDR                  0x00000118
 445 #define R_SER_USR0_ADDR             0x00000120
 446 #define R_SER_USR1_ADDR             0x00000128
 447 #define R_SER_USR2_ADDR             0x00000130
 448 #define R_SER_USR3_ADDR             0x00000138
 449 #define R_SER_CMD                   0x00000140
 450 #define R_SER_TX_RD_THRSH           0x00000160
 451 #define R_SER_TX_WR_THRSH           0x00000168
 452 #define R_SER_RX_RD_THRSH           0x00000170
 453 #define R_SER_LINE_MODE             0x00000178
 454 #define R_SER_DMA_ENABLE            0x00000180
 455 #define R_SER_INT_MASK              0x00000190
 456 #define R_SER_STATUS                0x00000188
 457 #define R_SER_STATUS_DEBUG          0x000001A8
 458 #define R_SER_RX_TABLE_BASE         0x00000200
 459 #define SER_RX_TABLE_COUNT          16
 460 #define R_SER_TX_TABLE_BASE         0x00000300
 461 #define SER_TX_TABLE_COUNT          16
 462
 463 /* RMON Counters */
 464 #define R_SER_RMON_TX_BYTE_LO       0x000001C0
 465 #define R_SER_RMON_TX_BYTE_HI       0x000001C8
 466 #define R_SER_RMON_RX_BYTE_LO       0x000001D0
 467 #define R_SER_RMON_RX_BYTE_HI       0x000001D8
 468 #define R_SER_RMON_TX_UNDERRUN      0x000001E0
 469 #define R_SER_RMON_RX_OVERFLOW      0x000001E8
 470 #define R_SER_RMON_RX_ERRORS        0x000001F0
 471 #define R_SER_RMON_RX_BADADDR       0x000001F8
 472
 473 #endif  /* 1250/112x */
 474
 475 /*  *********************************************************************
 476     * Generic Bus Registers
 477     ********************************************************************* */
 478
 479 #define IO_EXT_CFG_COUNT            8
 480
 481 #define A_IO_EXT_BASE               0x0010061000
 482 #define A_IO_EXT_REG(r)             (A_IO_EXT_BASE + (r))
 483
 484 #define A_IO_EXT_CFG_BASE           0x0010061000
 485 #define A_IO_EXT_MULT_SIZE_BASE     0x0010061100
 486 #define A_IO_EXT_START_ADDR_BASE    0x0010061200
 487 #define A_IO_EXT_TIME_CFG0_BASE     0x0010061600
 488 #define A_IO_EXT_TIME_CFG1_BASE     0x0010061700
 489
 490 #define IO_EXT_REGISTER_SPACING     8
 491 #define A_IO_EXT_CS_BASE(cs)        (A_IO_EXT_CFG_BASE+IO_EXT_REGISTER_SPACING*(cs))
 492 #define R_IO_EXT_REG(reg,cs)        ((cs)*IO_EXT_REGISTER_SPACING + (reg))
 493
 494 #define R_IO_EXT_CFG                0x0000
 495 #define R_IO_EXT_MULT_SIZE          0x0100
 496 #define R_IO_EXT_START_ADDR         0x0200
 497 #define R_IO_EXT_TIME_CFG0          0x0600
 498 #define R_IO_EXT_TIME_CFG1          0x0700
 499
 500
 501 #define A_IO_INTERRUPT_STATUS       0x0010061A00
 502 #define A_IO_INTERRUPT_DATA0        0x0010061A10
 503 #define A_IO_INTERRUPT_DATA1        0x0010061A18
 504 #define A_IO_INTERRUPT_DATA2        0x0010061A20
 505 #define A_IO_INTERRUPT_DATA3        0x0010061A28
 506 #define A_IO_INTERRUPT_ADDR0        0x0010061A30
 507 #define A_IO_INTERRUPT_ADDR1        0x0010061A40
 508 #define A_IO_INTERRUPT_PARITY       0x0010061A50
 509 #define A_IO_PCMCIA_CFG             0x0010061A60
 510 #define A_IO_PCMCIA_STATUS          0x0010061A70
 511 #define A_IO_DRIVE_0                0x0010061300
 512 #define A_IO_DRIVE_1                0x0010061308
 513 #define A_IO_DRIVE_2                0x0010061310
 514 #define A_IO_DRIVE_3                0x0010061318
 515 #define A_IO_DRIVE_BASE             A_IO_DRIVE_0
 516 #define IO_DRIVE_REGISTER_SPACING   8
 517 #define R_IO_DRIVE(x)               ((x)*IO_DRIVE_REGISTER_SPACING)
 518 #define A_IO_DRIVE(x)               (A_IO_DRIVE_BASE + R_IO_DRIVE(x))
 519
 520 #define R_IO_INTERRUPT_STATUS       0x0A00
 521 #define R_IO_INTERRUPT_DATA0        0x0A10
 522 #define R_IO_INTERRUPT_DATA1        0x0A18
 523 #define R_IO_INTERRUPT_DATA2        0x0A20
 524 #define R_IO_INTERRUPT_DATA3        0x0A28
 525 #define R_IO_INTERRUPT_ADDR0        0x0A30
 526 #define R_IO_INTERRUPT_ADDR1        0x0A40
 527 #define R_IO_INTERRUPT_PARITY       0x0A50
 528 #define R_IO_PCMCIA_CFG             0x0A60
 529 #define R_IO_PCMCIA_STATUS          0x0A70
 530
 531 /*  *********************************************************************
 532     * GPIO Registers
 533     ********************************************************************* */
 534
 535 #define A_GPIO_CLR_EDGE             0x0010061A80
 536 #define A_GPIO_INT_TYPE             0x0010061A88
 537 #define A_GPIO_INPUT_INVERT         0x0010061A90
 538 #define A_GPIO_GLITCH               0x0010061A98
 539 #define A_GPIO_READ                 0x0010061AA0
 540 #define A_GPIO_DIRECTION            0x0010061AA8
 541 #define A_GPIO_PIN_CLR              0x0010061AB0
 542 #define A_GPIO_PIN_SET              0x0010061AB8
 543
 544 #define A_GPIO_BASE                 0x0010061A80
 545
 546 #define R_GPIO_CLR_EDGE             0x00
 547 #define R_GPIO_INT_TYPE             0x08
 548 #define R_GPIO_INPUT_INVERT         0x10
 549 #define R_GPIO_GLITCH               0x18
 550 #define R_GPIO_READ                 0x20
 551 #define R_GPIO_DIRECTION            0x28
 552 #define R_GPIO_PIN_CLR              0x30
 553 #define R_GPIO_PIN_SET              0x38
 554
 555 /*  *********************************************************************
 556     * SMBus Registers
 557     ********************************************************************* */
 558
 559 #define A_SMB_XTRA_0                0x0010060000
 560 #define A_SMB_XTRA_1                0x0010060008
 561 #define A_SMB_FREQ_0                0x0010060010
 562 #define A_SMB_FREQ_1                0x0010060018
 563 #define A_SMB_STATUS_0              0x0010060020
 564 #define A_SMB_STATUS_1              0x0010060028
 565 #define A_SMB_CMD_0                 0x0010060030
 566 #define A_SMB_CMD_1                 0x0010060038
 567 #define A_SMB_START_0               0x0010060040
 568 #define A_SMB_START_1               0x0010060048
 569 #define A_SMB_DATA_0                0x0010060050
 570 #define A_SMB_DATA_1                0x0010060058
 571 #define A_SMB_CONTROL_0             0x0010060060
 572 #define A_SMB_CONTROL_1             0x0010060068
 573 #define A_SMB_PEC_0                 0x0010060070
 574 #define A_SMB_PEC_1                 0x0010060078
 575
 576 #define A_SMB_0                     0x0010060000
 577 #define A_SMB_1                     0x0010060008
 578 #define SMB_REGISTER_SPACING        0x8
 579 #define A_SMB_BASE(idx)             (A_SMB_0+(idx)*SMB_REGISTER_SPACING)
 580 #define A_SMB_REGISTER(idx,reg)     (A_SMB_BASE(idx)+(reg))
 581
 582 #define R_SMB_XTRA                  0x0000000000
 583 #define R_SMB_FREQ                  0x0000000010
 584 #define R_SMB_STATUS                0x0000000020
 585 #define R_SMB_CMD                   0x0000000030
 586 #define R_SMB_START                 0x0000000040
 587 #define R_SMB_DATA                  0x0000000050
 588 #define R_SMB_CONTROL               0x0000000060
 589 #define R_SMB_PEC                   0x0000000070
 590
 591 /*  *********************************************************************
 592     * Timer Registers
 593     ********************************************************************* */
 594
 595 /*
 596  * Watchdog timers
 597  */
 598
 599 #define A_SCD_WDOG_0                0x0010020050
 600 #define A_SCD_WDOG_1                0x0010020150
 601 #define SCD_WDOG_SPACING            0x100
 602 #define SCD_NUM_WDOGS               2
 603 #define A_SCD_WDOG_BASE(w)          (A_SCD_WDOG_0+SCD_WDOG_SPACING*(w))
 604 #define A_SCD_WDOG_REGISTER(w,r)    (A_SCD_WDOG_BASE(w) + (r))
 605
 606 #define R_SCD_WDOG_INIT             0x0000000000
 607 #define R_SCD_WDOG_CNT              0x0000000008
 608 #define R_SCD_WDOG_CFG              0x0000000010
 609
 610 #define A_SCD_WDOG_INIT_0           0x0010020050
 611 #define A_SCD_WDOG_CNT_0            0x0010020058
 612 #define A_SCD_WDOG_CFG_0            0x0010020060
 613
 614 #define A_SCD_WDOG_INIT_1           0x0010020150
 615 #define A_SCD_WDOG_CNT_1            0x0010020158
 616 #define A_SCD_WDOG_CFG_1            0x0010020160
 617
 618 /*
 619  * Generic timers
 620  */
 621
 622 #define A_SCD_TIMER_0               0x0010020070
 623 #define A_SCD_TIMER_1               0x0010020078
 624 #define A_SCD_TIMER_2               0x0010020170
 625 #define A_SCD_TIMER_3               0x0010020178
 626 #define SCD_NUM_TIMERS              4
 627 #define A_SCD_TIMER_BASE(w)         (A_SCD_TIMER_0+0x08*((w)&1)+0x100*(((w)&2)>>1))
 628 #define A_SCD_TIMER_REGISTER(w,r)   (A_SCD_TIMER_BASE(w) + (r))
 629
 630 #define R_SCD_TIMER_INIT            0x0000000000
 631 #define R_SCD_TIMER_CNT             0x0000000010
 632 #define R_SCD_TIMER_CFG             0x0000000020
 633
 634 #define A_SCD_TIMER_INIT_0          0x0010020070
 635 #define A_SCD_TIMER_CNT_0           0x0010020080
 636 #define A_SCD_TIMER_CFG_0           0x0010020090
 637
 638 #define A_SCD_TIMER_INIT_1          0x0010020078
 639 #define A_SCD_TIMER_CNT_1           0x0010020088
 640 #define A_SCD_TIMER_CFG_1           0x0010020098
 641
 642 #define A_SCD_TIMER_INIT_2          0x0010020170
 643 #define A_SCD_TIMER_CNT_2           0x0010020180
 644 #define A_SCD_TIMER_CFG_2           0x0010020190
 645
 646 #define A_SCD_TIMER_INIT_3          0x0010020178
 647 #define A_SCD_TIMER_CNT_3           0x0010020188
 648 #define A_SCD_TIMER_CFG_3           0x0010020198
 649
 650 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
 651 #define A_SCD_SCRATCH              0x0010020C10
 652 #endif /* 1250 PASS2 || 112x PASS1 */
 653
 654 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 655 #define A_SCD_ZBBUS_CYCLE_COUNT    0x0010030000
 656 #define A_SCD_ZBBUS_CYCLE_CP0      0x0010020C00
 657 #define A_SCD_ZBBUS_CYCLE_CP1      0x0010020C08
 658 #endif
 659
 660 /*  *********************************************************************
 661     * System Control Registers
 662     ********************************************************************* */
 663
 664 #define A_SCD_SYSTEM_REVISION       0x0010020000
 665 #define A_SCD_SYSTEM_CFG            0x0010020008
 666 #define A_SCD_SYSTEM_MANUF          0x0010038000
 667
 668 /*  *********************************************************************
 669     * System Address Trap Registers
 670     ********************************************************************* */
 671
 672 #define A_ADDR_TRAP_INDEX           0x00100200B0
 673 #define A_ADDR_TRAP_REG             0x00100200B8
 674 #define A_ADDR_TRAP_UP_0            0x0010020400
 675 #define A_ADDR_TRAP_UP_1            0x0010020408
 676 #define A_ADDR_TRAP_UP_2            0x0010020410
 677 #define A_ADDR_TRAP_UP_3            0x0010020418
 678 #define A_ADDR_TRAP_DOWN_0          0x0010020420
 679 #define A_ADDR_TRAP_DOWN_1          0x0010020428
 680 #define A_ADDR_TRAP_DOWN_2          0x0010020430
 681 #define A_ADDR_TRAP_DOWN_3          0x0010020438
 682 #define A_ADDR_TRAP_CFG_0           0x0010020440
 683 #define A_ADDR_TRAP_CFG_1           0x0010020448
 684 #define A_ADDR_TRAP_CFG_2           0x0010020450
 685 #define A_ADDR_TRAP_CFG_3           0x0010020458
 686 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 687 #define A_ADDR_TRAP_REG_DEBUG       0x0010020460
 688 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */
 689
 690 #define ADDR_TRAP_SPACING 8
 691 #define NUM_ADDR_TRAP 4
 692 #define A_ADDR_TRAP_UP(n) (A_ADDR_TRAP_UP_0 + ((n) * ADDR_TRAP_SPACING))
 693 #define A_ADDR_TRAP_DOWN(n) (A_ADDR_TRAP_DOWN_0 + ((n) * ADDR_TRAP_SPACING))
 694 #define A_ADDR_TRAP_CFG(n) (A_ADDR_TRAP_CFG_0 + ((n) * ADDR_TRAP_SPACING))
 695
 696
 697 /*  *********************************************************************
 698     * System Interrupt Mapper Registers
 699     ********************************************************************* */
 700
 701 #define A_IMR_CPU0_BASE                 0x0010020000
 702 #define A_IMR_CPU1_BASE                 0x0010022000
 703 #define IMR_REGISTER_SPACING            0x2000
 704 #define IMR_REGISTER_SPACING_SHIFT      13
 705
 706 #define A_IMR_MAPPER(cpu) (A_IMR_CPU0_BASE+(cpu)*IMR_REGISTER_SPACING)
 707 #define A_IMR_REGISTER(cpu,reg) (A_IMR_MAPPER(cpu)+(reg))
 708
 709 #define R_IMR_INTERRUPT_DIAG            0x0010
 710 #define R_IMR_INTERRUPT_LDT             0x0018
 711 #define R_IMR_INTERRUPT_MASK            0x0028
 712 #define R_IMR_INTERRUPT_TRACE           0x0038
 713 #define R_IMR_INTERRUPT_SOURCE_STATUS   0x0040
 714 #define R_IMR_LDT_INTERRUPT_SET         0x0048
 715 #define R_IMR_LDT_INTERRUPT             0x0018
 716 #define R_IMR_LDT_INTERRUPT_CLR         0x0020
 717 #define R_IMR_MAILBOX_CPU               0x00c0
 718 #define R_IMR_ALIAS_MAILBOX_CPU         0x1000
 719 #define R_IMR_MAILBOX_SET_CPU           0x00C8
 720 #define R_IMR_ALIAS_MAILBOX_SET_CPU     0x1008
 721 #define R_IMR_MAILBOX_CLR_CPU           0x00D0
 722 #define R_IMR_INTERRUPT_STATUS_BASE     0x0100
 723 #define R_IMR_INTERRUPT_STATUS_COUNT    7
 724 #define R_IMR_INTERRUPT_MAP_BASE        0x0200
 725 #define R_IMR_INTERRUPT_MAP_COUNT       64
 726
 727 /*
 728  * these macros work together to build the address of a mailbox
 729  * register, e.g., A_MAILBOX_REGISTER(R_IMR_MAILBOX_SET_CPU,1)
 730  * for mbox_0_set_cpu2 returns 0x00100240C8
 731  */
 732 #define A_MAILBOX_REGISTER(reg,cpu) \
 733     (A_IMR_CPU0_BASE + (cpu * IMR_REGISTER_SPACING) + reg)
 734
 735 /*  *********************************************************************
 736     * System Performance Counter Registers
 737     ********************************************************************* */
 738
 739 #define A_SCD_PERF_CNT_CFG          0x00100204C0
 740 #define A_SCD_PERF_CNT_0            0x00100204D0
 741 #define A_SCD_PERF_CNT_1            0x00100204D8
 742 #define A_SCD_PERF_CNT_2            0x00100204E0
 743 #define A_SCD_PERF_CNT_3            0x00100204E8
 744
 745 #define SCD_NUM_PERF_CNT 4
 746 #define SCD_PERF_CNT_SPACING 8
 747 #define A_SCD_PERF_CNT(n) (A_SCD_PERF_CNT_0+(n*SCD_PERF_CNT_SPACING))
 748
 749 /*  *********************************************************************
 750     * System Bus Watcher Registers
 751     ********************************************************************* */
 752
 753 #define A_SCD_BUS_ERR_STATUS        0x0010020880
 754 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
 755 #define A_SCD_BUS_ERR_STATUS_DEBUG  0x00100208D0
 756 #define A_BUS_ERR_STATUS_DEBUG  0x00100208D0
 757 #endif /* 1250 PASS2 || 112x PASS1 */
 758 #define A_BUS_ERR_DATA_0            0x00100208A0
 759 #define A_BUS_ERR_DATA_1            0x00100208A8
 760 #define A_BUS_ERR_DATA_2            0x00100208B0
 761 #define A_BUS_ERR_DATA_3            0x00100208B8
 762 #define A_BUS_L2_ERRORS             0x00100208C0
 763 #define A_BUS_MEM_IO_ERRORS         0x00100208C8
 764
 765 /*  *********************************************************************
 766     * System Debug Controller Registers
 767     ********************************************************************* */
 768
 769 #define A_SCD_JTAG_BASE             0x0010000000
 770
 771 /*  *********************************************************************
 772     * System Trace Buffer Registers
 773     ********************************************************************* */
 774
 775 #define A_SCD_TRACE_CFG             0x0010020A00
 776 #define A_SCD_TRACE_READ            0x0010020A08
 777 #define A_SCD_TRACE_EVENT_0         0x0010020A20
 778 #define A_SCD_TRACE_EVENT_1         0x0010020A28
 779 #define A_SCD_TRACE_EVENT_2         0x0010020A30
 780 #define A_SCD_TRACE_EVENT_3         0x0010020A38
 781 #define A_SCD_TRACE_SEQUENCE_0      0x0010020A40
 782 #define A_SCD_TRACE_SEQUENCE_1      0x0010020A48
 783 #define A_SCD_TRACE_SEQUENCE_2      0x0010020A50
 784 #define A_SCD_TRACE_SEQUENCE_3      0x0010020A58
 785 #define A_SCD_TRACE_EVENT_4         0x0010020A60
 786 #define A_SCD_TRACE_EVENT_5         0x0010020A68
 787 #define A_SCD_TRACE_EVENT_6         0x0010020A70
 788 #define A_SCD_TRACE_EVENT_7         0x0010020A78
 789 #define A_SCD_TRACE_SEQUENCE_4      0x0010020A80
 790 #define A_SCD_TRACE_SEQUENCE_5      0x0010020A88
 791 #define A_SCD_TRACE_SEQUENCE_6      0x0010020A90
 792 #define A_SCD_TRACE_SEQUENCE_7      0x0010020A98
 793
 794 #define TRACE_REGISTER_SPACING 8
 795 #define TRACE_NUM_REGISTERS    8
 796 #define A_SCD_TRACE_EVENT(n) (((n) & 4) ? \
 797    (A_SCD_TRACE_EVENT_4 + (((n) & 3) * TRACE_REGISTER_SPACING)) : \
 798    (A_SCD_TRACE_EVENT_0 + ((n) * TRACE_REGISTER_SPACING)))
 799 #define A_SCD_TRACE_SEQUENCE(n) (((n) & 4) ? \
 800    (A_SCD_TRACE_SEQUENCE_4 + (((n) & 3) * TRACE_REGISTER_SPACING)) : \
 801    (A_SCD_TRACE_SEQUENCE_0 + ((n) * TRACE_REGISTER_SPACING)))
 802
 803 /*  *********************************************************************
 804     * System Generic DMA Registers
 805     ********************************************************************* */
 806
 807 #define A_DM_0                      0x0010020B00
 808 #define A_DM_1                      0x0010020B20
 809 #define A_DM_2                      0x0010020B40
 810 #define A_DM_3                      0x0010020B60
 811 #define DM_REGISTER_SPACING         0x20
 812 #define DM_NUM_CHANNELS             4
 813 #define A_DM_BASE(idx) (A_DM_0 + ((idx) * DM_REGISTER_SPACING))
 814 #define A_DM_REGISTER(idx,reg) (A_DM_BASE(idx) + (reg))
 815
 816 #define R_DM_DSCR_BASE              0x0000000000
 817 #define R_DM_DSCR_COUNT             0x0000000008
 818 #define R_DM_CUR_DSCR_ADDR          0x0000000010
 819 #define R_DM_DSCR_BASE_DEBUG        0x0000000018
 820
 821 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
 822 #define A_DM_PARTIAL_0              0x0010020ba0
 823 #define A_DM_PARTIAL_1              0x0010020ba8
 824 #define A_DM_PARTIAL_2              0x0010020bb0
 825 #define A_DM_PARTIAL_3              0x0010020bb8
 826 #define DM_PARTIAL_REGISTER_SPACING 0x8
 827 #define A_DM_PARTIAL(idx)           (A_DM_PARTIAL_0 + ((idx) * DM_PARTIAL_REGISTER_SPACING))
 828 #endif /* 1250 PASS3 || 112x PASS1 */
 829
 830 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
 831 #define A_DM_CRC_0                  0x0010020b80
 832 #define A_DM_CRC_1                  0x0010020b90
 833 #define DM_CRC_REGISTER_SPACING     0x10
 834 #define DM_CRC_NUM_CHANNELS         2
 835 #define A_DM_CRC_BASE(idx)          (A_DM_CRC_0 + ((idx) * DM_CRC_REGISTER_SPACING))
 836 #define A_DM_CRC_REGISTER(idx,reg)  (A_DM_CRC_BASE(idx) + (reg))
 837
 838 #define R_CRC_DEF_0                 0x00
 839 #define R_CTCP_DEF_0                0x08
 840 #endif /* 1250 PASS3 || 112x PASS1 */
 841
 842 /*  *********************************************************************
 843     *  Physical Address Map
 844     ********************************************************************* */
 845
 846 #if SIBYTE_HDR_FEATURE_1250_112x
 847 #define A_PHYS_MEMORY_0                 _SB_MAKE64(0x0000000000)
 848 #define A_PHYS_MEMORY_SIZE              _SB_MAKE64((256*1024*1024))
 849 #define A_PHYS_SYSTEM_CTL               _SB_MAKE64(0x0010000000)
 850 #define A_PHYS_IO_SYSTEM                _SB_MAKE64(0x0010060000)
 851 #define A_PHYS_GENBUS                   _SB_MAKE64(0x0010090000)
 852 #define A_PHYS_GENBUS_END               _SB_MAKE64(0x0040000000)
 853 #define A_PHYS_LDTPCI_IO_MATCH_BYTES_32 _SB_MAKE64(0x0040000000)
 854 #define A_PHYS_LDTPCI_IO_MATCH_BITS_32  _SB_MAKE64(0x0060000000)
 855 #define A_PHYS_MEMORY_1                 _SB_MAKE64(0x0080000000)
 856 #define A_PHYS_MEMORY_2                 _SB_MAKE64(0x0090000000)
 857 #define A_PHYS_MEMORY_3                 _SB_MAKE64(0x00C0000000)
 858 #define A_PHYS_L2_CACHE_TEST            _SB_MAKE64(0x00D0000000)
 859 #define A_PHYS_LDT_SPECIAL_MATCH_BYTES  _SB_MAKE64(0x00D8000000)
 860 #define A_PHYS_LDTPCI_IO_MATCH_BYTES    _SB_MAKE64(0x00DC000000)
 861 #define A_PHYS_LDTPCI_CFG_MATCH_BYTES   _SB_MAKE64(0x00DE000000)
 862 #define A_PHYS_LDT_SPECIAL_MATCH_BITS   _SB_MAKE64(0x00F8000000)
 863 #define A_PHYS_LDTPCI_IO_MATCH_BITS     _SB_MAKE64(0x00FC000000)
 864 #define A_PHYS_LDTPCI_CFG_MATCH_BITS    _SB_MAKE64(0x00FE000000)
 865 #define A_PHYS_MEMORY_EXP               _SB_MAKE64(0x0100000000)
 866 #define A_PHYS_MEMORY_EXP_SIZE          _SB_MAKE64((508*1024*1024*1024))
 867 #define A_PHYS_LDT_EXP                  _SB_MAKE64(0x8000000000)
 868 #define A_PHYS_PCI_FULLACCESS_BYTES     _SB_MAKE64(0xF000000000)
 869 #define A_PHYS_PCI_FULLACCESS_BITS      _SB_MAKE64(0xF100000000)
 870 #define A_PHYS_RESERVED                 _SB_MAKE64(0xF200000000)
 871 #define A_PHYS_RESERVED_SPECIAL_LDT     _SB_MAKE64(0xFD00000000)
 872
 873 #define A_PHYS_L2CACHE_WAY_SIZE         _SB_MAKE64(0x0000020000)
 874 #define PHYS_L2CACHE_NUM_WAYS           4
 875 #define A_PHYS_L2CACHE_TOTAL_SIZE       _SB_MAKE64(0x0000080000)
 876 #define A_PHYS_L2CACHE_WAY0             _SB_MAKE64(0x00D0180000)
 877 #define A_PHYS_L2CACHE_WAY1             _SB_MAKE64(0x00D01A0000)
 878 #define A_PHYS_L2CACHE_WAY2             _SB_MAKE64(0x00D01C0000)
 879 #define A_PHYS_L2CACHE_WAY3             _SB_MAKE64(0x00D01E0000)
 880 #endif
 881
 882
 883 #endif