1 #ifndef _ASM_M32R_BITOPS_H
2 #define _ASM_M32R_BITOPS_H
5 * linux/include/asm-m32r/bitops.h
7 * Copyright 1992, Linus Torvalds.
10 * Copyright (C) 2001, 2002 Hitoshi Yamamoto
11 * Copyright (C) 2004 Hirokazu Takata <takata at linux-m32r.org>
14 #ifndef _LINUX_BITOPS_H
15 #error only <linux/bitops.h> can be included directly
18 #include <linux/compiler.h>
19 #include <asm/assembler.h>
20 #include <asm/system.h>
21 #include <asm/byteorder.h>
22 #include <asm/types.h>
25 * These have to be done with inline assembly: that way the bit-setting
26 * is guaranteed to be atomic. All bit operations return 0 if the bit
27 * was cleared before the operation and != 0 if it was not.
29 * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
33 * set_bit - Atomically set a bit in memory
35 * @addr: the address to start counting from
37 * This function is atomic and may not be reordered. See __set_bit()
38 * if you do not require the atomic guarantees.
39 * Note that @nr may be almost arbitrarily large; this function is not
40 * restricted to acting on a single-word quantity.
42 static __inline__ void set_bit(int nr, volatile void * addr)
45 volatile __u32 *a = addr;
50 mask = (1 << (nr & 0x1F));
52 local_irq_save(flags);
53 __asm__ __volatile__ (
54 DCACHE_CLEAR("%0", "r6", "%1")
55 M32R_LOCK" %0, @%1; \n\t"
57 M32R_UNLOCK" %0, @%1; \n\t"
61 #ifdef CONFIG_CHIP_M32700_TS1
63 #endif /* CONFIG_CHIP_M32700_TS1 */
65 local_irq_restore(flags);
69 * clear_bit - Clears a bit in memory
71 * @addr: Address to start counting from
73 * clear_bit() is atomic and may not be reordered. However, it does
74 * not contain a memory barrier, so if it is used for locking purposes,
75 * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
76 * in order to ensure changes are visible on other processors.
78 static __inline__ void clear_bit(int nr, volatile void * addr)
81 volatile __u32 *a = addr;
86 mask = (1 << (nr & 0x1F));
88 local_irq_save(flags);
90 __asm__ __volatile__ (
91 DCACHE_CLEAR("%0", "r6", "%1")
92 M32R_LOCK" %0, @%1; \n\t"
94 M32R_UNLOCK" %0, @%1; \n\t"
96 : "r" (a), "r" (~mask)
98 #ifdef CONFIG_CHIP_M32700_TS1
100 #endif /* CONFIG_CHIP_M32700_TS1 */
102 local_irq_restore(flags);
105 #define smp_mb__before_clear_bit() barrier()
106 #define smp_mb__after_clear_bit() barrier()
109 * change_bit - Toggle a bit in memory
111 * @addr: Address to start counting from
113 * change_bit() is atomic and may not be reordered.
114 * Note that @nr may be almost arbitrarily large; this function is not
115 * restricted to acting on a single-word quantity.
117 static __inline__ void change_bit(int nr, volatile void * addr)
120 volatile __u32 *a = addr;
125 mask = (1 << (nr & 0x1F));
127 local_irq_save(flags);
128 __asm__ __volatile__ (
129 DCACHE_CLEAR("%0", "r6", "%1")
130 M32R_LOCK" %0, @%1; \n\t"
132 M32R_UNLOCK" %0, @%1; \n\t"
134 : "r" (a), "r" (mask)
136 #ifdef CONFIG_CHIP_M32700_TS1
138 #endif /* CONFIG_CHIP_M32700_TS1 */
140 local_irq_restore(flags);
144 * test_and_set_bit - Set a bit and return its old value
146 * @addr: Address to count from
148 * This operation is atomic and cannot be reordered.
149 * It also implies a memory barrier.
151 static __inline__ int test_and_set_bit(int nr, volatile void * addr)
154 volatile __u32 *a = addr;
159 mask = (1 << (nr & 0x1F));
161 local_irq_save(flags);
162 __asm__ __volatile__ (
163 DCACHE_CLEAR("%0", "%1", "%2")
164 M32R_LOCK" %0, @%2; \n\t"
168 M32R_UNLOCK" %1, @%2; \n\t"
169 : "=&r" (oldbit), "=&r" (tmp)
170 : "r" (a), "r" (mask)
173 local_irq_restore(flags);
175 return (oldbit != 0);
179 * test_and_clear_bit - Clear a bit and return its old value
181 * @addr: Address to count from
183 * This operation is atomic and cannot be reordered.
184 * It also implies a memory barrier.
186 static __inline__ int test_and_clear_bit(int nr, volatile void * addr)
189 volatile __u32 *a = addr;
194 mask = (1 << (nr & 0x1F));
196 local_irq_save(flags);
198 __asm__ __volatile__ (
199 DCACHE_CLEAR("%0", "%1", "%3")
200 M32R_LOCK" %0, @%3; \n\t"
205 M32R_UNLOCK" %1, @%3; \n\t"
206 : "=&r" (oldbit), "=&r" (tmp), "+r" (mask)
210 local_irq_restore(flags);
212 return (oldbit != 0);
216 * test_and_change_bit - Change a bit and return its old value
218 * @addr: Address to count from
220 * This operation is atomic and cannot be reordered.
221 * It also implies a memory barrier.
223 static __inline__ int test_and_change_bit(int nr, volatile void * addr)
226 volatile __u32 *a = addr;
231 mask = (1 << (nr & 0x1F));
233 local_irq_save(flags);
234 __asm__ __volatile__ (
235 DCACHE_CLEAR("%0", "%1", "%2")
236 M32R_LOCK" %0, @%2; \n\t"
240 M32R_UNLOCK" %1, @%2; \n\t"
241 : "=&r" (oldbit), "=&r" (tmp)
242 : "r" (a), "r" (mask)
245 local_irq_restore(flags);
247 return (oldbit != 0);
250 #include <asm-generic/bitops/non-atomic.h>
251 #include <asm-generic/bitops/ffz.h>
252 #include <asm-generic/bitops/__ffs.h>
253 #include <asm-generic/bitops/fls.h>
254 #include <asm-generic/bitops/fls64.h>
258 #include <asm-generic/bitops/sched.h>
259 #include <asm-generic/bitops/find.h>
260 #include <asm-generic/bitops/ffs.h>
261 #include <asm-generic/bitops/hweight.h>
262 #include <asm-generic/bitops/lock.h>
264 #endif /* __KERNEL__ */
268 #include <asm-generic/bitops/ext2-non-atomic.h>
269 #include <asm-generic/bitops/ext2-atomic.h>
270 #include <asm-generic/bitops/minix.h>
272 #endif /* __KERNEL__ */
274 #endif /* _ASM_M32R_BITOPS_H */