4 #include <linux/config.h>
5 #include <linux/kernel.h>
6 #include <asm/segment.h>
7 #include <asm/cpufeature.h>
8 #include <linux/bitops.h> /* for LOCK_PREFIX */
12 struct task_struct; /* one of the stranger aspects of C forward declarations.. */
13 extern struct task_struct * FASTCALL(__switch_to(struct task_struct *prev, struct task_struct *next));
15 #define switch_to(prev,next,last) do { \
16 unsigned long esi,edi; \
17 asm volatile("pushl %%ebp\n\t" \
18 "movl %%esp,%0\n\t" /* save ESP */ \
19 "movl %5,%%esp\n\t" /* restore ESP */ \
20 "movl $1f,%1\n\t" /* save EIP */ \
21 "pushl %6\n\t" /* restore EIP */ \
25 :"=m" (prev->thread.esp),"=m" (prev->thread.eip), \
26 "=a" (last),"=S" (esi),"=D" (edi) \
27 :"m" (next->thread.esp),"m" (next->thread.eip), \
28 "2" (prev), "d" (next)); \
31 #define _set_base(addr,base) do { unsigned long __pr; \
32 __asm__ __volatile__ ("movw %%dx,%1\n\t" \
33 "rorl $16,%%edx\n\t" \
43 #define _set_limit(addr,limit) do { unsigned long __lr; \
44 __asm__ __volatile__ ("movw %%dx,%1\n\t" \
45 "rorl $16,%%edx\n\t" \
47 "andb $0xf0,%%dh\n\t" \
56 #define set_base(ldt,base) _set_base( ((char *)&(ldt)) , (base) )
57 #define set_limit(ldt,limit) _set_limit( ((char *)&(ldt)) , ((limit)-1)>>12 )
59 static inline unsigned long _get_base(char * addr)
62 __asm__("movb %3,%%dh\n\t"
73 #define get_base(ldt) _get_base( ((char *)&(ldt)) )
76 * Load a segment. Fall back on loading the zero
77 * segment if something goes wrong..
79 #define loadsegment(seg,value) \
82 "mov %0,%%" #seg "\n" \
84 ".section .fixup,\"ax\"\n" \
87 "popl %%" #seg "\n\t" \
90 ".section __ex_table,\"a\"\n\t" \
97 * Save a segment register away
99 #define savesegment(seg, value) \
100 asm volatile("mov %%" #seg ",%0":"=rm" (value))
103 * Clear and set 'TS' bit respectively
105 #define clts() __asm__ __volatile__ ("clts")
106 #define read_cr0() ({ \
107 unsigned int __dummy; \
108 __asm__ __volatile__( \
109 "movl %%cr0,%0\n\t" \
113 #define write_cr0(x) \
114 __asm__ __volatile__("movl %0,%%cr0": :"r" (x));
116 #define read_cr2() ({ \
117 unsigned int __dummy; \
118 __asm__ __volatile__( \
119 "movl %%cr2,%0\n\t" \
123 #define write_cr2(x) \
124 __asm__ __volatile__("movl %0,%%cr2": :"r" (x));
126 #define read_cr3() ({ \
127 unsigned int __dummy; \
129 "movl %%cr3,%0\n\t" \
133 #define write_cr3(x) \
134 __asm__ __volatile__("movl %0,%%cr3": :"r" (x));
136 #define read_cr4() ({ \
137 unsigned int __dummy; \
139 "movl %%cr4,%0\n\t" \
144 #define read_cr4_safe() ({ \
145 unsigned int __dummy; \
146 /* This could fault if %cr4 does not exist */ \
147 __asm__("1: movl %%cr4, %0 \n" \
149 ".section __ex_table,\"a\" \n" \
152 : "=r" (__dummy): "0" (0)); \
156 #define write_cr4(x) \
157 __asm__ __volatile__("movl %0,%%cr4": :"r" (x));
158 #define stts() write_cr0(8 | read_cr0())
160 #endif /* __KERNEL__ */
163 __asm__ __volatile__ ("wbinvd": : :"memory");
165 static inline unsigned long get_limit(unsigned long segment)
167 unsigned long __limit;
169 :"=r" (__limit):"r" (segment));
173 #define nop() __asm__ __volatile__ ("nop")
175 #define xchg(ptr,v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v),(ptr),sizeof(*(ptr))))
177 #define tas(ptr) (xchg((ptr),1))
179 struct __xchg_dummy { unsigned long a[100]; };
180 #define __xg(x) ((struct __xchg_dummy *)(x))
183 #ifdef CONFIG_X86_CMPXCHG64
186 * The semantics of XCHGCMP8B are a bit strange, this is why
187 * there is a loop and the loading of %%eax and %%edx has to
188 * be inside. This inlines well in most cases, the cached
189 * cost is around ~38 cycles. (in the future we might want
190 * to do an SIMD/3DNOW!/MMX/FPU 64-bit store here, but that
191 * might have an implicit FPU-save as a cost, so it's not
192 * clear which path to go.)
194 * cmpxchg8b must be used with the lock prefix here to allow
195 * the instruction to be executed atomically, see page 3-102
196 * of the instruction set reference 24319102.pdf. We need
197 * the reader side to see the coherent 64bit value.
199 static inline void __set_64bit (unsigned long long * ptr,
200 unsigned int low, unsigned int high)
202 __asm__ __volatile__ (
204 "movl (%0), %%eax\n\t"
205 "movl 4(%0), %%edx\n\t"
206 "lock cmpxchg8b (%0)\n\t"
212 : "ax","dx","memory");
215 static inline void __set_64bit_constant (unsigned long long *ptr,
216 unsigned long long value)
218 __set_64bit(ptr,(unsigned int)(value), (unsigned int)((value)>>32ULL));
220 #define ll_low(x) *(((unsigned int*)&(x))+0)
221 #define ll_high(x) *(((unsigned int*)&(x))+1)
223 static inline void __set_64bit_var (unsigned long long *ptr,
224 unsigned long long value)
226 __set_64bit(ptr,ll_low(value), ll_high(value));
229 #define set_64bit(ptr,value) \
230 (__builtin_constant_p(value) ? \
231 __set_64bit_constant(ptr, value) : \
232 __set_64bit_var(ptr, value) )
234 #define _set_64bit(ptr,value) \
235 (__builtin_constant_p(value) ? \
236 __set_64bit(ptr, (unsigned int)(value), (unsigned int)((value)>>32ULL) ) : \
237 __set_64bit(ptr, ll_low(value), ll_high(value)) )
242 * Note: no "lock" prefix even on SMP: xchg always implies lock anyway
243 * Note 2: xchg has side effect, so that attribute volatile is necessary,
244 * but generally the primitive is invalid, *ptr is output argument. --ANK
246 static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
250 __asm__ __volatile__("xchgb %b0,%1"
252 :"m" (*__xg(ptr)), "0" (x)
256 __asm__ __volatile__("xchgw %w0,%1"
258 :"m" (*__xg(ptr)), "0" (x)
262 __asm__ __volatile__("xchgl %0,%1"
264 :"m" (*__xg(ptr)), "0" (x)
272 * Atomic compare and exchange. Compare OLD with MEM, if identical,
273 * store NEW in MEM. Return the initial value in MEM. Success is
274 * indicated by comparing RETURN with OLD.
277 #ifdef CONFIG_X86_CMPXCHG
278 #define __HAVE_ARCH_CMPXCHG 1
279 #define cmpxchg(ptr,o,n)\
280 ((__typeof__(*(ptr)))__cmpxchg((ptr),(unsigned long)(o),\
281 (unsigned long)(n),sizeof(*(ptr))))
284 static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
285 unsigned long new, int size)
290 __asm__ __volatile__(LOCK_PREFIX "cmpxchgb %b1,%2"
292 : "q"(new), "m"(*__xg(ptr)), "0"(old)
296 __asm__ __volatile__(LOCK_PREFIX "cmpxchgw %w1,%2"
298 : "r"(new), "m"(*__xg(ptr)), "0"(old)
302 __asm__ __volatile__(LOCK_PREFIX "cmpxchgl %1,%2"
304 : "r"(new), "m"(*__xg(ptr)), "0"(old)
311 #ifndef CONFIG_X86_CMPXCHG
313 * Building a kernel capable running on 80386. It may be necessary to
314 * simulate the cmpxchg on the 80386 CPU. For that purpose we define
315 * a function for each of the sizes we support.
318 extern unsigned long cmpxchg_386_u8(volatile void *, u8, u8);
319 extern unsigned long cmpxchg_386_u16(volatile void *, u16, u16);
320 extern unsigned long cmpxchg_386_u32(volatile void *, u32, u32);
322 static inline unsigned long cmpxchg_386(volatile void *ptr, unsigned long old,
323 unsigned long new, int size)
327 return cmpxchg_386_u8(ptr, old, new);
329 return cmpxchg_386_u16(ptr, old, new);
331 return cmpxchg_386_u32(ptr, old, new);
336 #define cmpxchg(ptr,o,n) \
338 __typeof__(*(ptr)) __ret; \
339 if (likely(boot_cpu_data.x86 > 3)) \
340 __ret = __cmpxchg((ptr), (unsigned long)(o), \
341 (unsigned long)(n), sizeof(*(ptr))); \
343 __ret = cmpxchg_386((ptr), (unsigned long)(o), \
344 (unsigned long)(n), sizeof(*(ptr))); \
349 #ifdef CONFIG_X86_CMPXCHG64
351 static inline unsigned long long __cmpxchg64(volatile void *ptr, unsigned long long old,
352 unsigned long long new)
354 unsigned long long prev;
355 __asm__ __volatile__(LOCK_PREFIX "cmpxchg8b %3"
357 : "b"((unsigned long)new),
358 "c"((unsigned long)(new >> 32)),
365 #define cmpxchg64(ptr,o,n)\
366 ((__typeof__(*(ptr)))__cmpxchg64((ptr),(unsigned long long)(o),\
367 (unsigned long long)(n)))
373 __u8 *instr; /* original instruction */
375 __u8 cpuid; /* cpuid bit set for replacement */
376 __u8 instrlen; /* length of original instruction */
377 __u8 replacementlen; /* length of new instruction, <= instrlen */
383 * Alternative instructions for different CPU types or capabilities.
385 * This allows to use optimized instructions even on generic binary
388 * length of oldinstr must be longer or equal the length of newinstr
389 * It can be padded with nops as needed.
391 * For non barrier like inlines please define new variants
392 * without volatile and memory clobber.
394 #define alternative(oldinstr, newinstr, feature) \
395 asm volatile ("661:\n\t" oldinstr "\n662:\n" \
396 ".section .altinstructions,\"a\"\n" \
398 " .long 661b\n" /* label */ \
399 " .long 663f\n" /* new instruction */ \
400 " .byte %c0\n" /* feature bit */ \
401 " .byte 662b-661b\n" /* sourcelen */ \
402 " .byte 664f-663f\n" /* replacementlen */ \
404 ".section .altinstr_replacement,\"ax\"\n" \
405 "663:\n\t" newinstr "\n664:\n" /* replacement */ \
406 ".previous" :: "i" (feature) : "memory")
409 * Alternative inline assembly with input.
412 * No memory clobber here.
413 * Argument numbers start with 1.
414 * Best is to use constraints that are fixed size (like (%1) ... "r")
415 * If you use variable sized constraints like "m" or "g" in the
416 * replacement maake sure to pad to the worst case length.
418 #define alternative_input(oldinstr, newinstr, feature, input...) \
419 asm volatile ("661:\n\t" oldinstr "\n662:\n" \
420 ".section .altinstructions,\"a\"\n" \
422 " .long 661b\n" /* label */ \
423 " .long 663f\n" /* new instruction */ \
424 " .byte %c0\n" /* feature bit */ \
425 " .byte 662b-661b\n" /* sourcelen */ \
426 " .byte 664f-663f\n" /* replacementlen */ \
428 ".section .altinstr_replacement,\"ax\"\n" \
429 "663:\n\t" newinstr "\n664:\n" /* replacement */ \
430 ".previous" :: "i" (feature), ##input)
433 * Force strict CPU ordering.
434 * And yes, this is required on UP too when we're talking
437 * For now, "wmb()" doesn't actually do anything, as all
438 * Intel CPU's follow what Intel calls a *Processor Order*,
439 * in which all writes are seen in the program order even
442 * I expect future Intel CPU's to have a weaker ordering,
443 * but I'd also expect them to finally get their act together
444 * and add some real memory barriers if so.
446 * Some non intel clones support out of order store. wmb() ceases to be a
452 * Actually only lfence would be needed for mb() because all stores done
453 * by the kernel should be already ordered. But keep a full barrier for now.
456 #define mb() alternative("lock; addl $0,0(%%esp)", "mfence", X86_FEATURE_XMM2)
457 #define rmb() alternative("lock; addl $0,0(%%esp)", "lfence", X86_FEATURE_XMM2)
460 * read_barrier_depends - Flush all pending reads that subsequents reads
463 * No data-dependent reads from memory-like regions are ever reordered
464 * over this barrier. All reads preceding this primitive are guaranteed
465 * to access memory (but not necessarily other CPUs' caches) before any
466 * reads following this primitive that depend on the data return by
467 * any of the preceding reads. This primitive is much lighter weight than
468 * rmb() on most CPUs, and is never heavier weight than is
471 * These ordering constraints are respected by both the local CPU
474 * Ordering is not guaranteed by anything other than these primitives,
475 * not even by data dependencies. See the documentation for
476 * memory_barrier() for examples and URLs to more information.
478 * For example, the following code would force ordering (the initial
479 * value of "a" is zero, "b" is one, and "p" is "&a"):
487 * read_barrier_depends();
491 * because the read of "*q" depends on the read of "p" and these
492 * two reads are separated by a read_barrier_depends(). However,
493 * the following code, with the same initial values for "a" and "b":
501 * read_barrier_depends();
505 * does not enforce ordering, since there is no data dependency between
506 * the read of "a" and the read of "b". Therefore, on some CPUs, such
507 * as Alpha, "y" could be set to 3 and "x" to 0. Use rmb()
508 * in cases like thiswhere there are no data dependencies.
511 #define read_barrier_depends() do { } while(0)
513 #ifdef CONFIG_X86_OOSTORE
514 /* Actually there are no OOO store capable CPUs for now that do SSE,
515 but make it already an possibility. */
516 #define wmb() alternative("lock; addl $0,0(%%esp)", "sfence", X86_FEATURE_XMM)
518 #define wmb() __asm__ __volatile__ ("": : :"memory")
522 #define smp_mb() mb()
523 #define smp_rmb() rmb()
524 #define smp_wmb() wmb()
525 #define smp_read_barrier_depends() read_barrier_depends()
526 #define set_mb(var, value) do { xchg(&var, value); } while (0)
528 #define smp_mb() barrier()
529 #define smp_rmb() barrier()
530 #define smp_wmb() barrier()
531 #define smp_read_barrier_depends() do { } while(0)
532 #define set_mb(var, value) do { var = value; barrier(); } while (0)
535 #define set_wmb(var, value) do { var = value; wmb(); } while (0)
537 /* interrupt control.. */
538 #define local_save_flags(x) do { typecheck(unsigned long,x); __asm__ __volatile__("pushfl ; popl %0":"=g" (x): /* no input */); } while (0)
539 #define local_irq_restore(x) do { typecheck(unsigned long,x); __asm__ __volatile__("pushl %0 ; popfl": /* no output */ :"g" (x):"memory", "cc"); } while (0)
540 #define local_irq_disable() __asm__ __volatile__("cli": : :"memory")
541 #define local_irq_enable() __asm__ __volatile__("sti": : :"memory")
542 /* used in the idle loop; sti takes one instruction cycle to complete */
543 #define safe_halt() __asm__ __volatile__("sti; hlt": : :"memory")
544 /* used when interrupts are already enabled or to shutdown the processor */
545 #define halt() __asm__ __volatile__("hlt": : :"memory")
547 #define irqs_disabled() \
549 unsigned long flags; \
550 local_save_flags(flags); \
554 /* For spinlocks etc */
555 #define local_irq_save(x) __asm__ __volatile__("pushfl ; popl %0 ; cli":"=g" (x): /* no input */ :"memory")
558 * disable hlt during certain critical i/o operations
560 #define HAVE_DISABLE_HLT
561 void disable_hlt(void);
562 void enable_hlt(void);
564 extern int es7000_plat;
565 void cpu_idle_wait(void);
567 extern unsigned long arch_align_stack(unsigned long sp);