4 #include <linux/config.h>
5 #include <linux/kernel.h>
6 #include <asm/segment.h>
7 #include <asm/cpufeature.h>
8 #include <linux/bitops.h> /* for LOCK_PREFIX */
12 struct task_struct; /* one of the stranger aspects of C forward declarations.. */
13 extern struct task_struct * FASTCALL(__switch_to(struct task_struct *prev, struct task_struct *next));
15 #define switch_to(prev,next,last) do { \
16 unsigned long esi,edi; \
17 asm volatile("pushfl\n\t" \
19 "movl %%esp,%0\n\t" /* save ESP */ \
20 "movl %5,%%esp\n\t" /* restore ESP */ \
21 "movl $1f,%1\n\t" /* save EIP */ \
22 "pushl %6\n\t" /* restore EIP */ \
27 :"=m" (prev->thread.esp),"=m" (prev->thread.eip), \
28 "=a" (last),"=S" (esi),"=D" (edi) \
29 :"m" (next->thread.esp),"m" (next->thread.eip), \
30 "2" (prev), "d" (next)); \
33 #define _set_base(addr,base) do { unsigned long __pr; \
34 __asm__ __volatile__ ("movw %%dx,%1\n\t" \
35 "rorl $16,%%edx\n\t" \
45 #define _set_limit(addr,limit) do { unsigned long __lr; \
46 __asm__ __volatile__ ("movw %%dx,%1\n\t" \
47 "rorl $16,%%edx\n\t" \
49 "andb $0xf0,%%dh\n\t" \
58 #define set_base(ldt,base) _set_base( ((char *)&(ldt)) , (base) )
59 #define set_limit(ldt,limit) _set_limit( ((char *)&(ldt)) , ((limit)-1)>>12 )
61 static inline unsigned long _get_base(char * addr)
64 __asm__("movb %3,%%dh\n\t"
75 #define get_base(ldt) _get_base( ((char *)&(ldt)) )
78 * Load a segment. Fall back on loading the zero
79 * segment if something goes wrong..
81 #define loadsegment(seg,value) \
84 "mov %0,%%" #seg "\n" \
86 ".section .fixup,\"ax\"\n" \
89 "popl %%" #seg "\n\t" \
92 ".section __ex_table,\"a\"\n\t" \
99 * Save a segment register away
101 #define savesegment(seg, value) \
102 asm volatile("mov %%" #seg ",%0":"=rm" (value))
105 * Clear and set 'TS' bit respectively
107 #define clts() __asm__ __volatile__ ("clts")
108 #define read_cr0() ({ \
109 unsigned int __dummy; \
110 __asm__ __volatile__( \
111 "movl %%cr0,%0\n\t" \
115 #define write_cr0(x) \
116 __asm__ __volatile__("movl %0,%%cr0": :"r" (x));
118 #define read_cr2() ({ \
119 unsigned int __dummy; \
120 __asm__ __volatile__( \
121 "movl %%cr2,%0\n\t" \
125 #define write_cr2(x) \
126 __asm__ __volatile__("movl %0,%%cr2": :"r" (x));
128 #define read_cr3() ({ \
129 unsigned int __dummy; \
131 "movl %%cr3,%0\n\t" \
135 #define write_cr3(x) \
136 __asm__ __volatile__("movl %0,%%cr3": :"r" (x));
138 #define read_cr4() ({ \
139 unsigned int __dummy; \
141 "movl %%cr4,%0\n\t" \
145 #define write_cr4(x) \
146 __asm__ __volatile__("movl %0,%%cr4": :"r" (x));
147 #define stts() write_cr0(8 | read_cr0())
149 #endif /* __KERNEL__ */
152 __asm__ __volatile__ ("wbinvd": : :"memory");
154 static inline unsigned long get_limit(unsigned long segment)
156 unsigned long __limit;
158 :"=r" (__limit):"r" (segment));
162 #define nop() __asm__ __volatile__ ("nop")
164 #define xchg(ptr,v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v),(ptr),sizeof(*(ptr))))
166 #define tas(ptr) (xchg((ptr),1))
168 struct __xchg_dummy { unsigned long a[100]; };
169 #define __xg(x) ((struct __xchg_dummy *)(x))
173 * The semantics of XCHGCMP8B are a bit strange, this is why
174 * there is a loop and the loading of %%eax and %%edx has to
175 * be inside. This inlines well in most cases, the cached
176 * cost is around ~38 cycles. (in the future we might want
177 * to do an SIMD/3DNOW!/MMX/FPU 64-bit store here, but that
178 * might have an implicit FPU-save as a cost, so it's not
179 * clear which path to go.)
181 * cmpxchg8b must be used with the lock prefix here to allow
182 * the instruction to be executed atomically, see page 3-102
183 * of the instruction set reference 24319102.pdf. We need
184 * the reader side to see the coherent 64bit value.
186 static inline void __set_64bit (unsigned long long * ptr,
187 unsigned int low, unsigned int high)
189 __asm__ __volatile__ (
191 "movl (%0), %%eax\n\t"
192 "movl 4(%0), %%edx\n\t"
193 "lock cmpxchg8b (%0)\n\t"
199 : "ax","dx","memory");
202 static inline void __set_64bit_constant (unsigned long long *ptr,
203 unsigned long long value)
205 __set_64bit(ptr,(unsigned int)(value), (unsigned int)((value)>>32ULL));
207 #define ll_low(x) *(((unsigned int*)&(x))+0)
208 #define ll_high(x) *(((unsigned int*)&(x))+1)
210 static inline void __set_64bit_var (unsigned long long *ptr,
211 unsigned long long value)
213 __set_64bit(ptr,ll_low(value), ll_high(value));
216 #define set_64bit(ptr,value) \
217 (__builtin_constant_p(value) ? \
218 __set_64bit_constant(ptr, value) : \
219 __set_64bit_var(ptr, value) )
221 #define _set_64bit(ptr,value) \
222 (__builtin_constant_p(value) ? \
223 __set_64bit(ptr, (unsigned int)(value), (unsigned int)((value)>>32ULL) ) : \
224 __set_64bit(ptr, ll_low(value), ll_high(value)) )
227 * Note: no "lock" prefix even on SMP: xchg always implies lock anyway
228 * Note 2: xchg has side effect, so that attribute volatile is necessary,
229 * but generally the primitive is invalid, *ptr is output argument. --ANK
231 static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
235 __asm__ __volatile__("xchgb %b0,%1"
237 :"m" (*__xg(ptr)), "0" (x)
241 __asm__ __volatile__("xchgw %w0,%1"
243 :"m" (*__xg(ptr)), "0" (x)
247 __asm__ __volatile__("xchgl %0,%1"
249 :"m" (*__xg(ptr)), "0" (x)
257 * Atomic compare and exchange. Compare OLD with MEM, if identical,
258 * store NEW in MEM. Return the initial value in MEM. Success is
259 * indicated by comparing RETURN with OLD.
262 #ifdef CONFIG_X86_CMPXCHG
263 #define __HAVE_ARCH_CMPXCHG 1
266 static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
267 unsigned long new, int size)
272 __asm__ __volatile__(LOCK_PREFIX "cmpxchgb %b1,%2"
274 : "q"(new), "m"(*__xg(ptr)), "0"(old)
278 __asm__ __volatile__(LOCK_PREFIX "cmpxchgw %w1,%2"
280 : "q"(new), "m"(*__xg(ptr)), "0"(old)
284 __asm__ __volatile__(LOCK_PREFIX "cmpxchgl %1,%2"
286 : "q"(new), "m"(*__xg(ptr)), "0"(old)
293 #define cmpxchg(ptr,o,n)\
294 ((__typeof__(*(ptr)))__cmpxchg((ptr),(unsigned long)(o),\
295 (unsigned long)(n),sizeof(*(ptr))))
299 __u8 *instr; /* original instruction */
301 __u8 cpuid; /* cpuid bit set for replacement */
302 __u8 instrlen; /* length of original instruction */
303 __u8 replacementlen; /* length of new instruction, <= instrlen */
309 * Alternative instructions for different CPU types or capabilities.
311 * This allows to use optimized instructions even on generic binary
314 * length of oldinstr must be longer or equal the length of newinstr
315 * It can be padded with nops as needed.
317 * For non barrier like inlines please define new variants
318 * without volatile and memory clobber.
320 #define alternative(oldinstr, newinstr, feature) \
321 asm volatile ("661:\n\t" oldinstr "\n662:\n" \
322 ".section .altinstructions,\"a\"\n" \
324 " .long 661b\n" /* label */ \
325 " .long 663f\n" /* new instruction */ \
326 " .byte %c0\n" /* feature bit */ \
327 " .byte 662b-661b\n" /* sourcelen */ \
328 " .byte 664f-663f\n" /* replacementlen */ \
330 ".section .altinstr_replacement,\"ax\"\n" \
331 "663:\n\t" newinstr "\n664:\n" /* replacement */ \
332 ".previous" :: "i" (feature) : "memory")
335 * Alternative inline assembly with input.
338 * No memory clobber here.
339 * Argument numbers start with 1.
340 * Best is to use constraints that are fixed size (like (%1) ... "r")
341 * If you use variable sized constraints like "m" or "g" in the
342 * replacement maake sure to pad to the worst case length.
344 #define alternative_input(oldinstr, newinstr, feature, input...) \
345 asm volatile ("661:\n\t" oldinstr "\n662:\n" \
346 ".section .altinstructions,\"a\"\n" \
348 " .long 661b\n" /* label */ \
349 " .long 663f\n" /* new instruction */ \
350 " .byte %c0\n" /* feature bit */ \
351 " .byte 662b-661b\n" /* sourcelen */ \
352 " .byte 664f-663f\n" /* replacementlen */ \
354 ".section .altinstr_replacement,\"ax\"\n" \
355 "663:\n\t" newinstr "\n664:\n" /* replacement */ \
356 ".previous" :: "i" (feature), ##input)
359 * Force strict CPU ordering.
360 * And yes, this is required on UP too when we're talking
363 * For now, "wmb()" doesn't actually do anything, as all
364 * Intel CPU's follow what Intel calls a *Processor Order*,
365 * in which all writes are seen in the program order even
368 * I expect future Intel CPU's to have a weaker ordering,
369 * but I'd also expect them to finally get their act together
370 * and add some real memory barriers if so.
372 * Some non intel clones support out of order store. wmb() ceases to be a
378 * Actually only lfence would be needed for mb() because all stores done
379 * by the kernel should be already ordered. But keep a full barrier for now.
382 #define mb() alternative("lock; addl $0,0(%%esp)", "mfence", X86_FEATURE_XMM2)
383 #define rmb() alternative("lock; addl $0,0(%%esp)", "lfence", X86_FEATURE_XMM2)
386 * read_barrier_depends - Flush all pending reads that subsequents reads
389 * No data-dependent reads from memory-like regions are ever reordered
390 * over this barrier. All reads preceding this primitive are guaranteed
391 * to access memory (but not necessarily other CPUs' caches) before any
392 * reads following this primitive that depend on the data return by
393 * any of the preceding reads. This primitive is much lighter weight than
394 * rmb() on most CPUs, and is never heavier weight than is
397 * These ordering constraints are respected by both the local CPU
400 * Ordering is not guaranteed by anything other than these primitives,
401 * not even by data dependencies. See the documentation for
402 * memory_barrier() for examples and URLs to more information.
404 * For example, the following code would force ordering (the initial
405 * value of "a" is zero, "b" is one, and "p" is "&a"):
413 * read_barrier_depends();
417 * because the read of "*q" depends on the read of "p" and these
418 * two reads are separated by a read_barrier_depends(). However,
419 * the following code, with the same initial values for "a" and "b":
427 * read_barrier_depends();
431 * does not enforce ordering, since there is no data dependency between
432 * the read of "a" and the read of "b". Therefore, on some CPUs, such
433 * as Alpha, "y" could be set to 3 and "x" to 0. Use rmb()
434 * in cases like thiswhere there are no data dependencies.
437 #define read_barrier_depends() do { } while(0)
439 #ifdef CONFIG_X86_OOSTORE
440 /* Actually there are no OOO store capable CPUs for now that do SSE,
441 but make it already an possibility. */
442 #define wmb() alternative("lock; addl $0,0(%%esp)", "sfence", X86_FEATURE_XMM)
444 #define wmb() __asm__ __volatile__ ("": : :"memory")
448 #define smp_mb() mb()
449 #define smp_rmb() rmb()
450 #define smp_wmb() wmb()
451 #define smp_read_barrier_depends() read_barrier_depends()
452 #define set_mb(var, value) do { xchg(&var, value); } while (0)
454 #define smp_mb() barrier()
455 #define smp_rmb() barrier()
456 #define smp_wmb() barrier()
457 #define smp_read_barrier_depends() do { } while(0)
458 #define set_mb(var, value) do { var = value; barrier(); } while (0)
461 #define set_wmb(var, value) do { var = value; wmb(); } while (0)
463 /* interrupt control.. */
464 #define local_save_flags(x) do { typecheck(unsigned long,x); __asm__ __volatile__("pushfl ; popl %0":"=g" (x): /* no input */); } while (0)
465 #define local_irq_restore(x) do { typecheck(unsigned long,x); __asm__ __volatile__("pushl %0 ; popfl": /* no output */ :"g" (x):"memory", "cc"); } while (0)
466 #define local_irq_disable() __asm__ __volatile__("cli": : :"memory")
467 #define local_irq_enable() __asm__ __volatile__("sti": : :"memory")
468 /* used in the idle loop; sti takes one instruction cycle to complete */
469 #define safe_halt() __asm__ __volatile__("sti; hlt": : :"memory")
470 /* used when interrupts are already enabled or to shutdown the processor */
471 #define halt() __asm__ __volatile__("hlt": : :"memory")
473 #define irqs_disabled() \
475 unsigned long flags; \
476 local_save_flags(flags); \
480 /* For spinlocks etc */
481 #define local_irq_save(x) __asm__ __volatile__("pushfl ; popl %0 ; cli":"=g" (x): /* no input */ :"memory")
484 * disable hlt during certain critical i/o operations
486 #define HAVE_DISABLE_HLT
487 void disable_hlt(void);
488 void enable_hlt(void);
490 extern int es7000_plat;
491 void cpu_idle_wait(void);
493 extern unsigned long arch_align_stack(unsigned long sp);