1 /* bitops.h: bit operations for the Fujitsu FR-V CPUs
3 * For an explanation of how atomic ops work in this arch, see:
4 * Documentation/fujitsu/frv/atomic-ops.txt
6 * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
7 * Written by David Howells (dhowells@redhat.com)
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
17 #include <linux/compiler.h>
18 #include <asm/byteorder.h>
19 #include <asm/system.h>
20 #include <asm/atomic.h>
24 #include <asm-generic/bitops/ffz.h>
27 * clear_bit() doesn't provide any barrier for the compiler.
29 #define smp_mb__before_clear_bit() barrier()
30 #define smp_mb__after_clear_bit() barrier()
32 static inline int test_and_clear_bit(int nr, volatile void *addr)
34 volatile unsigned long *ptr = addr;
35 unsigned long mask = 1UL << (nr & 31);
37 return (atomic_test_and_ANDNOT_mask(mask, ptr) & mask) != 0;
40 static inline int test_and_set_bit(int nr, volatile void *addr)
42 volatile unsigned long *ptr = addr;
43 unsigned long mask = 1UL << (nr & 31);
45 return (atomic_test_and_OR_mask(mask, ptr) & mask) != 0;
48 static inline int test_and_change_bit(int nr, volatile void *addr)
50 volatile unsigned long *ptr = addr;
51 unsigned long mask = 1UL << (nr & 31);
53 return (atomic_test_and_XOR_mask(mask, ptr) & mask) != 0;
56 static inline void clear_bit(int nr, volatile void *addr)
58 test_and_clear_bit(nr, addr);
61 static inline void set_bit(int nr, volatile void *addr)
63 test_and_set_bit(nr, addr);
66 static inline void change_bit(int nr, volatile void * addr)
68 test_and_change_bit(nr, addr);
71 static inline void __clear_bit(int nr, volatile void * addr)
73 volatile unsigned long *a = addr;
77 mask = 1 << (nr & 31);
81 static inline void __set_bit(int nr, volatile void * addr)
83 volatile unsigned long *a = addr;
87 mask = 1 << (nr & 31);
91 static inline void __change_bit(int nr, volatile void *addr)
93 volatile unsigned long *a = addr;
97 mask = 1 << (nr & 31);
101 static inline int __test_and_clear_bit(int nr, volatile void * addr)
103 volatile unsigned long *a = addr;
107 mask = 1 << (nr & 31);
108 retval = (mask & *a) != 0;
113 static inline int __test_and_set_bit(int nr, volatile void * addr)
115 volatile unsigned long *a = addr;
119 mask = 1 << (nr & 31);
120 retval = (mask & *a) != 0;
125 static inline int __test_and_change_bit(int nr, volatile void * addr)
127 volatile unsigned long *a = addr;
131 mask = 1 << (nr & 31);
132 retval = (mask & *a) != 0;
138 * This routine doesn't need to be atomic.
140 static inline int __constant_test_bit(int nr, const volatile void * addr)
142 return ((1UL << (nr & 31)) & (((const volatile unsigned int *) addr)[nr >> 5])) != 0;
145 static inline int __test_bit(int nr, const volatile void * addr)
147 int * a = (int *) addr;
151 mask = 1 << (nr & 0x1f);
152 return ((mask & *a) != 0);
155 #define test_bit(nr,addr) \
156 (__builtin_constant_p(nr) ? \
157 __constant_test_bit((nr),(addr)) : \
158 __test_bit((nr),(addr)))
160 #include <asm-generic/bitops/find.h>
163 * fls - find last bit set
164 * @x: the word to search
166 * This is defined the same way as ffs:
167 * - return 32..1 to indicate bit 31..0 most significant bit set
168 * - return 0 to indicate no bits set
174 asm(" subcc %1,gr0,gr0,icc0 \n" \
175 " ckne icc0,cc4 \n" \
176 " cscan.p %1,gr0,%0 ,cc4,#1 \n" \
177 " csub %0,%0,%0 ,cc4,#0 \n" \
178 " csub %2,%0,%0 ,cc4,#1 \n" \
188 * fls64 - find last bit set in a 64-bit value
189 * @n: the value to search
191 * This is defined the same way as ffs:
192 * - return 64..1 to indicate bit 63..0 most significant bit set
193 * - return 0 to indicate no bits set
195 static inline __attribute__((const))
200 struct { u32 h, l; };
206 asm(" subcc.p %3,gr0,gr0,icc0 \n"
207 " subcc %4,gr0,gr0,icc1 \n"
210 " norcr cc4,cc5,cc6 \n"
211 " csub.p %0,%0,%0 ,cc6,1 \n"
212 " orcr cc5,cc4,cc4 \n"
213 " andcr cc4,cc5,cc4 \n"
214 " cscan.p %3,gr0,%0 ,cc4,0 \n"
216 " cscan.p %4,gr0,%0 ,cc4,1 \n"
218 " csub.p %1,%0,%0 ,cc4,0 \n"
219 " csub %2,%0,%0 ,cc4,1 \n"
220 : "=&r"(bit), "=r"(x), "=r"(y)
221 : "0r"(_.h), "r"(_.l)
222 : "icc0", "icc1", "cc4", "cc5", "cc6"
229 * ffs - find first bit set
230 * @x: the word to search
232 * - return 32..1 to indicate bit 31..0 most least significant bit set
233 * - return 0 to indicate no bits set
235 static inline __attribute__((const))
238 /* Note: (x & -x) gives us a mask that is the least significant
239 * (rightmost) 1-bit of the value in x.
245 * __ffs - find first bit set
246 * @x: the word to search
248 * - return 31..0 to indicate bit 31..0 most least significant bit set
249 * - if no bits are set in x, the result is undefined
251 static inline __attribute__((const))
252 int __ffs(unsigned long x)
255 asm("scan %1,gr0,%0" : "=r"(bit) : "r"(x & -x));
260 * special slimline version of fls() for calculating ilog2_u32()
261 * - note: no protection against n == 0
263 #define ARCH_HAS_ILOG2_U32
264 static inline __attribute__((const))
265 int __ilog2_u32(u32 n)
268 asm("scan %1,gr0,%0" : "=r"(bit) : "r"(n));
273 * special slimline version of fls64() for calculating ilog2_u64()
274 * - note: no protection against n == 0
276 #define ARCH_HAS_ILOG2_U64
277 static inline __attribute__((const))
278 int __ilog2_u64(u64 n)
282 struct { u32 h, l; };
288 asm(" subcc %3,gr0,gr0,icc0 \n"
290 " cscan.p %3,gr0,%0 ,cc4,0 \n"
292 " cscan.p %4,gr0,%0 ,cc4,1 \n"
294 " csub.p %1,%0,%0 ,cc4,0 \n"
295 " csub %2,%0,%0 ,cc4,1 \n"
296 : "=&r"(bit), "=r"(x), "=r"(y)
297 : "0r"(_.h), "r"(_.l)
303 #include <asm-generic/bitops/sched.h>
304 #include <asm-generic/bitops/hweight.h>
306 #include <asm-generic/bitops/ext2-non-atomic.h>
308 #define ext2_set_bit_atomic(lock,nr,addr) test_and_set_bit ((nr) ^ 0x18, (addr))
309 #define ext2_clear_bit_atomic(lock,nr,addr) test_and_clear_bit((nr) ^ 0x18, (addr))
311 #include <asm-generic/bitops/minix-le.h>
313 #endif /* __KERNEL__ */
315 #endif /* _ASM_BITOPS_H */