2 * include/asm-arm/arch-realview/entry-macro.S
4 * Low-level IRQ helper macros for RealView platforms
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
10 #include <asm/hardware.h>
11 #include <asm/hardware/gic.h>
12 #include <asm/arch/board-eb.h>
17 .macro get_irqnr_preamble, base, tmp
18 #ifdef CONFIG_REALVIEW_MPCORE
19 ldr \base, =IO_ADDRESS(REALVIEW_EB11MP_GIC_CPU_BASE)
21 ldr \base, =IO_ADDRESS(REALVIEW_GIC_CPU_BASE)
25 .macro arch_ret_to_user, tmp1, tmp2
29 * The interrupt numbering scheme is defined in the
30 * interrupt controller spec. To wit:
32 * Interrupts 0-15 are IPI
34 * 29-31 are local. We allow 30 to be used for the watchdog.
36 * 1021-1022 are reserved
37 * 1023 is "spurious" (no interrupt)
39 * For now, we ignore all local interrupts so only return an interrupt if it's
40 * between 30 and 1020. The test_for_ipi routine below will pick up on IPIs.
42 * A simple read from the controller will tell us the number of the highest
43 * priority enabled interrupt. We then just need to check whether it is in the
44 * valid range for an IRQ (30-1020 inclusive).
47 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
49 ldr \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */
53 bic \irqnr, \irqstat, #0x1c00
62 /* We assume that irqstat (the raw value of the IRQ acknowledge
63 * register) is preserved from the macro above.
64 * If there is an IPI, we immediately signal end of interrupt on the
65 * controller, since this requires the original irqstat value which
66 * we won't easily be able to recreate later.
69 .macro test_for_ipi, irqnr, irqstat, base, tmp
70 bic \irqnr, \irqstat, #0x1c00
72 strcc \irqstat, [\base, #GIC_CPU_EOI]
76 /* As above, this assumes that irqstat and base are preserved.. */
78 .macro test_for_ltirq, irqnr, irqstat, base, tmp
79 bic \irqnr, \irqstat, #0x1c00
83 streq \irqstat, [\base, #GIC_CPU_EOI]