drivers/video/via/hw.h

   1 /*
   2  * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
   3  * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
   4
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public
   7  * License as published by the Free Software Foundation;
   8  * either version 2, or (at your option) any later version.
   9
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
  12  * the implied warranty of MERCHANTABILITY or FITNESS FOR
  13  * A PARTICULAR PURPOSE.See the GNU General Public License
  14  * for more details.
  15
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc.,
  19  * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  20  */
  21
  22 #ifndef __HW_H__
  23 #define __HW_H__
  24
  25 #include "viamode.h"
  26 #include "global.h"
  27 #include "via_modesetting.h"
  28
  29 #define viafb_read_reg(p, i)                    via_read_reg(p, i)
  30 #define viafb_write_reg(i, p, d)                via_write_reg(p, i, d)
  31 #define viafb_write_reg_mask(i, p, d, m)        via_write_reg_mask(p, i, d, m)
  32
  33 /* VIA output devices */
  34 #define VIA_6C          0x00000001
  35 #define VIA_93          0x00000002
  36 #define VIA_96          0x00000004
  37 #define VIA_CRT         0x00000010
  38 #define VIA_DVP1        0x00000020
  39 #define VIA_LVDS1       0x00000040
  40 #define VIA_LVDS2       0x00000080
  41
  42 /***************************************************
  43 * Definition IGA1 Design Method of CRTC Registers *
  44 ****************************************************/
  45 #define IGA1_HOR_TOTAL_FORMULA(x)           (((x)/8)-5)
  46 #define IGA1_HOR_ADDR_FORMULA(x)            (((x)/8)-1)
  47 #define IGA1_HOR_BLANK_START_FORMULA(x)     (((x)/8)-1)
  48 #define IGA1_HOR_BLANK_END_FORMULA(x, y)     (((x+y)/8)-1)
  49 #define IGA1_HOR_SYNC_START_FORMULA(x)      ((x)/8)
  50 #define IGA1_HOR_SYNC_END_FORMULA(x, y)      ((x+y)/8)
  51
  52 #define IGA1_VER_TOTAL_FORMULA(x)           ((x)-2)
  53 #define IGA1_VER_ADDR_FORMULA(x)            ((x)-1)
  54 #define IGA1_VER_BLANK_START_FORMULA(x)     ((x)-1)
  55 #define IGA1_VER_BLANK_END_FORMULA(x, y)     ((x+y)-1)
  56 #define IGA1_VER_SYNC_START_FORMULA(x)      ((x)-1)
  57 #define IGA1_VER_SYNC_END_FORMULA(x, y)      ((x+y)-1)
  58
  59 /***************************************************
  60 ** Definition IGA2 Design Method of CRTC Registers *
  61 ****************************************************/
  62 #define IGA2_HOR_TOTAL_FORMULA(x)           ((x)-1)
  63 #define IGA2_HOR_ADDR_FORMULA(x)            ((x)-1)
  64 #define IGA2_HOR_BLANK_START_FORMULA(x)     ((x)-1)
  65 #define IGA2_HOR_BLANK_END_FORMULA(x, y)     ((x+y)-1)
  66 #define IGA2_HOR_SYNC_START_FORMULA(x)      ((x)-1)
  67 #define IGA2_HOR_SYNC_END_FORMULA(x, y)      ((x+y)-1)
  68
  69 #define IGA2_VER_TOTAL_FORMULA(x)           ((x)-1)
  70 #define IGA2_VER_ADDR_FORMULA(x)            ((x)-1)
  71 #define IGA2_VER_BLANK_START_FORMULA(x)     ((x)-1)
  72 #define IGA2_VER_BLANK_END_FORMULA(x, y)     ((x+y)-1)
  73 #define IGA2_VER_SYNC_START_FORMULA(x)      ((x)-1)
  74 #define IGA2_VER_SYNC_END_FORMULA(x, y)      ((x+y)-1)
  75
  76 /**********************************************************/
  77 /* Definition IGA2 Design Method of CRTC Shadow Registers */
  78 /**********************************************************/
  79 #define IGA2_HOR_TOTAL_SHADOW_FORMULA(x)           ((x/8)-5)
  80 #define IGA2_HOR_BLANK_END_SHADOW_FORMULA(x, y)     (((x+y)/8)-1)
  81 #define IGA2_VER_TOTAL_SHADOW_FORMULA(x)           ((x)-2)
  82 #define IGA2_VER_ADDR_SHADOW_FORMULA(x)            ((x)-1)
  83 #define IGA2_VER_BLANK_START_SHADOW_FORMULA(x)     ((x)-1)
  84 #define IGA2_VER_BLANK_END_SHADOW_FORMULA(x, y)     ((x+y)-1)
  85 #define IGA2_VER_SYNC_START_SHADOW_FORMULA(x)      (x)
  86 #define IGA2_VER_SYNC_END_SHADOW_FORMULA(x, y)      (x+y)
  87
  88 /* Define Register Number for IGA1 CRTC Timing */
  89
  90 /* location: {CR00,0,7},{CR36,3,3} */
  91 #define IGA1_HOR_TOTAL_REG_NUM          2
  92 /* location: {CR01,0,7} */
  93 #define IGA1_HOR_ADDR_REG_NUM           1
  94 /* location: {CR02,0,7} */
  95 #define IGA1_HOR_BLANK_START_REG_NUM    1
  96 /* location: {CR03,0,4},{CR05,7,7},{CR33,5,5} */
  97 #define IGA1_HOR_BLANK_END_REG_NUM      3
  98 /* location: {CR04,0,7},{CR33,4,4} */
  99 #define IGA1_HOR_SYNC_START_REG_NUM     2
 100 /* location: {CR05,0,4} */
 101 #define IGA1_HOR_SYNC_END_REG_NUM       1
 102 /* location: {CR06,0,7},{CR07,0,0},{CR07,5,5},{CR35,0,0} */
 103 #define IGA1_VER_TOTAL_REG_NUM          4
 104 /* location: {CR12,0,7},{CR07,1,1},{CR07,6,6},{CR35,2,2} */
 105 #define IGA1_VER_ADDR_REG_NUM           4
 106 /* location: {CR15,0,7},{CR07,3,3},{CR09,5,5},{CR35,3,3} */
 107 #define IGA1_VER_BLANK_START_REG_NUM    4
 108 /* location: {CR16,0,7} */
 109 #define IGA1_VER_BLANK_END_REG_NUM      1
 110 /* location: {CR10,0,7},{CR07,2,2},{CR07,7,7},{CR35,1,1} */
 111 #define IGA1_VER_SYNC_START_REG_NUM     4
 112 /* location: {CR11,0,3} */
 113 #define IGA1_VER_SYNC_END_REG_NUM       1
 114
 115 /* Define Register Number for IGA2 Shadow CRTC Timing */
 116
 117 /* location: {CR6D,0,7},{CR71,3,3} */
 118 #define IGA2_SHADOW_HOR_TOTAL_REG_NUM       2
 119 /* location: {CR6E,0,7} */
 120 #define IGA2_SHADOW_HOR_BLANK_END_REG_NUM   1
 121 /* location: {CR6F,0,7},{CR71,0,2} */
 122 #define IGA2_SHADOW_VER_TOTAL_REG_NUM       2
 123 /* location: {CR70,0,7},{CR71,4,6} */
 124 #define IGA2_SHADOW_VER_ADDR_REG_NUM        2
 125 /* location: {CR72,0,7},{CR74,4,6} */
 126 #define IGA2_SHADOW_VER_BLANK_START_REG_NUM 2
 127 /* location: {CR73,0,7},{CR74,0,2} */
 128 #define IGA2_SHADOW_VER_BLANK_END_REG_NUM   2
 129 /* location: {CR75,0,7},{CR76,4,6} */
 130 #define IGA2_SHADOW_VER_SYNC_START_REG_NUM  2
 131 /* location: {CR76,0,3} */
 132 #define IGA2_SHADOW_VER_SYNC_END_REG_NUM    1
 133
 134 /* Define Register Number for IGA2 CRTC Timing */
 135
 136 /* location: {CR50,0,7},{CR55,0,3} */
 137 #define IGA2_HOR_TOTAL_REG_NUM          2
 138 /* location: {CR51,0,7},{CR55,4,6} */
 139 #define IGA2_HOR_ADDR_REG_NUM           2
 140 /* location: {CR52,0,7},{CR54,0,2} */
 141 #define IGA2_HOR_BLANK_START_REG_NUM    2
 142 /* location: CLE266: {CR53,0,7},{CR54,3,5} => CLE266's CR5D[6]
 143 is reserved, so it may have problem to set 1600x1200 on IGA2. */
 144 /*              Others: {CR53,0,7},{CR54,3,5},{CR5D,6,6} */
 145 #define IGA2_HOR_BLANK_END_REG_NUM      3
 146 /* location: {CR56,0,7},{CR54,6,7},{CR5C,7,7} */
 147 /* VT3314 and Later: {CR56,0,7},{CR54,6,7},{CR5C,7,7}, {CR5D,7,7} */
 148 #define IGA2_HOR_SYNC_START_REG_NUM     4
 149
 150 /* location: {CR57,0,7},{CR5C,6,6} */
 151 #define IGA2_HOR_SYNC_END_REG_NUM       2
 152 /* location: {CR58,0,7},{CR5D,0,2} */
 153 #define IGA2_VER_TOTAL_REG_NUM          2
 154 /* location: {CR59,0,7},{CR5D,3,5} */
 155 #define IGA2_VER_ADDR_REG_NUM           2
 156 /* location: {CR5A,0,7},{CR5C,0,2} */
 157 #define IGA2_VER_BLANK_START_REG_NUM    2
 158 /* location: {CR5E,0,7},{CR5C,3,5} */
 159 #define IGA2_VER_BLANK_END_REG_NUM      2
 160 /* location: {CR5E,0,7},{CR5F,5,7} */
 161 #define IGA2_VER_SYNC_START_REG_NUM     2
 162 /* location: {CR5F,0,4} */
 163 #define IGA2_VER_SYNC_END_REG_NUM       1
 164
 165 /* Define Fetch Count Register*/
 166
 167 /* location: {SR1C,0,7},{SR1D,0,1} */
 168 #define IGA1_FETCH_COUNT_REG_NUM        2
 169 /* 16 bytes alignment. */
 170 #define IGA1_FETCH_COUNT_ALIGN_BYTE     16
 171 /* x: H resolution, y: color depth */
 172 #define IGA1_FETCH_COUNT_PATCH_VALUE    4
 173 #define IGA1_FETCH_COUNT_FORMULA(x, y)   \
 174         (((x*y)/IGA1_FETCH_COUNT_ALIGN_BYTE) + IGA1_FETCH_COUNT_PATCH_VALUE)
 175
 176 /* location: {CR65,0,7},{CR67,2,3} */
 177 #define IGA2_FETCH_COUNT_REG_NUM        2
 178 #define IGA2_FETCH_COUNT_ALIGN_BYTE     16
 179 #define IGA2_FETCH_COUNT_PATCH_VALUE    0
 180 #define IGA2_FETCH_COUNT_FORMULA(x, y)   \
 181         (((x*y)/IGA2_FETCH_COUNT_ALIGN_BYTE) + IGA2_FETCH_COUNT_PATCH_VALUE)
 182
 183 /* Staring Address*/
 184
 185 /* location: {CR0C,0,7},{CR0D,0,7},{CR34,0,7},{CR48,0,1} */
 186 #define IGA1_STARTING_ADDR_REG_NUM      4
 187 /* location: {CR62,1,7},{CR63,0,7},{CR64,0,7} */
 188 #define IGA2_STARTING_ADDR_REG_NUM      3
 189
 190 /* Define Display OFFSET*/
 191 /* These value are by HW suggested value*/
 192 /* location: {SR17,0,7} */
 193 #define K800_IGA1_FIFO_MAX_DEPTH                384
 194 /* location: {SR16,0,5},{SR16,7,7} */
 195 #define K800_IGA1_FIFO_THRESHOLD                328
 196 /* location: {SR18,0,5},{SR18,7,7} */
 197 #define K800_IGA1_FIFO_HIGH_THRESHOLD           296
 198 /* location: {SR22,0,4}. (128/4) =64, K800 must be set zero, */
 199                                 /* because HW only 5 bits */
 200 #define K800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM      0
 201
 202 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
 203 #define K800_IGA2_FIFO_MAX_DEPTH                384
 204 /* location: {CR68,0,3},{CR95,4,6} */
 205 #define K800_IGA2_FIFO_THRESHOLD                328
 206 /* location: {CR92,0,3},{CR95,0,2} */
 207 #define K800_IGA2_FIFO_HIGH_THRESHOLD           296
 208 /* location: {CR94,0,6} */
 209 #define K800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM      128
 210
 211 /* location: {SR17,0,7} */
 212 #define P880_IGA1_FIFO_MAX_DEPTH                192
 213 /* location: {SR16,0,5},{SR16,7,7} */
 214 #define P880_IGA1_FIFO_THRESHOLD                128
 215 /* location: {SR18,0,5},{SR18,7,7} */
 216 #define P880_IGA1_FIFO_HIGH_THRESHOLD           64
 217 /* location: {SR22,0,4}. (128/4) =64, K800 must be set zero, */
 218                                 /* because HW only 5 bits */
 219 #define P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM      0
 220
 221 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
 222 #define P880_IGA2_FIFO_MAX_DEPTH                96
 223 /* location: {CR68,0,3},{CR95,4,6} */
 224 #define P880_IGA2_FIFO_THRESHOLD                64
 225 /* location: {CR92,0,3},{CR95,0,2} */
 226 #define P880_IGA2_FIFO_HIGH_THRESHOLD           32
 227 /* location: {CR94,0,6} */
 228 #define P880_IGA2_DISPLAY_QUEUE_EXPIRE_NUM      128
 229
 230 /* VT3314 chipset*/
 231
 232 /* location: {SR17,0,7} */
 233 #define CN700_IGA1_FIFO_MAX_DEPTH               96
 234 /* location: {SR16,0,5},{SR16,7,7} */
 235 #define CN700_IGA1_FIFO_THRESHOLD               80
 236 /* location: {SR18,0,5},{SR18,7,7} */
 237 #define CN700_IGA1_FIFO_HIGH_THRESHOLD          64
 238 /* location: {SR22,0,4}. (128/4) =64, P800 must be set zero,
 239                                 because HW only 5 bits */
 240 #define CN700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM     0
 241 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
 242 #define CN700_IGA2_FIFO_MAX_DEPTH               96
 243 /* location: {CR68,0,3},{CR95,4,6} */
 244 #define CN700_IGA2_FIFO_THRESHOLD               80
 245 /* location: {CR92,0,3},{CR95,0,2} */
 246 #define CN700_IGA2_FIFO_HIGH_THRESHOLD          32
 247 /* location: {CR94,0,6} */
 248 #define CN700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM     128
 249
 250 /* For VT3324, these values are suggested by HW */
 251 /* location: {SR17,0,7} */
 252 #define CX700_IGA1_FIFO_MAX_DEPTH               192
 253 /* location: {SR16,0,5},{SR16,7,7} */
 254 #define CX700_IGA1_FIFO_THRESHOLD               128
 255 /* location: {SR18,0,5},{SR18,7,7} */
 256 #define CX700_IGA1_FIFO_HIGH_THRESHOLD          128
 257 /* location: {SR22,0,4} */
 258 #define CX700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM     124
 259
 260 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
 261 #define CX700_IGA2_FIFO_MAX_DEPTH               96
 262 /* location: {CR68,0,3},{CR95,4,6} */
 263 #define CX700_IGA2_FIFO_THRESHOLD               64
 264 /* location: {CR92,0,3},{CR95,0,2} */
 265 #define CX700_IGA2_FIFO_HIGH_THRESHOLD          32
 266 /* location: {CR94,0,6} */
 267 #define CX700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM     128
 268
 269 /* VT3336 chipset*/
 270 /* location: {SR17,0,7} */
 271 #define K8M890_IGA1_FIFO_MAX_DEPTH               360
 272 /* location: {SR16,0,5},{SR16,7,7} */
 273 #define K8M890_IGA1_FIFO_THRESHOLD               328
 274 /* location: {SR18,0,5},{SR18,7,7} */
 275 #define K8M890_IGA1_FIFO_HIGH_THRESHOLD          296
 276 /* location: {SR22,0,4}. */
 277 #define K8M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM     124
 278
 279 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
 280 #define K8M890_IGA2_FIFO_MAX_DEPTH               360
 281 /* location: {CR68,0,3},{CR95,4,6} */
 282 #define K8M890_IGA2_FIFO_THRESHOLD               328
 283 /* location: {CR92,0,3},{CR95,0,2} */
 284 #define K8M890_IGA2_FIFO_HIGH_THRESHOLD          296
 285 /* location: {CR94,0,6} */
 286 #define K8M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM     124
 287
 288 /* VT3327 chipset*/
 289 /* location: {SR17,0,7} */
 290 #define P4M890_IGA1_FIFO_MAX_DEPTH               96
 291 /* location: {SR16,0,5},{SR16,7,7} */
 292 #define P4M890_IGA1_FIFO_THRESHOLD               76
 293 /* location: {SR18,0,5},{SR18,7,7} */
 294 #define P4M890_IGA1_FIFO_HIGH_THRESHOLD          64
 295 /* location: {SR22,0,4}. (32/4) =8 */
 296 #define P4M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM     32
 297 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
 298 #define P4M890_IGA2_FIFO_MAX_DEPTH               96
 299 /* location: {CR68,0,3},{CR95,4,6} */
 300 #define P4M890_IGA2_FIFO_THRESHOLD               76
 301 /* location: {CR92,0,3},{CR95,0,2} */
 302 #define P4M890_IGA2_FIFO_HIGH_THRESHOLD          64
 303 /* location: {CR94,0,6} */
 304 #define P4M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM     32
 305
 306 /* VT3364 chipset*/
 307 /* location: {SR17,0,7} */
 308 #define P4M900_IGA1_FIFO_MAX_DEPTH               96
 309 /* location: {SR16,0,5},{SR16,7,7} */
 310 #define P4M900_IGA1_FIFO_THRESHOLD               76
 311 /* location: {SR18,0,5},{SR18,7,7} */
 312 #define P4M900_IGA1_FIFO_HIGH_THRESHOLD          76
 313 /* location: {SR22,0,4}. */
 314 #define P4M900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM     32
 315 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
 316 #define P4M900_IGA2_FIFO_MAX_DEPTH               96
 317 /* location: {CR68,0,3},{CR95,4,6} */
 318 #define P4M900_IGA2_FIFO_THRESHOLD               76
 319 /* location: {CR92,0,3},{CR95,0,2} */
 320 #define P4M900_IGA2_FIFO_HIGH_THRESHOLD          76
 321 /* location: {CR94,0,6} */
 322 #define P4M900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM     32
 323
 324 /* For VT3353, these values are suggested by HW */
 325 /* location: {SR17,0,7} */
 326 #define VX800_IGA1_FIFO_MAX_DEPTH               192
 327 /* location: {SR16,0,5},{SR16,7,7} */
 328 #define VX800_IGA1_FIFO_THRESHOLD               152
 329 /* location: {SR18,0,5},{SR18,7,7} */
 330 #define VX800_IGA1_FIFO_HIGH_THRESHOLD          152
 331 /* location: {SR22,0,4} */
 332 #define VX800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM      64
 333 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
 334 #define VX800_IGA2_FIFO_MAX_DEPTH               96
 335 /* location: {CR68,0,3},{CR95,4,6} */
 336 #define VX800_IGA2_FIFO_THRESHOLD               64
 337 /* location: {CR92,0,3},{CR95,0,2} */
 338 #define VX800_IGA2_FIFO_HIGH_THRESHOLD          32
 339 /* location: {CR94,0,6} */
 340 #define VX800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM     128
 341
 342 /* For VT3409 */
 343 #define VX855_IGA1_FIFO_MAX_DEPTH               400
 344 #define VX855_IGA1_FIFO_THRESHOLD               320
 345 #define VX855_IGA1_FIFO_HIGH_THRESHOLD          320
 346 #define VX855_IGA1_DISPLAY_QUEUE_EXPIRE_NUM     160
 347
 348 #define VX855_IGA2_FIFO_MAX_DEPTH               200
 349 #define VX855_IGA2_FIFO_THRESHOLD               160
 350 #define VX855_IGA2_FIFO_HIGH_THRESHOLD          160
 351 #define VX855_IGA2_DISPLAY_QUEUE_EXPIRE_NUM     320
 352
 353 #define IGA1_FIFO_DEPTH_SELECT_REG_NUM          1
 354 #define IGA1_FIFO_THRESHOLD_REG_NUM             2
 355 #define IGA1_FIFO_HIGH_THRESHOLD_REG_NUM        2
 356 #define IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM   1
 357
 358 #define IGA2_FIFO_DEPTH_SELECT_REG_NUM          3
 359 #define IGA2_FIFO_THRESHOLD_REG_NUM             2
 360 #define IGA2_FIFO_HIGH_THRESHOLD_REG_NUM        2
 361 #define IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM   1
 362
 363 #define IGA1_FIFO_DEPTH_SELECT_FORMULA(x)                   ((x/2)-1)
 364 #define IGA1_FIFO_THRESHOLD_FORMULA(x)                      (x/4)
 365 #define IGA1_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA(x)            (x/4)
 366 #define IGA1_FIFO_HIGH_THRESHOLD_FORMULA(x)                 (x/4)
 367 #define IGA2_FIFO_DEPTH_SELECT_FORMULA(x)                   (((x/2)/4)-1)
 368 #define IGA2_FIFO_THRESHOLD_FORMULA(x)                      (x/4)
 369 #define IGA2_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA(x)            (x/4)
 370 #define IGA2_FIFO_HIGH_THRESHOLD_FORMULA(x)                 (x/4)
 371
 372 /************************************************************************/
 373 /*  LCD Timing                                                          */
 374 /************************************************************************/
 375
 376 /* 500 ms = 500000 us */
 377 #define LCD_POWER_SEQ_TD0               500000
 378 /* 50 ms = 50000 us */
 379 #define LCD_POWER_SEQ_TD1               50000
 380 /* 0 us */
 381 #define LCD_POWER_SEQ_TD2               0
 382 /* 210 ms = 210000 us */
 383 #define LCD_POWER_SEQ_TD3               210000
 384 /* 2^10 * (1/14.31818M) = 71.475 us (K400.revA) */
 385 #define CLE266_POWER_SEQ_UNIT           71
 386 /* 2^11 * (1/14.31818M) = 142.95 us (K400.revB) */
 387 #define K800_POWER_SEQ_UNIT             142
 388 /* 2^13 * (1/14.31818M) = 572.1 us */
 389 #define P880_POWER_SEQ_UNIT             572
 390
 391 #define CLE266_POWER_SEQ_FORMULA(x)     ((x)/CLE266_POWER_SEQ_UNIT)
 392 #define K800_POWER_SEQ_FORMULA(x)       ((x)/K800_POWER_SEQ_UNIT)
 393 #define P880_POWER_SEQ_FORMULA(x)       ((x)/P880_POWER_SEQ_UNIT)
 394
 395 /* location: {CR8B,0,7},{CR8F,0,3} */
 396 #define LCD_POWER_SEQ_TD0_REG_NUM       2
 397 /* location: {CR8C,0,7},{CR8F,4,7} */
 398 #define LCD_POWER_SEQ_TD1_REG_NUM       2
 399 /* location: {CR8D,0,7},{CR90,0,3} */
 400 #define LCD_POWER_SEQ_TD2_REG_NUM       2
 401 /* location: {CR8E,0,7},{CR90,4,7} */
 402 #define LCD_POWER_SEQ_TD3_REG_NUM       2
 403
 404 /* LCD Scaling factor*/
 405 /* x: indicate setting horizontal size*/
 406 /* y: indicate panel horizontal size*/
 407
 408 /* Horizontal scaling factor 10 bits (2^10) */
 409 #define CLE266_LCD_HOR_SCF_FORMULA(x, y)   (((x-1)*1024)/(y-1))
 410 /* Vertical scaling factor 10 bits (2^10) */
 411 #define CLE266_LCD_VER_SCF_FORMULA(x, y)   (((x-1)*1024)/(y-1))
 412 /* Horizontal scaling factor 10 bits (2^12) */
 413 #define K800_LCD_HOR_SCF_FORMULA(x, y)     (((x-1)*4096)/(y-1))
 414 /* Vertical scaling factor 10 bits (2^11) */
 415 #define K800_LCD_VER_SCF_FORMULA(x, y)     (((x-1)*2048)/(y-1))
 416
 417 /* location: {CR9F,0,1},{CR77,0,7},{CR79,4,5} */
 418 #define LCD_HOR_SCALING_FACTOR_REG_NUM  3
 419 /* location: {CR79,3,3},{CR78,0,7},{CR79,6,7} */
 420 #define LCD_VER_SCALING_FACTOR_REG_NUM  3
 421 /* location: {CR77,0,7},{CR79,4,5} */
 422 #define LCD_HOR_SCALING_FACTOR_REG_NUM_CLE  2
 423 /* location: {CR78,0,7},{CR79,6,7} */
 424 #define LCD_VER_SCALING_FACTOR_REG_NUM_CLE  2
 425
 426 /************************************************
 427  *****     Define IGA1 Display Timing       *****
 428  ************************************************/
 429 struct io_register {
 430         u8 io_addr;
 431         u8 start_bit;
 432         u8 end_bit;
 433 };
 434
 435 /* IGA1 Horizontal Total */
 436 struct iga1_hor_total {
 437         int reg_num;
 438         struct io_register reg[IGA1_HOR_TOTAL_REG_NUM];
 439 };
 440
 441 /* IGA1 Horizontal Addressable Video */
 442 struct iga1_hor_addr {
 443         int reg_num;
 444         struct io_register reg[IGA1_HOR_ADDR_REG_NUM];
 445 };
 446
 447 /* IGA1 Horizontal Blank Start */
 448 struct iga1_hor_blank_start {
 449         int reg_num;
 450         struct io_register reg[IGA1_HOR_BLANK_START_REG_NUM];
 451 };
 452
 453 /* IGA1 Horizontal Blank End */
 454 struct iga1_hor_blank_end {
 455         int reg_num;
 456         struct io_register reg[IGA1_HOR_BLANK_END_REG_NUM];
 457 };
 458
 459 /* IGA1 Horizontal Sync Start */
 460 struct iga1_hor_sync_start {
 461         int reg_num;
 462         struct io_register reg[IGA1_HOR_SYNC_START_REG_NUM];
 463 };
 464
 465 /* IGA1 Horizontal Sync End */
 466 struct iga1_hor_sync_end {
 467         int reg_num;
 468         struct io_register reg[IGA1_HOR_SYNC_END_REG_NUM];
 469 };
 470
 471 /* IGA1 Vertical Total */
 472 struct iga1_ver_total {
 473         int reg_num;
 474         struct io_register reg[IGA1_VER_TOTAL_REG_NUM];
 475 };
 476
 477 /* IGA1 Vertical Addressable Video */
 478 struct iga1_ver_addr {
 479         int reg_num;
 480         struct io_register reg[IGA1_VER_ADDR_REG_NUM];
 481 };
 482
 483 /* IGA1 Vertical Blank Start */
 484 struct iga1_ver_blank_start {
 485         int reg_num;
 486         struct io_register reg[IGA1_VER_BLANK_START_REG_NUM];
 487 };
 488
 489 /* IGA1 Vertical Blank End */
 490 struct iga1_ver_blank_end {
 491         int reg_num;
 492         struct io_register reg[IGA1_VER_BLANK_END_REG_NUM];
 493 };
 494
 495 /* IGA1 Vertical Sync Start */
 496 struct iga1_ver_sync_start {
 497         int reg_num;
 498         struct io_register reg[IGA1_VER_SYNC_START_REG_NUM];
 499 };
 500
 501 /* IGA1 Vertical Sync End */
 502 struct iga1_ver_sync_end {
 503         int reg_num;
 504         struct io_register reg[IGA1_VER_SYNC_END_REG_NUM];
 505 };
 506
 507 /*****************************************************
 508 **      Define IGA2 Shadow Display Timing         ****
 509 *****************************************************/
 510
 511 /* IGA2 Shadow Horizontal Total */
 512 struct iga2_shadow_hor_total {
 513         int reg_num;
 514         struct io_register reg[IGA2_SHADOW_HOR_TOTAL_REG_NUM];
 515 };
 516
 517 /* IGA2 Shadow Horizontal Blank End */
 518 struct iga2_shadow_hor_blank_end {
 519         int reg_num;
 520         struct io_register reg[IGA2_SHADOW_HOR_BLANK_END_REG_NUM];
 521 };
 522
 523 /* IGA2 Shadow Vertical Total */
 524 struct iga2_shadow_ver_total {
 525         int reg_num;
 526         struct io_register reg[IGA2_SHADOW_VER_TOTAL_REG_NUM];
 527 };
 528
 529 /* IGA2 Shadow Vertical Addressable Video */
 530 struct iga2_shadow_ver_addr {
 531         int reg_num;
 532         struct io_register reg[IGA2_SHADOW_VER_ADDR_REG_NUM];
 533 };
 534
 535 /* IGA2 Shadow Vertical Blank Start */
 536 struct iga2_shadow_ver_blank_start {
 537         int reg_num;
 538         struct io_register reg[IGA2_SHADOW_VER_BLANK_START_REG_NUM];
 539 };
 540
 541 /* IGA2 Shadow Vertical Blank End */
 542 struct iga2_shadow_ver_blank_end {
 543         int reg_num;
 544         struct io_register reg[IGA2_SHADOW_VER_BLANK_END_REG_NUM];
 545 };
 546
 547 /* IGA2 Shadow Vertical Sync Start */
 548 struct iga2_shadow_ver_sync_start {
 549         int reg_num;
 550         struct io_register reg[IGA2_SHADOW_VER_SYNC_START_REG_NUM];
 551 };
 552
 553 /* IGA2 Shadow Vertical Sync End */
 554 struct iga2_shadow_ver_sync_end {
 555         int reg_num;
 556         struct io_register reg[IGA2_SHADOW_VER_SYNC_END_REG_NUM];
 557 };
 558
 559 /*****************************************************
 560 **      Define IGA2 Display Timing                ****
 561 ******************************************************/
 562
 563 /* IGA2 Horizontal Total */
 564 struct iga2_hor_total {
 565         int reg_num;
 566         struct io_register reg[IGA2_HOR_TOTAL_REG_NUM];
 567 };
 568
 569 /* IGA2 Horizontal Addressable Video */
 570 struct iga2_hor_addr {
 571         int reg_num;
 572         struct io_register reg[IGA2_HOR_ADDR_REG_NUM];
 573 };
 574
 575 /* IGA2 Horizontal Blank Start */
 576 struct iga2_hor_blank_start {
 577         int reg_num;
 578         struct io_register reg[IGA2_HOR_BLANK_START_REG_NUM];
 579 };
 580
 581 /* IGA2 Horizontal Blank End */
 582 struct iga2_hor_blank_end {
 583         int reg_num;
 584         struct io_register reg[IGA2_HOR_BLANK_END_REG_NUM];
 585 };
 586
 587 /* IGA2 Horizontal Sync Start */
 588 struct iga2_hor_sync_start {
 589         int reg_num;
 590         struct io_register reg[IGA2_HOR_SYNC_START_REG_NUM];
 591 };
 592
 593 /* IGA2 Horizontal Sync End */
 594 struct iga2_hor_sync_end {
 595         int reg_num;
 596         struct io_register reg[IGA2_HOR_SYNC_END_REG_NUM];
 597 };
 598
 599 /* IGA2 Vertical Total */
 600 struct iga2_ver_total {
 601         int reg_num;
 602         struct io_register reg[IGA2_VER_TOTAL_REG_NUM];
 603 };
 604
 605 /* IGA2 Vertical Addressable Video */
 606 struct iga2_ver_addr {
 607         int reg_num;
 608         struct io_register reg[IGA2_VER_ADDR_REG_NUM];
 609 };
 610
 611 /* IGA2 Vertical Blank Start */
 612 struct iga2_ver_blank_start {
 613         int reg_num;
 614         struct io_register reg[IGA2_VER_BLANK_START_REG_NUM];
 615 };
 616
 617 /* IGA2 Vertical Blank End */
 618 struct iga2_ver_blank_end {
 619         int reg_num;
 620         struct io_register reg[IGA2_VER_BLANK_END_REG_NUM];
 621 };
 622
 623 /* IGA2 Vertical Sync Start */
 624 struct iga2_ver_sync_start {
 625         int reg_num;
 626         struct io_register reg[IGA2_VER_SYNC_START_REG_NUM];
 627 };
 628
 629 /* IGA2 Vertical Sync End */
 630 struct iga2_ver_sync_end {
 631         int reg_num;
 632         struct io_register reg[IGA2_VER_SYNC_END_REG_NUM];
 633 };
 634
 635 /* IGA1 Fetch Count Register */
 636 struct iga1_fetch_count {
 637         int reg_num;
 638         struct io_register reg[IGA1_FETCH_COUNT_REG_NUM];
 639 };
 640
 641 /* IGA2 Fetch Count Register */
 642 struct iga2_fetch_count {
 643         int reg_num;
 644         struct io_register reg[IGA2_FETCH_COUNT_REG_NUM];
 645 };
 646
 647 struct fetch_count {
 648         struct iga1_fetch_count iga1_fetch_count_reg;
 649         struct iga2_fetch_count iga2_fetch_count_reg;
 650 };
 651
 652 /* Starting Address Register */
 653 struct iga1_starting_addr {
 654         int reg_num;
 655         struct io_register reg[IGA1_STARTING_ADDR_REG_NUM];
 656 };
 657
 658 struct iga2_starting_addr {
 659         int reg_num;
 660         struct io_register reg[IGA2_STARTING_ADDR_REG_NUM];
 661 };
 662
 663 struct starting_addr {
 664         struct iga1_starting_addr iga1_starting_addr_reg;
 665         struct iga2_starting_addr iga2_starting_addr_reg;
 666 };
 667
 668 /* LCD Power Sequence Timer */
 669 struct lcd_pwd_seq_td0 {
 670         int reg_num;
 671         struct io_register reg[LCD_POWER_SEQ_TD0_REG_NUM];
 672 };
 673
 674 struct lcd_pwd_seq_td1 {
 675         int reg_num;
 676         struct io_register reg[LCD_POWER_SEQ_TD1_REG_NUM];
 677 };
 678
 679 struct lcd_pwd_seq_td2 {
 680         int reg_num;
 681         struct io_register reg[LCD_POWER_SEQ_TD2_REG_NUM];
 682 };
 683
 684 struct lcd_pwd_seq_td3 {
 685         int reg_num;
 686         struct io_register reg[LCD_POWER_SEQ_TD3_REG_NUM];
 687 };
 688
 689 struct _lcd_pwd_seq_timer {
 690         struct lcd_pwd_seq_td0 td0;
 691         struct lcd_pwd_seq_td1 td1;
 692         struct lcd_pwd_seq_td2 td2;
 693         struct lcd_pwd_seq_td3 td3;
 694 };
 695
 696 /* LCD Scaling Factor */
 697 struct _lcd_hor_scaling_factor {
 698         int reg_num;
 699         struct io_register reg[LCD_HOR_SCALING_FACTOR_REG_NUM];
 700 };
 701
 702 struct _lcd_ver_scaling_factor {
 703         int reg_num;
 704         struct io_register reg[LCD_VER_SCALING_FACTOR_REG_NUM];
 705 };
 706
 707 struct _lcd_scaling_factor {
 708         struct _lcd_hor_scaling_factor lcd_hor_scaling_factor;
 709         struct _lcd_ver_scaling_factor lcd_ver_scaling_factor;
 710 };
 711
 712 struct pll_config {
 713         u16 multiplier;
 714         u8 divisor;
 715         u8 rshift;
 716 };
 717
 718 struct pll_map {
 719         u32 clk;
 720         struct pll_config cle266_pll;
 721         struct pll_config k800_pll;
 722         struct pll_config cx700_pll;
 723         struct pll_config vx855_pll;
 724 };
 725
 726 struct rgbLUT {
 727         u8 red;
 728         u8 green;
 729         u8 blue;
 730 };
 731
 732 struct lcd_pwd_seq_timer {
 733         u16 td0;
 734         u16 td1;
 735         u16 td2;
 736         u16 td3;
 737 };
 738
 739 /* Display FIFO Relation Registers*/
 740 struct iga1_fifo_depth_select {
 741         int reg_num;
 742         struct io_register reg[IGA1_FIFO_DEPTH_SELECT_REG_NUM];
 743 };
 744
 745 struct iga1_fifo_threshold_select {
 746         int reg_num;
 747         struct io_register reg[IGA1_FIFO_THRESHOLD_REG_NUM];
 748 };
 749
 750 struct iga1_fifo_high_threshold_select {
 751         int reg_num;
 752         struct io_register reg[IGA1_FIFO_HIGH_THRESHOLD_REG_NUM];
 753 };
 754
 755 struct iga1_display_queue_expire_num {
 756         int reg_num;
 757         struct io_register reg[IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM];
 758 };
 759
 760 struct iga2_fifo_depth_select {
 761         int reg_num;
 762         struct io_register reg[IGA2_FIFO_DEPTH_SELECT_REG_NUM];
 763 };
 764
 765 struct iga2_fifo_threshold_select {
 766         int reg_num;
 767         struct io_register reg[IGA2_FIFO_THRESHOLD_REG_NUM];
 768 };
 769
 770 struct iga2_fifo_high_threshold_select {
 771         int reg_num;
 772         struct io_register reg[IGA2_FIFO_HIGH_THRESHOLD_REG_NUM];
 773 };
 774
 775 struct iga2_display_queue_expire_num {
 776         int reg_num;
 777         struct io_register reg[IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM];
 778 };
 779
 780 struct fifo_depth_select {
 781         struct iga1_fifo_depth_select iga1_fifo_depth_select_reg;
 782         struct iga2_fifo_depth_select iga2_fifo_depth_select_reg;
 783 };
 784
 785 struct fifo_threshold_select {
 786         struct iga1_fifo_threshold_select iga1_fifo_threshold_select_reg;
 787         struct iga2_fifo_threshold_select iga2_fifo_threshold_select_reg;
 788 };
 789
 790 struct fifo_high_threshold_select {
 791         struct iga1_fifo_high_threshold_select
 792          iga1_fifo_high_threshold_select_reg;
 793         struct iga2_fifo_high_threshold_select
 794          iga2_fifo_high_threshold_select_reg;
 795 };
 796
 797 struct display_queue_expire_num {
 798         struct iga1_display_queue_expire_num
 799          iga1_display_queue_expire_num_reg;
 800         struct iga2_display_queue_expire_num
 801          iga2_display_queue_expire_num_reg;
 802 };
 803
 804 struct iga1_crtc_timing {
 805         struct iga1_hor_total hor_total;
 806         struct iga1_hor_addr hor_addr;
 807         struct iga1_hor_blank_start hor_blank_start;
 808         struct iga1_hor_blank_end hor_blank_end;
 809         struct iga1_hor_sync_start hor_sync_start;
 810         struct iga1_hor_sync_end hor_sync_end;
 811         struct iga1_ver_total ver_total;
 812         struct iga1_ver_addr ver_addr;
 813         struct iga1_ver_blank_start ver_blank_start;
 814         struct iga1_ver_blank_end ver_blank_end;
 815         struct iga1_ver_sync_start ver_sync_start;
 816         struct iga1_ver_sync_end ver_sync_end;
 817 };
 818
 819 struct iga2_shadow_crtc_timing {
 820         struct iga2_shadow_hor_total hor_total_shadow;
 821         struct iga2_shadow_hor_blank_end hor_blank_end_shadow;
 822         struct iga2_shadow_ver_total ver_total_shadow;
 823         struct iga2_shadow_ver_addr ver_addr_shadow;
 824         struct iga2_shadow_ver_blank_start ver_blank_start_shadow;
 825         struct iga2_shadow_ver_blank_end ver_blank_end_shadow;
 826         struct iga2_shadow_ver_sync_start ver_sync_start_shadow;
 827         struct iga2_shadow_ver_sync_end ver_sync_end_shadow;
 828 };
 829
 830 struct iga2_crtc_timing {
 831         struct iga2_hor_total hor_total;
 832         struct iga2_hor_addr hor_addr;
 833         struct iga2_hor_blank_start hor_blank_start;
 834         struct iga2_hor_blank_end hor_blank_end;
 835         struct iga2_hor_sync_start hor_sync_start;
 836         struct iga2_hor_sync_end hor_sync_end;
 837         struct iga2_ver_total ver_total;
 838         struct iga2_ver_addr ver_addr;
 839         struct iga2_ver_blank_start ver_blank_start;
 840         struct iga2_ver_blank_end ver_blank_end;
 841         struct iga2_ver_sync_start ver_sync_start;
 842         struct iga2_ver_sync_end ver_sync_end;
 843 };
 844
 845 /* device ID */
 846 #define CLE266_FUNCTION3    0x3123
 847 #define KM400_FUNCTION3     0x3205
 848 #define CN400_FUNCTION2     0x2259
 849 #define CN400_FUNCTION3     0x3259
 850 /* support VT3314 chipset */
 851 #define CN700_FUNCTION2     0x2314
 852 #define CN700_FUNCTION3     0x3208
 853 /* VT3324 chipset */
 854 #define CX700_FUNCTION2     0x2324
 855 #define CX700_FUNCTION3     0x3324
 856 /* VT3204 chipset*/
 857 #define KM800_FUNCTION3      0x3204
 858 /* VT3336 chipset*/
 859 #define KM890_FUNCTION3      0x3336
 860 /* VT3327 chipset*/
 861 #define P4M890_FUNCTION3     0x3327
 862 /* VT3293 chipset*/
 863 #define CN750_FUNCTION3     0x3208
 864 /* VT3364 chipset*/
 865 #define P4M900_FUNCTION3    0x3364
 866 /* VT3353 chipset*/
 867 #define VX800_FUNCTION3     0x3353
 868 /* VT3409 chipset*/
 869 #define VX855_FUNCTION3     0x3409
 870
 871 #define NUM_TOTAL_PLL_TABLE ARRAY_SIZE(pll_value)
 872
 873 struct IODATA {
 874         u8 Index;
 875         u8 Mask;
 876         u8 Data;
 877 };
 878
 879 struct pci_device_id_info {
 880         u32 vendor;
 881         u32 device;
 882         u32 chip_index;
 883 };
 884
 885 extern unsigned int viafb_second_virtual_xres;
 886 extern int viafb_SAMM_ON;
 887 extern int viafb_dual_fb;
 888 extern int viafb_LCD2_ON;
 889 extern int viafb_LCD_ON;
 890 extern int viafb_DVI_ON;
 891 extern int viafb_hotplug;
 892
 893 void viafb_set_output_path(int device, int set_iga,
 894         int output_interface);
 895
 896 void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
 897         struct VideoModeTable *video_mode, int bpp_byte, int set_iga);
 898
 899 void viafb_set_vclock(u32 CLK, int set_iga);
 900 void viafb_load_reg(int timing_value, int viafb_load_reg_num,
 901         struct io_register *reg,
 902               int io_type);
 903 void viafb_crt_disable(void);
 904 void viafb_crt_enable(void);
 905 void init_ad9389(void);
 906 /* Access I/O Function */
 907 void viafb_lock_crt(void);
 908 void viafb_unlock_crt(void);
 909 void viafb_load_fetch_count_reg(int h_addr, int bpp_byte, int set_iga);
 910 void viafb_write_regx(struct io_reg RegTable[], int ItemNum);
 911 u32 viafb_get_clk_value(int clk);
 912 void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active);
 913 void viafb_set_dpa_gfx(int output_interface, struct GFX_DPA_SETTING\
 914                                         *p_gfx_dpa_setting);
 915
 916 int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp,
 917         struct VideoModeTable *vmode_tbl1, int video_bpp1);
 918 void viafb_fill_var_timing_info(struct fb_var_screeninfo *var, int refresh,
 919         struct VideoModeTable *vmode_tbl);
 920 void __devinit viafb_init_chip_info(int chip_type);
 921 void __devinit viafb_init_dac(int set_iga);
 922 int viafb_get_pixclock(int hres, int vres, int vmode_refresh);
 923 int viafb_get_refresh(int hres, int vres, u32 float_refresh);
 924 void viafb_update_device_setting(int hres, int vres, int bpp,
 925                            int vmode_refresh, int flag);
 926
 927 void viafb_set_iga_path(void);
 928 void viafb_set_primary_color_register(u8 index, u8 red, u8 green, u8 blue);
 929 void viafb_set_secondary_color_register(u8 index, u8 red, u8 green, u8 blue);
 930 void viafb_get_fb_info(unsigned int *fb_base, unsigned int *fb_len);
 931
 932 #endif /* __HW_H__ */