drivers/video/via/hw.c

   1 /*
   2  * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
   3  * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
   4
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public
   7  * License as published by the Free Software Foundation;
   8  * either version 2, or (at your option) any later version.
   9
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
  12  * the implied warranty of MERCHANTABILITY or FITNESS FOR
  13  * A PARTICULAR PURPOSE.See the GNU General Public License
  14  * for more details.
  15
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc.,
  19  * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  20  */
  21
  22 #include "global.h"
  23
  24 static struct pll_map pll_value[] = {
  25         {CLK_25_175M, CLE266_PLL_25_175M, K800_PLL_25_175M,
  26          CX700_25_175M, VX855_25_175M},
  27         {CLK_29_581M, CLE266_PLL_29_581M, K800_PLL_29_581M,
  28          CX700_29_581M, VX855_29_581M},
  29         {CLK_26_880M, CLE266_PLL_26_880M, K800_PLL_26_880M,
  30          CX700_26_880M, VX855_26_880M},
  31         {CLK_31_490M, CLE266_PLL_31_490M, K800_PLL_31_490M,
  32          CX700_31_490M, VX855_31_490M},
  33         {CLK_31_500M, CLE266_PLL_31_500M, K800_PLL_31_500M,
  34          CX700_31_500M, VX855_31_500M},
  35         {CLK_31_728M, CLE266_PLL_31_728M, K800_PLL_31_728M,
  36          CX700_31_728M, VX855_31_728M},
  37         {CLK_32_668M, CLE266_PLL_32_668M, K800_PLL_32_668M,
  38          CX700_32_668M, VX855_32_668M},
  39         {CLK_36_000M, CLE266_PLL_36_000M, K800_PLL_36_000M,
  40          CX700_36_000M, VX855_36_000M},
  41         {CLK_40_000M, CLE266_PLL_40_000M, K800_PLL_40_000M,
  42          CX700_40_000M, VX855_40_000M},
  43         {CLK_41_291M, CLE266_PLL_41_291M, K800_PLL_41_291M,
  44          CX700_41_291M, VX855_41_291M},
  45         {CLK_43_163M, CLE266_PLL_43_163M, K800_PLL_43_163M,
  46          CX700_43_163M, VX855_43_163M},
  47         {CLK_45_250M, CLE266_PLL_45_250M, K800_PLL_45_250M,
  48          CX700_45_250M, VX855_45_250M},
  49         {CLK_46_000M, CLE266_PLL_46_000M, K800_PLL_46_000M,
  50          CX700_46_000M, VX855_46_000M},
  51         {CLK_46_996M, CLE266_PLL_46_996M, K800_PLL_46_996M,
  52          CX700_46_996M, VX855_46_996M},
  53         {CLK_48_000M, CLE266_PLL_48_000M, K800_PLL_48_000M,
  54          CX700_48_000M, VX855_48_000M},
  55         {CLK_48_875M, CLE266_PLL_48_875M, K800_PLL_48_875M,
  56          CX700_48_875M, VX855_48_875M},
  57         {CLK_49_500M, CLE266_PLL_49_500M, K800_PLL_49_500M,
  58          CX700_49_500M, VX855_49_500M},
  59         {CLK_52_406M, CLE266_PLL_52_406M, K800_PLL_52_406M,
  60          CX700_52_406M, VX855_52_406M},
  61         {CLK_52_977M, CLE266_PLL_52_977M, K800_PLL_52_977M,
  62          CX700_52_977M, VX855_52_977M},
  63         {CLK_56_250M, CLE266_PLL_56_250M, K800_PLL_56_250M,
  64          CX700_56_250M, VX855_56_250M},
  65         {CLK_60_466M, CLE266_PLL_60_466M, K800_PLL_60_466M,
  66          CX700_60_466M, VX855_60_466M},
  67         {CLK_61_500M, CLE266_PLL_61_500M, K800_PLL_61_500M,
  68          CX700_61_500M, VX855_61_500M},
  69         {CLK_65_000M, CLE266_PLL_65_000M, K800_PLL_65_000M,
  70          CX700_65_000M, VX855_65_000M},
  71         {CLK_65_178M, CLE266_PLL_65_178M, K800_PLL_65_178M,
  72          CX700_65_178M, VX855_65_178M},
  73         {CLK_66_750M, CLE266_PLL_66_750M, K800_PLL_66_750M,
  74          CX700_66_750M, VX855_66_750M},
  75         {CLK_68_179M, CLE266_PLL_68_179M, K800_PLL_68_179M,
  76          CX700_68_179M, VX855_68_179M},
  77         {CLK_69_924M, CLE266_PLL_69_924M, K800_PLL_69_924M,
  78          CX700_69_924M, VX855_69_924M},
  79         {CLK_70_159M, CLE266_PLL_70_159M, K800_PLL_70_159M,
  80          CX700_70_159M, VX855_70_159M},
  81         {CLK_72_000M, CLE266_PLL_72_000M, K800_PLL_72_000M,
  82          CX700_72_000M, VX855_72_000M},
  83         {CLK_78_750M, CLE266_PLL_78_750M, K800_PLL_78_750M,
  84          CX700_78_750M, VX855_78_750M},
  85         {CLK_80_136M, CLE266_PLL_80_136M, K800_PLL_80_136M,
  86          CX700_80_136M, VX855_80_136M},
  87         {CLK_83_375M, CLE266_PLL_83_375M, K800_PLL_83_375M,
  88          CX700_83_375M, VX855_83_375M},
  89         {CLK_83_950M, CLE266_PLL_83_950M, K800_PLL_83_950M,
  90          CX700_83_950M, VX855_83_950M},
  91         {CLK_84_750M, CLE266_PLL_84_750M, K800_PLL_84_750M,
  92          CX700_84_750M, VX855_84_750M},
  93         {CLK_85_860M, CLE266_PLL_85_860M, K800_PLL_85_860M,
  94          CX700_85_860M, VX855_85_860M},
  95         {CLK_88_750M, CLE266_PLL_88_750M, K800_PLL_88_750M,
  96          CX700_88_750M, VX855_88_750M},
  97         {CLK_94_500M, CLE266_PLL_94_500M, K800_PLL_94_500M,
  98          CX700_94_500M, VX855_94_500M},
  99         {CLK_97_750M, CLE266_PLL_97_750M, K800_PLL_97_750M,
 100          CX700_97_750M, VX855_97_750M},
 101         {CLK_101_000M, CLE266_PLL_101_000M, K800_PLL_101_000M,
 102          CX700_101_000M, VX855_101_000M},
 103         {CLK_106_500M, CLE266_PLL_106_500M, K800_PLL_106_500M,
 104          CX700_106_500M, VX855_106_500M},
 105         {CLK_108_000M, CLE266_PLL_108_000M, K800_PLL_108_000M,
 106          CX700_108_000M, VX855_108_000M},
 107         {CLK_113_309M, CLE266_PLL_113_309M, K800_PLL_113_309M,
 108          CX700_113_309M, VX855_113_309M},
 109         {CLK_118_840M, CLE266_PLL_118_840M, K800_PLL_118_840M,
 110          CX700_118_840M, VX855_118_840M},
 111         {CLK_119_000M, CLE266_PLL_119_000M, K800_PLL_119_000M,
 112          CX700_119_000M, VX855_119_000M},
 113         {CLK_121_750M, CLE266_PLL_121_750M, K800_PLL_121_750M,
 114          CX700_121_750M, 0},
 115         {CLK_125_104M, CLE266_PLL_125_104M, K800_PLL_125_104M,
 116          CX700_125_104M, 0},
 117         {CLK_133_308M, CLE266_PLL_133_308M, K800_PLL_133_308M,
 118          CX700_133_308M, 0},
 119         {CLK_135_000M, CLE266_PLL_135_000M, K800_PLL_135_000M,
 120          CX700_135_000M, VX855_135_000M},
 121         {CLK_136_700M, CLE266_PLL_136_700M, K800_PLL_136_700M,
 122          CX700_136_700M, VX855_136_700M},
 123         {CLK_138_400M, CLE266_PLL_138_400M, K800_PLL_138_400M,
 124          CX700_138_400M, VX855_138_400M},
 125         {CLK_146_760M, CLE266_PLL_146_760M, K800_PLL_146_760M,
 126          CX700_146_760M, VX855_146_760M},
 127         {CLK_153_920M, CLE266_PLL_153_920M, K800_PLL_153_920M,
 128          CX700_153_920M, VX855_153_920M},
 129         {CLK_156_000M, CLE266_PLL_156_000M, K800_PLL_156_000M,
 130          CX700_156_000M, VX855_156_000M},
 131         {CLK_157_500M, CLE266_PLL_157_500M, K800_PLL_157_500M,
 132          CX700_157_500M, VX855_157_500M},
 133         {CLK_162_000M, CLE266_PLL_162_000M, K800_PLL_162_000M,
 134          CX700_162_000M, VX855_162_000M},
 135         {CLK_187_000M, CLE266_PLL_187_000M, K800_PLL_187_000M,
 136          CX700_187_000M, VX855_187_000M},
 137         {CLK_193_295M, CLE266_PLL_193_295M, K800_PLL_193_295M,
 138          CX700_193_295M, VX855_193_295M},
 139         {CLK_202_500M, CLE266_PLL_202_500M, K800_PLL_202_500M,
 140          CX700_202_500M, VX855_202_500M},
 141         {CLK_204_000M, CLE266_PLL_204_000M, K800_PLL_204_000M,
 142          CX700_204_000M, VX855_204_000M},
 143         {CLK_218_500M, CLE266_PLL_218_500M, K800_PLL_218_500M,
 144          CX700_218_500M, VX855_218_500M},
 145         {CLK_234_000M, CLE266_PLL_234_000M, K800_PLL_234_000M,
 146          CX700_234_000M, VX855_234_000M},
 147         {CLK_267_250M, CLE266_PLL_267_250M, K800_PLL_267_250M,
 148          CX700_267_250M, VX855_267_250M},
 149         {CLK_297_500M, CLE266_PLL_297_500M, K800_PLL_297_500M,
 150          CX700_297_500M, VX855_297_500M},
 151         {CLK_74_481M, CLE266_PLL_74_481M, K800_PLL_74_481M,
 152          CX700_74_481M, VX855_74_481M},
 153         {CLK_172_798M, CLE266_PLL_172_798M, K800_PLL_172_798M,
 154          CX700_172_798M, VX855_172_798M},
 155         {CLK_122_614M, CLE266_PLL_122_614M, K800_PLL_122_614M,
 156          CX700_122_614M, VX855_122_614M},
 157         {CLK_74_270M, CLE266_PLL_74_270M, K800_PLL_74_270M,
 158          CX700_74_270M, 0},
 159         {CLK_148_500M, CLE266_PLL_148_500M, K800_PLL_148_500M,
 160          CX700_148_500M, VX855_148_500M}
 161 };
 162
 163 static struct fifo_depth_select display_fifo_depth_reg = {
 164         /* IGA1 FIFO Depth_Select */
 165         {IGA1_FIFO_DEPTH_SELECT_REG_NUM, {{SR17, 0, 7} } },
 166         /* IGA2 FIFO Depth_Select */
 167         {IGA2_FIFO_DEPTH_SELECT_REG_NUM,
 168          {{CR68, 4, 7}, {CR94, 7, 7}, {CR95, 7, 7} } }
 169 };
 170
 171 static struct fifo_threshold_select fifo_threshold_select_reg = {
 172         /* IGA1 FIFO Threshold Select */
 173         {IGA1_FIFO_THRESHOLD_REG_NUM, {{SR16, 0, 5}, {SR16, 7, 7} } },
 174         /* IGA2 FIFO Threshold Select */
 175         {IGA2_FIFO_THRESHOLD_REG_NUM, {{CR68, 0, 3}, {CR95, 4, 6} } }
 176 };
 177
 178 static struct fifo_high_threshold_select fifo_high_threshold_select_reg = {
 179         /* IGA1 FIFO High Threshold Select */
 180         {IGA1_FIFO_HIGH_THRESHOLD_REG_NUM, {{SR18, 0, 5}, {SR18, 7, 7} } },
 181         /* IGA2 FIFO High Threshold Select */
 182         {IGA2_FIFO_HIGH_THRESHOLD_REG_NUM, {{CR92, 0, 3}, {CR95, 0, 2} } }
 183 };
 184
 185 static struct display_queue_expire_num display_queue_expire_num_reg = {
 186         /* IGA1 Display Queue Expire Num */
 187         {IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{SR22, 0, 4} } },
 188         /* IGA2 Display Queue Expire Num */
 189         {IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{CR94, 0, 6} } }
 190 };
 191
 192 /* Definition Fetch Count Registers*/
 193 static struct fetch_count fetch_count_reg = {
 194         /* IGA1 Fetch Count Register */
 195         {IGA1_FETCH_COUNT_REG_NUM, {{SR1C, 0, 7}, {SR1D, 0, 1} } },
 196         /* IGA2 Fetch Count Register */
 197         {IGA2_FETCH_COUNT_REG_NUM, {{CR65, 0, 7}, {CR67, 2, 3} } }
 198 };
 199
 200 static struct iga1_crtc_timing iga1_crtc_reg = {
 201         /* IGA1 Horizontal Total */
 202         {IGA1_HOR_TOTAL_REG_NUM, {{CR00, 0, 7}, {CR36, 3, 3} } },
 203         /* IGA1 Horizontal Addressable Video */
 204         {IGA1_HOR_ADDR_REG_NUM, {{CR01, 0, 7} } },
 205         /* IGA1 Horizontal Blank Start */
 206         {IGA1_HOR_BLANK_START_REG_NUM, {{CR02, 0, 7} } },
 207         /* IGA1 Horizontal Blank End */
 208         {IGA1_HOR_BLANK_END_REG_NUM,
 209          {{CR03, 0, 4}, {CR05, 7, 7}, {CR33, 5, 5} } },
 210         /* IGA1 Horizontal Sync Start */
 211         {IGA1_HOR_SYNC_START_REG_NUM, {{CR04, 0, 7}, {CR33, 4, 4} } },
 212         /* IGA1 Horizontal Sync End */
 213         {IGA1_HOR_SYNC_END_REG_NUM, {{CR05, 0, 4} } },
 214         /* IGA1 Vertical Total */
 215         {IGA1_VER_TOTAL_REG_NUM,
 216          {{CR06, 0, 7}, {CR07, 0, 0}, {CR07, 5, 5}, {CR35, 0, 0} } },
 217         /* IGA1 Vertical Addressable Video */
 218         {IGA1_VER_ADDR_REG_NUM,
 219          {{CR12, 0, 7}, {CR07, 1, 1}, {CR07, 6, 6}, {CR35, 2, 2} } },
 220         /* IGA1 Vertical Blank Start */
 221         {IGA1_VER_BLANK_START_REG_NUM,
 222          {{CR15, 0, 7}, {CR07, 3, 3}, {CR09, 5, 5}, {CR35, 3, 3} } },
 223         /* IGA1 Vertical Blank End */
 224         {IGA1_VER_BLANK_END_REG_NUM, {{CR16, 0, 7} } },
 225         /* IGA1 Vertical Sync Start */
 226         {IGA1_VER_SYNC_START_REG_NUM,
 227          {{CR10, 0, 7}, {CR07, 2, 2}, {CR07, 7, 7}, {CR35, 1, 1} } },
 228         /* IGA1 Vertical Sync End */
 229         {IGA1_VER_SYNC_END_REG_NUM, {{CR11, 0, 3} } }
 230 };
 231
 232 static struct iga2_crtc_timing iga2_crtc_reg = {
 233         /* IGA2 Horizontal Total */
 234         {IGA2_HOR_TOTAL_REG_NUM, {{CR50, 0, 7}, {CR55, 0, 3} } },
 235         /* IGA2 Horizontal Addressable Video */
 236         {IGA2_HOR_ADDR_REG_NUM, {{CR51, 0, 7}, {CR55, 4, 6} } },
 237         /* IGA2 Horizontal Blank Start */
 238         {IGA2_HOR_BLANK_START_REG_NUM, {{CR52, 0, 7}, {CR54, 0, 2} } },
 239         /* IGA2 Horizontal Blank End */
 240         {IGA2_HOR_BLANK_END_REG_NUM,
 241          {{CR53, 0, 7}, {CR54, 3, 5}, {CR5D, 6, 6} } },
 242         /* IGA2 Horizontal Sync Start */
 243         {IGA2_HOR_SYNC_START_REG_NUM,
 244          {{CR56, 0, 7}, {CR54, 6, 7}, {CR5C, 7, 7}, {CR5D, 7, 7} } },
 245         /* IGA2 Horizontal Sync End */
 246         {IGA2_HOR_SYNC_END_REG_NUM, {{CR57, 0, 7}, {CR5C, 6, 6} } },
 247         /* IGA2 Vertical Total */
 248         {IGA2_VER_TOTAL_REG_NUM, {{CR58, 0, 7}, {CR5D, 0, 2} } },
 249         /* IGA2 Vertical Addressable Video */
 250         {IGA2_VER_ADDR_REG_NUM, {{CR59, 0, 7}, {CR5D, 3, 5} } },
 251         /* IGA2 Vertical Blank Start */
 252         {IGA2_VER_BLANK_START_REG_NUM, {{CR5A, 0, 7}, {CR5C, 0, 2} } },
 253         /* IGA2 Vertical Blank End */
 254         {IGA2_VER_BLANK_END_REG_NUM, {{CR5B, 0, 7}, {CR5C, 3, 5} } },
 255         /* IGA2 Vertical Sync Start */
 256         {IGA2_VER_SYNC_START_REG_NUM, {{CR5E, 0, 7}, {CR5F, 5, 7} } },
 257         /* IGA2 Vertical Sync End */
 258         {IGA2_VER_SYNC_END_REG_NUM, {{CR5F, 0, 4} } }
 259 };
 260
 261 static struct rgbLUT palLUT_table[] = {
 262         /* {R,G,B} */
 263         /* Index 0x00~0x03 */
 264         {0x00, 0x00, 0x00}, {0x00, 0x00, 0x2A}, {0x00, 0x2A, 0x00}, {0x00,
 265                                                                      0x2A,
 266                                                                      0x2A},
 267         /* Index 0x04~0x07 */
 268         {0x2A, 0x00, 0x00}, {0x2A, 0x00, 0x2A}, {0x2A, 0x15, 0x00}, {0x2A,
 269                                                                      0x2A,
 270                                                                      0x2A},
 271         /* Index 0x08~0x0B */
 272         {0x15, 0x15, 0x15}, {0x15, 0x15, 0x3F}, {0x15, 0x3F, 0x15}, {0x15,
 273                                                                      0x3F,
 274                                                                      0x3F},
 275         /* Index 0x0C~0x0F */
 276         {0x3F, 0x15, 0x15}, {0x3F, 0x15, 0x3F}, {0x3F, 0x3F, 0x15}, {0x3F,
 277                                                                      0x3F,
 278                                                                      0x3F},
 279         /* Index 0x10~0x13 */
 280         {0x00, 0x00, 0x00}, {0x05, 0x05, 0x05}, {0x08, 0x08, 0x08}, {0x0B,
 281                                                                      0x0B,
 282                                                                      0x0B},
 283         /* Index 0x14~0x17 */
 284         {0x0E, 0x0E, 0x0E}, {0x11, 0x11, 0x11}, {0x14, 0x14, 0x14}, {0x18,
 285                                                                      0x18,
 286                                                                      0x18},
 287         /* Index 0x18~0x1B */
 288         {0x1C, 0x1C, 0x1C}, {0x20, 0x20, 0x20}, {0x24, 0x24, 0x24}, {0x28,
 289                                                                      0x28,
 290                                                                      0x28},
 291         /* Index 0x1C~0x1F */
 292         {0x2D, 0x2D, 0x2D}, {0x32, 0x32, 0x32}, {0x38, 0x38, 0x38}, {0x3F,
 293                                                                      0x3F,
 294                                                                      0x3F},
 295         /* Index 0x20~0x23 */
 296         {0x00, 0x00, 0x3F}, {0x10, 0x00, 0x3F}, {0x1F, 0x00, 0x3F}, {0x2F,
 297                                                                      0x00,
 298                                                                      0x3F},
 299         /* Index 0x24~0x27 */
 300         {0x3F, 0x00, 0x3F}, {0x3F, 0x00, 0x2F}, {0x3F, 0x00, 0x1F}, {0x3F,
 301                                                                      0x00,
 302                                                                      0x10},
 303         /* Index 0x28~0x2B */
 304         {0x3F, 0x00, 0x00}, {0x3F, 0x10, 0x00}, {0x3F, 0x1F, 0x00}, {0x3F,
 305                                                                      0x2F,
 306                                                                      0x00},
 307         /* Index 0x2C~0x2F */
 308         {0x3F, 0x3F, 0x00}, {0x2F, 0x3F, 0x00}, {0x1F, 0x3F, 0x00}, {0x10,
 309                                                                      0x3F,
 310                                                                      0x00},
 311         /* Index 0x30~0x33 */
 312         {0x00, 0x3F, 0x00}, {0x00, 0x3F, 0x10}, {0x00, 0x3F, 0x1F}, {0x00,
 313                                                                      0x3F,
 314                                                                      0x2F},
 315         /* Index 0x34~0x37 */
 316         {0x00, 0x3F, 0x3F}, {0x00, 0x2F, 0x3F}, {0x00, 0x1F, 0x3F}, {0x00,
 317                                                                      0x10,
 318                                                                      0x3F},
 319         /* Index 0x38~0x3B */
 320         {0x1F, 0x1F, 0x3F}, {0x27, 0x1F, 0x3F}, {0x2F, 0x1F, 0x3F}, {0x37,
 321                                                                      0x1F,
 322                                                                      0x3F},
 323         /* Index 0x3C~0x3F */
 324         {0x3F, 0x1F, 0x3F}, {0x3F, 0x1F, 0x37}, {0x3F, 0x1F, 0x2F}, {0x3F,
 325                                                                      0x1F,
 326                                                                      0x27},
 327         /* Index 0x40~0x43 */
 328         {0x3F, 0x1F, 0x1F}, {0x3F, 0x27, 0x1F}, {0x3F, 0x2F, 0x1F}, {0x3F,
 329                                                                      0x3F,
 330                                                                      0x1F},
 331         /* Index 0x44~0x47 */
 332         {0x3F, 0x3F, 0x1F}, {0x37, 0x3F, 0x1F}, {0x2F, 0x3F, 0x1F}, {0x27,
 333                                                                      0x3F,
 334                                                                      0x1F},
 335         /* Index 0x48~0x4B */
 336         {0x1F, 0x3F, 0x1F}, {0x1F, 0x3F, 0x27}, {0x1F, 0x3F, 0x2F}, {0x1F,
 337                                                                      0x3F,
 338                                                                      0x37},
 339         /* Index 0x4C~0x4F */
 340         {0x1F, 0x3F, 0x3F}, {0x1F, 0x37, 0x3F}, {0x1F, 0x2F, 0x3F}, {0x1F,
 341                                                                      0x27,
 342                                                                      0x3F},
 343         /* Index 0x50~0x53 */
 344         {0x2D, 0x2D, 0x3F}, {0x31, 0x2D, 0x3F}, {0x36, 0x2D, 0x3F}, {0x3A,
 345                                                                      0x2D,
 346                                                                      0x3F},
 347         /* Index 0x54~0x57 */
 348         {0x3F, 0x2D, 0x3F}, {0x3F, 0x2D, 0x3A}, {0x3F, 0x2D, 0x36}, {0x3F,
 349                                                                      0x2D,
 350                                                                      0x31},
 351         /* Index 0x58~0x5B */
 352         {0x3F, 0x2D, 0x2D}, {0x3F, 0x31, 0x2D}, {0x3F, 0x36, 0x2D}, {0x3F,
 353                                                                      0x3A,
 354                                                                      0x2D},
 355         /* Index 0x5C~0x5F */
 356         {0x3F, 0x3F, 0x2D}, {0x3A, 0x3F, 0x2D}, {0x36, 0x3F, 0x2D}, {0x31,
 357                                                                      0x3F,
 358                                                                      0x2D},
 359         /* Index 0x60~0x63 */
 360         {0x2D, 0x3F, 0x2D}, {0x2D, 0x3F, 0x31}, {0x2D, 0x3F, 0x36}, {0x2D,
 361                                                                      0x3F,
 362                                                                      0x3A},
 363         /* Index 0x64~0x67 */
 364         {0x2D, 0x3F, 0x3F}, {0x2D, 0x3A, 0x3F}, {0x2D, 0x36, 0x3F}, {0x2D,
 365                                                                      0x31,
 366                                                                      0x3F},
 367         /* Index 0x68~0x6B */
 368         {0x00, 0x00, 0x1C}, {0x07, 0x00, 0x1C}, {0x0E, 0x00, 0x1C}, {0x15,
 369                                                                      0x00,
 370                                                                      0x1C},
 371         /* Index 0x6C~0x6F */
 372         {0x1C, 0x00, 0x1C}, {0x1C, 0x00, 0x15}, {0x1C, 0x00, 0x0E}, {0x1C,
 373                                                                      0x00,
 374                                                                      0x07},
 375         /* Index 0x70~0x73 */
 376         {0x1C, 0x00, 0x00}, {0x1C, 0x07, 0x00}, {0x1C, 0x0E, 0x00}, {0x1C,
 377                                                                      0x15,
 378                                                                      0x00},
 379         /* Index 0x74~0x77 */
 380         {0x1C, 0x1C, 0x00}, {0x15, 0x1C, 0x00}, {0x0E, 0x1C, 0x00}, {0x07,
 381                                                                      0x1C,
 382                                                                      0x00},
 383         /* Index 0x78~0x7B */
 384         {0x00, 0x1C, 0x00}, {0x00, 0x1C, 0x07}, {0x00, 0x1C, 0x0E}, {0x00,
 385                                                                      0x1C,
 386                                                                      0x15},
 387         /* Index 0x7C~0x7F */
 388         {0x00, 0x1C, 0x1C}, {0x00, 0x15, 0x1C}, {0x00, 0x0E, 0x1C}, {0x00,
 389                                                                      0x07,
 390                                                                      0x1C},
 391         /* Index 0x80~0x83 */
 392         {0x0E, 0x0E, 0x1C}, {0x11, 0x0E, 0x1C}, {0x15, 0x0E, 0x1C}, {0x18,
 393                                                                      0x0E,
 394                                                                      0x1C},
 395         /* Index 0x84~0x87 */
 396         {0x1C, 0x0E, 0x1C}, {0x1C, 0x0E, 0x18}, {0x1C, 0x0E, 0x15}, {0x1C,
 397                                                                      0x0E,
 398                                                                      0x11},
 399         /* Index 0x88~0x8B */
 400         {0x1C, 0x0E, 0x0E}, {0x1C, 0x11, 0x0E}, {0x1C, 0x15, 0x0E}, {0x1C,
 401                                                                      0x18,
 402                                                                      0x0E},
 403         /* Index 0x8C~0x8F */
 404         {0x1C, 0x1C, 0x0E}, {0x18, 0x1C, 0x0E}, {0x15, 0x1C, 0x0E}, {0x11,
 405                                                                      0x1C,
 406                                                                      0x0E},
 407         /* Index 0x90~0x93 */
 408         {0x0E, 0x1C, 0x0E}, {0x0E, 0x1C, 0x11}, {0x0E, 0x1C, 0x15}, {0x0E,
 409                                                                      0x1C,
 410                                                                      0x18},
 411         /* Index 0x94~0x97 */
 412         {0x0E, 0x1C, 0x1C}, {0x0E, 0x18, 0x1C}, {0x0E, 0x15, 0x1C}, {0x0E,
 413                                                                      0x11,
 414                                                                      0x1C},
 415         /* Index 0x98~0x9B */
 416         {0x14, 0x14, 0x1C}, {0x16, 0x14, 0x1C}, {0x18, 0x14, 0x1C}, {0x1A,
 417                                                                      0x14,
 418                                                                      0x1C},
 419         /* Index 0x9C~0x9F */
 420         {0x1C, 0x14, 0x1C}, {0x1C, 0x14, 0x1A}, {0x1C, 0x14, 0x18}, {0x1C,
 421                                                                      0x14,
 422                                                                      0x16},
 423         /* Index 0xA0~0xA3 */
 424         {0x1C, 0x14, 0x14}, {0x1C, 0x16, 0x14}, {0x1C, 0x18, 0x14}, {0x1C,
 425                                                                      0x1A,
 426                                                                      0x14},
 427         /* Index 0xA4~0xA7 */
 428         {0x1C, 0x1C, 0x14}, {0x1A, 0x1C, 0x14}, {0x18, 0x1C, 0x14}, {0x16,
 429                                                                      0x1C,
 430                                                                      0x14},
 431         /* Index 0xA8~0xAB */
 432         {0x14, 0x1C, 0x14}, {0x14, 0x1C, 0x16}, {0x14, 0x1C, 0x18}, {0x14,
 433                                                                      0x1C,
 434                                                                      0x1A},
 435         /* Index 0xAC~0xAF */
 436         {0x14, 0x1C, 0x1C}, {0x14, 0x1A, 0x1C}, {0x14, 0x18, 0x1C}, {0x14,
 437                                                                      0x16,
 438                                                                      0x1C},
 439         /* Index 0xB0~0xB3 */
 440         {0x00, 0x00, 0x10}, {0x04, 0x00, 0x10}, {0x08, 0x00, 0x10}, {0x0C,
 441                                                                      0x00,
 442                                                                      0x10},
 443         /* Index 0xB4~0xB7 */
 444         {0x10, 0x00, 0x10}, {0x10, 0x00, 0x0C}, {0x10, 0x00, 0x08}, {0x10,
 445                                                                      0x00,
 446                                                                      0x04},
 447         /* Index 0xB8~0xBB */
 448         {0x10, 0x00, 0x00}, {0x10, 0x04, 0x00}, {0x10, 0x08, 0x00}, {0x10,
 449                                                                      0x0C,
 450                                                                      0x00},
 451         /* Index 0xBC~0xBF */
 452         {0x10, 0x10, 0x00}, {0x0C, 0x10, 0x00}, {0x08, 0x10, 0x00}, {0x04,
 453                                                                      0x10,
 454                                                                      0x00},
 455         /* Index 0xC0~0xC3 */
 456         {0x00, 0x10, 0x00}, {0x00, 0x10, 0x04}, {0x00, 0x10, 0x08}, {0x00,
 457                                                                      0x10,
 458                                                                      0x0C},
 459         /* Index 0xC4~0xC7 */
 460         {0x00, 0x10, 0x10}, {0x00, 0x0C, 0x10}, {0x00, 0x08, 0x10}, {0x00,
 461                                                                      0x04,
 462                                                                      0x10},
 463         /* Index 0xC8~0xCB */
 464         {0x08, 0x08, 0x10}, {0x0A, 0x08, 0x10}, {0x0C, 0x08, 0x10}, {0x0E,
 465                                                                      0x08,
 466                                                                      0x10},
 467         /* Index 0xCC~0xCF */
 468         {0x10, 0x08, 0x10}, {0x10, 0x08, 0x0E}, {0x10, 0x08, 0x0C}, {0x10,
 469                                                                      0x08,
 470                                                                      0x0A},
 471         /* Index 0xD0~0xD3 */
 472         {0x10, 0x08, 0x08}, {0x10, 0x0A, 0x08}, {0x10, 0x0C, 0x08}, {0x10,
 473                                                                      0x0E,
 474                                                                      0x08},
 475         /* Index 0xD4~0xD7 */
 476         {0x10, 0x10, 0x08}, {0x0E, 0x10, 0x08}, {0x0C, 0x10, 0x08}, {0x0A,
 477                                                                      0x10,
 478                                                                      0x08},
 479         /* Index 0xD8~0xDB */
 480         {0x08, 0x10, 0x08}, {0x08, 0x10, 0x0A}, {0x08, 0x10, 0x0C}, {0x08,
 481                                                                      0x10,
 482                                                                      0x0E},
 483         /* Index 0xDC~0xDF */
 484         {0x08, 0x10, 0x10}, {0x08, 0x0E, 0x10}, {0x08, 0x0C, 0x10}, {0x08,
 485                                                                      0x0A,
 486                                                                      0x10},
 487         /* Index 0xE0~0xE3 */
 488         {0x0B, 0x0B, 0x10}, {0x0C, 0x0B, 0x10}, {0x0D, 0x0B, 0x10}, {0x0F,
 489                                                                      0x0B,
 490                                                                      0x10},
 491         /* Index 0xE4~0xE7 */
 492         {0x10, 0x0B, 0x10}, {0x10, 0x0B, 0x0F}, {0x10, 0x0B, 0x0D}, {0x10,
 493                                                                      0x0B,
 494                                                                      0x0C},
 495         /* Index 0xE8~0xEB */
 496         {0x10, 0x0B, 0x0B}, {0x10, 0x0C, 0x0B}, {0x10, 0x0D, 0x0B}, {0x10,
 497                                                                      0x0F,
 498                                                                      0x0B},
 499         /* Index 0xEC~0xEF */
 500         {0x10, 0x10, 0x0B}, {0x0F, 0x10, 0x0B}, {0x0D, 0x10, 0x0B}, {0x0C,
 501                                                                      0x10,
 502                                                                      0x0B},
 503         /* Index 0xF0~0xF3 */
 504         {0x0B, 0x10, 0x0B}, {0x0B, 0x10, 0x0C}, {0x0B, 0x10, 0x0D}, {0x0B,
 505                                                                      0x10,
 506                                                                      0x0F},
 507         /* Index 0xF4~0xF7 */
 508         {0x0B, 0x10, 0x10}, {0x0B, 0x0F, 0x10}, {0x0B, 0x0D, 0x10}, {0x0B,
 509                                                                      0x0C,
 510                                                                      0x10},
 511         /* Index 0xF8~0xFB */
 512         {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00,
 513                                                                      0x00,
 514                                                                      0x00},
 515         /* Index 0xFC~0xFF */
 516         {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00,
 517                                                                      0x00,
 518                                                                      0x00}
 519 };
 520
 521 static void set_crt_output_path(int set_iga);
 522 static void dvi_patch_skew_dvp0(void);
 523 static void dvi_patch_skew_dvp1(void);
 524 static void dvi_patch_skew_dvp_low(void);
 525 static void set_dvi_output_path(int set_iga, int output_interface);
 526 static void set_lcd_output_path(int set_iga, int output_interface);
 527 static void load_fix_bit_crtc_reg(void);
 528 static void init_gfx_chip_info(struct pci_dev *pdev,
 529                                 const struct pci_device_id *pdi);
 530 static void init_tmds_chip_info(void);
 531 static void init_lvds_chip_info(void);
 532 static void device_screen_off(void);
 533 static void device_screen_on(void);
 534 static void set_display_channel(void);
 535 static void device_off(void);
 536 static void device_on(void);
 537 static void enable_second_display_channel(void);
 538 static void disable_second_display_channel(void);
 539
 540 void viafb_write_reg(u8 index, u16 io_port, u8 data)
 541 {
 542         outb(index, io_port);
 543         outb(data, io_port + 1);
 544         /*DEBUG_MSG(KERN_INFO "\nIndex=%2d Value=%2d", index, data); */
 545 }
 546 u8 viafb_read_reg(int io_port, u8 index)
 547 {
 548         outb(index, io_port);
 549         return inb(io_port + 1);
 550 }
 551
 552 void viafb_lock_crt(void)
 553 {
 554         viafb_write_reg_mask(CR11, VIACR, BIT7, BIT7);
 555 }
 556
 557 void viafb_unlock_crt(void)
 558 {
 559         viafb_write_reg_mask(CR11, VIACR, 0, BIT7);
 560         viafb_write_reg_mask(CR47, VIACR, 0, BIT0);
 561 }
 562
 563 void viafb_write_reg_mask(u8 index, int io_port, u8 data, u8 mask)
 564 {
 565         u8 tmp;
 566
 567         outb(index, io_port);
 568         tmp = inb(io_port + 1);
 569         outb((data & mask) | (tmp & (~mask)), io_port + 1);
 570         /*DEBUG_MSG(KERN_INFO "\nIndex=%2d Value=%2d", index, tmp); */
 571 }
 572
 573 void write_dac_reg(u8 index, u8 r, u8 g, u8 b)
 574 {
 575         outb(index, LUT_INDEX_WRITE);
 576         outb(r, LUT_DATA);
 577         outb(g, LUT_DATA);
 578         outb(b, LUT_DATA);
 579 }
 580
 581 /*Set IGA path for each device*/
 582 void viafb_set_iga_path(void)
 583 {
 584
 585         if (viafb_SAMM_ON == 1) {
 586                 if (viafb_CRT_ON) {
 587                         if (viafb_primary_dev == CRT_Device)
 588                                 viaparinfo->crt_setting_info->iga_path = IGA1;
 589                         else
 590                                 viaparinfo->crt_setting_info->iga_path = IGA2;
 591                 }
 592
 593                 if (viafb_DVI_ON) {
 594                         if (viafb_primary_dev == DVI_Device)
 595                                 viaparinfo->tmds_setting_info->iga_path = IGA1;
 596                         else
 597                                 viaparinfo->tmds_setting_info->iga_path = IGA2;
 598                 }
 599
 600                 if (viafb_LCD_ON) {
 601                         if (viafb_primary_dev == LCD_Device) {
 602                                 if (viafb_dual_fb &&
 603                                         (viaparinfo->chip_info->gfx_chip_name ==
 604                                         UNICHROME_CLE266)) {
 605                                         viaparinfo->
 606                                         lvds_setting_info->iga_path = IGA2;
 607                                         viaparinfo->
 608                                         crt_setting_info->iga_path = IGA1;
 609                                         viaparinfo->
 610                                         tmds_setting_info->iga_path = IGA1;
 611                                 } else
 612                                         viaparinfo->
 613                                         lvds_setting_info->iga_path = IGA1;
 614                         } else {
 615                                 viaparinfo->lvds_setting_info->iga_path = IGA2;
 616                         }
 617                 }
 618                 if (viafb_LCD2_ON) {
 619                         if (LCD2_Device == viafb_primary_dev)
 620                                 viaparinfo->lvds_setting_info2->iga_path = IGA1;
 621                         else
 622                                 viaparinfo->lvds_setting_info2->iga_path = IGA2;
 623                 }
 624         } else {
 625                 viafb_SAMM_ON = 0;
 626
 627                 if (viafb_CRT_ON && viafb_LCD_ON) {
 628                         viaparinfo->crt_setting_info->iga_path = IGA1;
 629                         viaparinfo->lvds_setting_info->iga_path = IGA2;
 630                 } else if (viafb_CRT_ON && viafb_DVI_ON) {
 631                         viaparinfo->crt_setting_info->iga_path = IGA1;
 632                         viaparinfo->tmds_setting_info->iga_path = IGA2;
 633                 } else if (viafb_LCD_ON && viafb_DVI_ON) {
 634                         viaparinfo->tmds_setting_info->iga_path = IGA1;
 635                         viaparinfo->lvds_setting_info->iga_path = IGA2;
 636                 } else if (viafb_LCD_ON && viafb_LCD2_ON) {
 637                         viaparinfo->lvds_setting_info->iga_path = IGA2;
 638                         viaparinfo->lvds_setting_info2->iga_path = IGA2;
 639                 } else if (viafb_CRT_ON) {
 640                         viaparinfo->crt_setting_info->iga_path = IGA1;
 641                 } else if (viafb_LCD_ON) {
 642                         viaparinfo->lvds_setting_info->iga_path = IGA2;
 643                 } else if (viafb_DVI_ON) {
 644                         viaparinfo->tmds_setting_info->iga_path = IGA1;
 645                 }
 646         }
 647 }
 648
 649 void viafb_set_primary_address(u32 addr)
 650 {
 651         DEBUG_MSG(KERN_DEBUG "viafb_set_primary_address(0x%08X)\n", addr);
 652         viafb_write_reg(CR0D, VIACR, addr & 0xFF);
 653         viafb_write_reg(CR0C, VIACR, (addr >> 8) & 0xFF);
 654         viafb_write_reg(CR34, VIACR, (addr >> 16) & 0xFF);
 655         viafb_write_reg_mask(CR48, VIACR, (addr >> 24) & 0x1F, 0x1F);
 656 }
 657
 658 void viafb_set_secondary_address(u32 addr)
 659 {
 660         DEBUG_MSG(KERN_DEBUG "viafb_set_secondary_address(0x%08X)\n", addr);
 661         /* secondary display supports only quadword aligned memory */
 662         viafb_write_reg_mask(CR62, VIACR, (addr >> 2) & 0xFE, 0xFE);
 663         viafb_write_reg(CR63, VIACR, (addr >> 10) & 0xFF);
 664         viafb_write_reg(CR64, VIACR, (addr >> 18) & 0xFF);
 665         viafb_write_reg_mask(CRA3, VIACR, (addr >> 26) & 0x07, 0x07);
 666 }
 667
 668 void viafb_set_primary_pitch(u32 pitch)
 669 {
 670         DEBUG_MSG(KERN_DEBUG "viafb_set_primary_pitch(0x%08X)\n", pitch);
 671         /* spec does not say that first adapter skips 3 bits but old
 672          * code did it and seems to be reasonable in analogy to 2nd adapter
 673          */
 674         pitch = pitch >> 3;
 675         viafb_write_reg(0x13, VIACR, pitch & 0xFF);
 676         viafb_write_reg_mask(0x35, VIACR, (pitch >> (8 - 5)) & 0xE0, 0xE0);
 677 }
 678
 679 void viafb_set_secondary_pitch(u32 pitch)
 680 {
 681         DEBUG_MSG(KERN_DEBUG "viafb_set_secondary_pitch(0x%08X)\n", pitch);
 682         pitch = pitch >> 3;
 683         viafb_write_reg(0x66, VIACR, pitch & 0xFF);
 684         viafb_write_reg_mask(0x67, VIACR, (pitch >> 8) & 0x03, 0x03);
 685         viafb_write_reg_mask(0x71, VIACR, (pitch >> (10 - 7)) & 0x80, 0x80);
 686 }
 687
 688 void viafb_set_primary_color_depth(u8 depth)
 689 {
 690         u8 value;
 691
 692         DEBUG_MSG(KERN_DEBUG "viafb_set_primary_color_depth(%d)\n", depth);
 693         switch (depth) {
 694         case 6:
 695                 value = 0x00;
 696                 break;
 697         case 16:
 698                 value = 0x14;
 699                 break;
 700         case 24:
 701                 value = 0x0C;
 702                 break;
 703         default:
 704                 printk(KERN_WARNING "viafb_set_primary_color_depth: "
 705                         "Unsupported depth: %d\n", depth);
 706                 return;
 707         }
 708
 709         viafb_write_reg_mask(0x15, VIASR, value, 0x1C);
 710 }
 711
 712 void viafb_set_secondary_color_depth(u8 depth)
 713 {
 714         u8 value;
 715
 716         DEBUG_MSG(KERN_DEBUG "viafb_set_secondary_color_depth(%d)\n", depth);
 717         switch (depth) {
 718         case 6:
 719                 value = 0x00;
 720                 break;
 721         case 16:
 722                 value = 0x40;
 723                 break;
 724         case 24:
 725                 value = 0xC0;
 726                 break;
 727         default:
 728                 printk(KERN_WARNING "viafb_set_secondary_color_depth: "
 729                         "Unsupported depth: %d\n", depth);
 730                 return;
 731         }
 732
 733         viafb_write_reg_mask(0x67, VIACR, value, 0xC0);
 734 }
 735
 736 void viafb_set_output_path(int device, int set_iga, int output_interface)
 737 {
 738         switch (device) {
 739         case DEVICE_CRT:
 740                 set_crt_output_path(set_iga);
 741                 break;
 742         case DEVICE_DVI:
 743                 set_dvi_output_path(set_iga, output_interface);
 744                 break;
 745         case DEVICE_LCD:
 746                 set_lcd_output_path(set_iga, output_interface);
 747                 break;
 748         }
 749 }
 750
 751 static void set_crt_output_path(int set_iga)
 752 {
 753         viafb_write_reg_mask(CR36, VIACR, 0x00, BIT4 + BIT5);
 754
 755         switch (set_iga) {
 756         case IGA1:
 757                 viafb_write_reg_mask(SR16, VIASR, 0x00, BIT6);
 758                 break;
 759         case IGA2:
 760         case IGA1_IGA2:
 761                 viafb_write_reg_mask(CR6A, VIACR, 0xC0, BIT6 + BIT7);
 762                 viafb_write_reg_mask(SR16, VIASR, 0x40, BIT6);
 763                 if (set_iga == IGA1_IGA2)
 764                         viafb_write_reg_mask(CR6B, VIACR, 0x08, BIT3);
 765                 break;
 766         }
 767 }
 768
 769 static void dvi_patch_skew_dvp0(void)
 770 {
 771         /* Reset data driving first: */
 772         viafb_write_reg_mask(SR1B, VIASR, 0, BIT1);
 773         viafb_write_reg_mask(SR2A, VIASR, 0, BIT4);
 774
 775         switch (viaparinfo->chip_info->gfx_chip_name) {
 776         case UNICHROME_P4M890:
 777                 {
 778                         if ((viaparinfo->tmds_setting_info->h_active == 1600) &&
 779                                 (viaparinfo->tmds_setting_info->v_active ==
 780                                 1200))
 781                                 viafb_write_reg_mask(CR96, VIACR, 0x03,
 782                                                BIT0 + BIT1 + BIT2);
 783                         else
 784                                 viafb_write_reg_mask(CR96, VIACR, 0x07,
 785                                                BIT0 + BIT1 + BIT2);
 786                         break;
 787                 }
 788
 789         case UNICHROME_P4M900:
 790                 {
 791                         viafb_write_reg_mask(CR96, VIACR, 0x07,
 792                                        BIT0 + BIT1 + BIT2 + BIT3);
 793                         viafb_write_reg_mask(SR1B, VIASR, 0x02, BIT1);
 794                         viafb_write_reg_mask(SR2A, VIASR, 0x10, BIT4);
 795                         break;
 796                 }
 797
 798         default:
 799                 {
 800                         break;
 801                 }
 802         }
 803 }
 804
 805 static void dvi_patch_skew_dvp1(void)
 806 {
 807         switch (viaparinfo->chip_info->gfx_chip_name) {
 808         case UNICHROME_CX700:
 809                 {
 810                         break;
 811                 }
 812
 813         default:
 814                 {
 815                         break;
 816                 }
 817         }
 818 }
 819
 820 static void dvi_patch_skew_dvp_low(void)
 821 {
 822         switch (viaparinfo->chip_info->gfx_chip_name) {
 823         case UNICHROME_K8M890:
 824                 {
 825                         viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1);
 826                         break;
 827                 }
 828
 829         case UNICHROME_P4M900:
 830                 {
 831                         viafb_write_reg_mask(CR99, VIACR, 0x08,
 832                                        BIT0 + BIT1 + BIT2 + BIT3);
 833                         break;
 834                 }
 835
 836         case UNICHROME_P4M890:
 837                 {
 838                         viafb_write_reg_mask(CR99, VIACR, 0x0F,
 839                                        BIT0 + BIT1 + BIT2 + BIT3);
 840                         break;
 841                 }
 842
 843         default:
 844                 {
 845                         break;
 846                 }
 847         }
 848 }
 849
 850 static void set_dvi_output_path(int set_iga, int output_interface)
 851 {
 852         switch (output_interface) {
 853         case INTERFACE_DVP0:
 854                 viafb_write_reg_mask(CR6B, VIACR, 0x01, BIT0);
 855
 856                 if (set_iga == IGA1) {
 857                         viafb_write_reg_mask(CR96, VIACR, 0x00, BIT4);
 858                         viafb_write_reg_mask(CR6C, VIACR, 0x21, BIT0 +
 859                                 BIT5 + BIT7);
 860                 } else {
 861                         viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
 862                         viafb_write_reg_mask(CR6C, VIACR, 0xA1, BIT0 +
 863                                 BIT5 + BIT7);
 864                 }
 865
 866                 viafb_write_reg_mask(SR1E, VIASR, 0xC0, BIT7 + BIT6);
 867
 868                 dvi_patch_skew_dvp0();
 869                 break;
 870
 871         case INTERFACE_DVP1:
 872                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
 873                         if (set_iga == IGA1)
 874                                 viafb_write_reg_mask(CR93, VIACR, 0x21,
 875                                                BIT0 + BIT5 + BIT7);
 876                         else
 877                                 viafb_write_reg_mask(CR93, VIACR, 0xA1,
 878                                                BIT0 + BIT5 + BIT7);
 879                 } else {
 880                         if (set_iga == IGA1)
 881                                 viafb_write_reg_mask(CR9B, VIACR, 0x00, BIT4);
 882                         else
 883                                 viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
 884                 }
 885
 886                 viafb_write_reg_mask(SR1E, VIASR, 0x30, BIT4 + BIT5);
 887                 dvi_patch_skew_dvp1();
 888                 break;
 889         case INTERFACE_DFP_HIGH:
 890                 if (viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266) {
 891                         if (set_iga == IGA1) {
 892                                 viafb_write_reg_mask(CR96, VIACR, 0x00, BIT4);
 893                                 viafb_write_reg_mask(CR97, VIACR, 0x03,
 894                                                BIT0 + BIT1 + BIT4);
 895                         } else {
 896                                 viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
 897                                 viafb_write_reg_mask(CR97, VIACR, 0x13,
 898                                                BIT0 + BIT1 + BIT4);
 899                         }
 900                 }
 901                 viafb_write_reg_mask(SR2A, VIASR, 0x0C, BIT2 + BIT3);
 902                 break;
 903
 904         case INTERFACE_DFP_LOW:
 905                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
 906                         break;
 907
 908                 if (set_iga == IGA1) {
 909                         viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
 910                         viafb_write_reg_mask(CR9B, VIACR, 0x00, BIT4);
 911                 } else {
 912                         viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
 913                         viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
 914                 }
 915
 916                 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1);
 917                 dvi_patch_skew_dvp_low();
 918                 break;
 919
 920         case INTERFACE_TMDS:
 921                 if (set_iga == IGA1)
 922                         viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
 923                 else
 924                         viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
 925                 break;
 926         }
 927
 928         if (set_iga == IGA2) {
 929                 enable_second_display_channel();
 930                 /* Disable LCD Scaling */
 931                 viafb_write_reg_mask(CR79, VIACR, 0x00, BIT0);
 932         }
 933 }
 934
 935 static void set_lcd_output_path(int set_iga, int output_interface)
 936 {
 937         DEBUG_MSG(KERN_INFO
 938                   "set_lcd_output_path, iga:%d,out_interface:%d\n",
 939                   set_iga, output_interface);
 940         switch (set_iga) {
 941         case IGA1:
 942                 viafb_write_reg_mask(CR6B, VIACR, 0x00, BIT3);
 943                 viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
 944
 945                 disable_second_display_channel();
 946                 break;
 947
 948         case IGA2:
 949                 viafb_write_reg_mask(CR6B, VIACR, 0x00, BIT3);
 950                 viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
 951
 952                 enable_second_display_channel();
 953                 break;
 954
 955         case IGA1_IGA2:
 956                 viafb_write_reg_mask(CR6B, VIACR, 0x08, BIT3);
 957                 viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
 958
 959                 disable_second_display_channel();
 960                 break;
 961         }
 962
 963         switch (output_interface) {
 964         case INTERFACE_DVP0:
 965                 if (set_iga == IGA1) {
 966                         viafb_write_reg_mask(CR96, VIACR, 0x00, BIT4);
 967                 } else {
 968                         viafb_write_reg(CR91, VIACR, 0x00);
 969                         viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
 970                 }
 971                 break;
 972
 973         case INTERFACE_DVP1:
 974                 if (set_iga == IGA1)
 975                         viafb_write_reg_mask(CR9B, VIACR, 0x00, BIT4);
 976                 else {
 977                         viafb_write_reg(CR91, VIACR, 0x00);
 978                         viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
 979                 }
 980                 break;
 981
 982         case INTERFACE_DFP_HIGH:
 983                 if (set_iga == IGA1)
 984                         viafb_write_reg_mask(CR97, VIACR, 0x00, BIT4);
 985                 else {
 986                         viafb_write_reg(CR91, VIACR, 0x00);
 987                         viafb_write_reg_mask(CR97, VIACR, 0x10, BIT4);
 988                         viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
 989                 }
 990                 break;
 991
 992         case INTERFACE_DFP_LOW:
 993                 if (set_iga == IGA1)
 994                         viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
 995                 else {
 996                         viafb_write_reg(CR91, VIACR, 0x00);
 997                         viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
 998                         viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
 999                 }
1000
1001                 break;
1002
1003         case INTERFACE_DFP:
1004                 if ((UNICHROME_K8M890 == viaparinfo->chip_info->gfx_chip_name)
1005                     || (UNICHROME_P4M890 ==
1006                     viaparinfo->chip_info->gfx_chip_name))
1007                         viafb_write_reg_mask(CR97, VIACR, 0x84,
1008                                        BIT7 + BIT2 + BIT1 + BIT0);
1009                 if (set_iga == IGA1) {
1010                         viafb_write_reg_mask(CR97, VIACR, 0x00, BIT4);
1011                         viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
1012                 } else {
1013                         viafb_write_reg(CR91, VIACR, 0x00);
1014                         viafb_write_reg_mask(CR97, VIACR, 0x10, BIT4);
1015                         viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
1016                 }
1017                 break;
1018
1019         case INTERFACE_LVDS0:
1020         case INTERFACE_LVDS0LVDS1:
1021                 if (set_iga == IGA1)
1022                         viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
1023                 else
1024                         viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
1025
1026                 break;
1027
1028         case INTERFACE_LVDS1:
1029                 if (set_iga == IGA1)
1030                         viafb_write_reg_mask(CR97, VIACR, 0x00, BIT4);
1031                 else
1032                         viafb_write_reg_mask(CR97, VIACR, 0x10, BIT4);
1033                 break;
1034         }
1035 }
1036
1037 static void load_fix_bit_crtc_reg(void)
1038 {
1039         /* always set to 1 */
1040         viafb_write_reg_mask(CR03, VIACR, 0x80, BIT7);
1041         /* line compare should set all bits = 1 (extend modes) */
1042         viafb_write_reg(CR18, VIACR, 0xff);
1043         /* line compare should set all bits = 1 (extend modes) */
1044         viafb_write_reg_mask(CR07, VIACR, 0x10, BIT4);
1045         /* line compare should set all bits = 1 (extend modes) */
1046         viafb_write_reg_mask(CR09, VIACR, 0x40, BIT6);
1047         /* line compare should set all bits = 1 (extend modes) */
1048         viafb_write_reg_mask(CR35, VIACR, 0x10, BIT4);
1049         /* line compare should set all bits = 1 (extend modes) */
1050         viafb_write_reg_mask(CR33, VIACR, 0x06, BIT0 + BIT1 + BIT2);
1051         /*viafb_write_reg_mask(CR32, VIACR, 0x01, BIT0); */
1052         /* extend mode always set to e3h */
1053         viafb_write_reg(CR17, VIACR, 0xe3);
1054         /* extend mode always set to 0h */
1055         viafb_write_reg(CR08, VIACR, 0x00);
1056         /* extend mode always set to 0h */
1057         viafb_write_reg(CR14, VIACR, 0x00);
1058
1059         /* If K8M800, enable Prefetch Mode. */
1060         if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800)
1061                 || (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890))
1062                 viafb_write_reg_mask(CR33, VIACR, 0x08, BIT3);
1063         if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
1064             && (viaparinfo->chip_info->gfx_chip_revision == CLE266_REVISION_AX))
1065                 viafb_write_reg_mask(SR1A, VIASR, 0x02, BIT1);
1066
1067 }
1068
1069 void viafb_load_reg(int timing_value, int viafb_load_reg_num,
1070         struct io_register *reg,
1071               int io_type)
1072 {
1073         int reg_mask;
1074         int bit_num = 0;
1075         int data;
1076         int i, j;
1077         int shift_next_reg;
1078         int start_index, end_index, cr_index;
1079         u16 get_bit;
1080
1081         for (i = 0; i < viafb_load_reg_num; i++) {
1082                 reg_mask = 0;
1083                 data = 0;
1084                 start_index = reg[i].start_bit;
1085                 end_index = reg[i].end_bit;
1086                 cr_index = reg[i].io_addr;
1087
1088                 shift_next_reg = bit_num;
1089                 for (j = start_index; j <= end_index; j++) {
1090                         /*if (bit_num==8) timing_value = timing_value >>8; */
1091                         reg_mask = reg_mask | (BIT0 << j);
1092                         get_bit = (timing_value & (BIT0 << bit_num));
1093                         data =
1094                             data | ((get_bit >> shift_next_reg) << start_index);
1095                         bit_num++;
1096                 }
1097                 if (io_type == VIACR)
1098                         viafb_write_reg_mask(cr_index, VIACR, data, reg_mask);
1099                 else
1100                         viafb_write_reg_mask(cr_index, VIASR, data, reg_mask);
1101         }
1102
1103 }
1104
1105 /* Write Registers */
1106 void viafb_write_regx(struct io_reg RegTable[], int ItemNum)
1107 {
1108         int i;
1109         unsigned char RegTemp;
1110
1111         /*DEBUG_MSG(KERN_INFO "Table Size : %x!!\n",ItemNum ); */
1112
1113         for (i = 0; i < ItemNum; i++) {
1114                 outb(RegTable[i].index, RegTable[i].port);
1115                 RegTemp = inb(RegTable[i].port + 1);
1116                 RegTemp = (RegTemp & (~RegTable[i].mask)) | RegTable[i].value;
1117                 outb(RegTemp, RegTable[i].port + 1);
1118         }
1119 }
1120
1121 void viafb_load_fetch_count_reg(int h_addr, int bpp_byte, int set_iga)
1122 {
1123         int reg_value;
1124         int viafb_load_reg_num;
1125         struct io_register *reg = NULL;
1126
1127         switch (set_iga) {
1128         case IGA1_IGA2:
1129         case IGA1:
1130                 reg_value = IGA1_FETCH_COUNT_FORMULA(h_addr, bpp_byte);
1131                 viafb_load_reg_num = fetch_count_reg.
1132                         iga1_fetch_count_reg.reg_num;
1133                 reg = fetch_count_reg.iga1_fetch_count_reg.reg;
1134                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1135                 if (set_iga == IGA1)
1136                         break;
1137         case IGA2:
1138                 reg_value = IGA2_FETCH_COUNT_FORMULA(h_addr, bpp_byte);
1139                 viafb_load_reg_num = fetch_count_reg.
1140                         iga2_fetch_count_reg.reg_num;
1141                 reg = fetch_count_reg.iga2_fetch_count_reg.reg;
1142                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1143                 break;
1144         }
1145
1146 }
1147
1148 void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active)
1149 {
1150         int reg_value;
1151         int viafb_load_reg_num;
1152         struct io_register *reg = NULL;
1153         int iga1_fifo_max_depth = 0, iga1_fifo_threshold =
1154             0, iga1_fifo_high_threshold = 0, iga1_display_queue_expire_num = 0;
1155         int iga2_fifo_max_depth = 0, iga2_fifo_threshold =
1156             0, iga2_fifo_high_threshold = 0, iga2_display_queue_expire_num = 0;
1157
1158         if (set_iga == IGA1) {
1159                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1160                         iga1_fifo_max_depth = K800_IGA1_FIFO_MAX_DEPTH;
1161                         iga1_fifo_threshold = K800_IGA1_FIFO_THRESHOLD;
1162                         iga1_fifo_high_threshold =
1163                             K800_IGA1_FIFO_HIGH_THRESHOLD;
1164                         /* If resolution > 1280x1024, expire length = 64, else
1165                            expire length = 128 */
1166                         if ((hor_active > 1280) && (ver_active > 1024))
1167                                 iga1_display_queue_expire_num = 16;
1168                         else
1169                                 iga1_display_queue_expire_num =
1170                                     K800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1171
1172                 }
1173
1174                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_PM800) {
1175                         iga1_fifo_max_depth = P880_IGA1_FIFO_MAX_DEPTH;
1176                         iga1_fifo_threshold = P880_IGA1_FIFO_THRESHOLD;
1177                         iga1_fifo_high_threshold =
1178                             P880_IGA1_FIFO_HIGH_THRESHOLD;
1179                         iga1_display_queue_expire_num =
1180                             P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1181
1182                         /* If resolution > 1280x1024, expire length = 64, else
1183                            expire length = 128 */
1184                         if ((hor_active > 1280) && (ver_active > 1024))
1185                                 iga1_display_queue_expire_num = 16;
1186                         else
1187                                 iga1_display_queue_expire_num =
1188                                     P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1189                 }
1190
1191                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CN700) {
1192                         iga1_fifo_max_depth = CN700_IGA1_FIFO_MAX_DEPTH;
1193                         iga1_fifo_threshold = CN700_IGA1_FIFO_THRESHOLD;
1194                         iga1_fifo_high_threshold =
1195                             CN700_IGA1_FIFO_HIGH_THRESHOLD;
1196
1197                         /* If resolution > 1280x1024, expire length = 64,
1198                            else expire length = 128 */
1199                         if ((hor_active > 1280) && (ver_active > 1024))
1200                                 iga1_display_queue_expire_num = 16;
1201                         else
1202                                 iga1_display_queue_expire_num =
1203                                     CN700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1204                 }
1205
1206                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
1207                         iga1_fifo_max_depth = CX700_IGA1_FIFO_MAX_DEPTH;
1208                         iga1_fifo_threshold = CX700_IGA1_FIFO_THRESHOLD;
1209                         iga1_fifo_high_threshold =
1210                             CX700_IGA1_FIFO_HIGH_THRESHOLD;
1211                         iga1_display_queue_expire_num =
1212                             CX700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1213                 }
1214
1215                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890) {
1216                         iga1_fifo_max_depth = K8M890_IGA1_FIFO_MAX_DEPTH;
1217                         iga1_fifo_threshold = K8M890_IGA1_FIFO_THRESHOLD;
1218                         iga1_fifo_high_threshold =
1219                             K8M890_IGA1_FIFO_HIGH_THRESHOLD;
1220                         iga1_display_queue_expire_num =
1221                             K8M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1222                 }
1223
1224                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M890) {
1225                         iga1_fifo_max_depth = P4M890_IGA1_FIFO_MAX_DEPTH;
1226                         iga1_fifo_threshold = P4M890_IGA1_FIFO_THRESHOLD;
1227                         iga1_fifo_high_threshold =
1228                             P4M890_IGA1_FIFO_HIGH_THRESHOLD;
1229                         iga1_display_queue_expire_num =
1230                             P4M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1231                 }
1232
1233                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M900) {
1234                         iga1_fifo_max_depth = P4M900_IGA1_FIFO_MAX_DEPTH;
1235                         iga1_fifo_threshold = P4M900_IGA1_FIFO_THRESHOLD;
1236                         iga1_fifo_high_threshold =
1237                             P4M900_IGA1_FIFO_HIGH_THRESHOLD;
1238                         iga1_display_queue_expire_num =
1239                             P4M900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1240                 }
1241
1242                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX800) {
1243                         iga1_fifo_max_depth = VX800_IGA1_FIFO_MAX_DEPTH;
1244                         iga1_fifo_threshold = VX800_IGA1_FIFO_THRESHOLD;
1245                         iga1_fifo_high_threshold =
1246                             VX800_IGA1_FIFO_HIGH_THRESHOLD;
1247                         iga1_display_queue_expire_num =
1248                             VX800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1249                 }
1250
1251                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX855) {
1252                         iga1_fifo_max_depth = VX855_IGA1_FIFO_MAX_DEPTH;
1253                         iga1_fifo_threshold = VX855_IGA1_FIFO_THRESHOLD;
1254                         iga1_fifo_high_threshold =
1255                             VX855_IGA1_FIFO_HIGH_THRESHOLD;
1256                         iga1_display_queue_expire_num =
1257                             VX855_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1258                 }
1259
1260                 /* Set Display FIFO Depath Select */
1261                 reg_value = IGA1_FIFO_DEPTH_SELECT_FORMULA(iga1_fifo_max_depth);
1262                 viafb_load_reg_num =
1263                     display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg_num;
1264                 reg = display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg;
1265                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1266
1267                 /* Set Display FIFO Threshold Select */
1268                 reg_value = IGA1_FIFO_THRESHOLD_FORMULA(iga1_fifo_threshold);
1269                 viafb_load_reg_num =
1270                     fifo_threshold_select_reg.
1271                     iga1_fifo_threshold_select_reg.reg_num;
1272                 reg =
1273                     fifo_threshold_select_reg.
1274                     iga1_fifo_threshold_select_reg.reg;
1275                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1276
1277                 /* Set FIFO High Threshold Select */
1278                 reg_value =
1279                     IGA1_FIFO_HIGH_THRESHOLD_FORMULA(iga1_fifo_high_threshold);
1280                 viafb_load_reg_num =
1281                     fifo_high_threshold_select_reg.
1282                     iga1_fifo_high_threshold_select_reg.reg_num;
1283                 reg =
1284                     fifo_high_threshold_select_reg.
1285                     iga1_fifo_high_threshold_select_reg.reg;
1286                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1287
1288                 /* Set Display Queue Expire Num */
1289                 reg_value =
1290                     IGA1_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA
1291                     (iga1_display_queue_expire_num);
1292                 viafb_load_reg_num =
1293                     display_queue_expire_num_reg.
1294                     iga1_display_queue_expire_num_reg.reg_num;
1295                 reg =
1296                     display_queue_expire_num_reg.
1297                     iga1_display_queue_expire_num_reg.reg;
1298                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1299
1300         } else {
1301                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1302                         iga2_fifo_max_depth = K800_IGA2_FIFO_MAX_DEPTH;
1303                         iga2_fifo_threshold = K800_IGA2_FIFO_THRESHOLD;
1304                         iga2_fifo_high_threshold =
1305                             K800_IGA2_FIFO_HIGH_THRESHOLD;
1306
1307                         /* If resolution > 1280x1024, expire length = 64,
1308                            else  expire length = 128 */
1309                         if ((hor_active > 1280) && (ver_active > 1024))
1310                                 iga2_display_queue_expire_num = 16;
1311                         else
1312                                 iga2_display_queue_expire_num =
1313                                     K800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1314                 }
1315
1316                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_PM800) {
1317                         iga2_fifo_max_depth = P880_IGA2_FIFO_MAX_DEPTH;
1318                         iga2_fifo_threshold = P880_IGA2_FIFO_THRESHOLD;
1319                         iga2_fifo_high_threshold =
1320                             P880_IGA2_FIFO_HIGH_THRESHOLD;
1321
1322                         /* If resolution > 1280x1024, expire length = 64,
1323                            else  expire length = 128 */
1324                         if ((hor_active > 1280) && (ver_active > 1024))
1325                                 iga2_display_queue_expire_num = 16;
1326                         else
1327                                 iga2_display_queue_expire_num =
1328                                     P880_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1329                 }
1330
1331                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CN700) {
1332                         iga2_fifo_max_depth = CN700_IGA2_FIFO_MAX_DEPTH;
1333                         iga2_fifo_threshold = CN700_IGA2_FIFO_THRESHOLD;
1334                         iga2_fifo_high_threshold =
1335                             CN700_IGA2_FIFO_HIGH_THRESHOLD;
1336
1337                         /* If resolution > 1280x1024, expire length = 64,
1338                            else expire length = 128 */
1339                         if ((hor_active > 1280) && (ver_active > 1024))
1340                                 iga2_display_queue_expire_num = 16;
1341                         else
1342                                 iga2_display_queue_expire_num =
1343                                     CN700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1344                 }
1345
1346                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
1347                         iga2_fifo_max_depth = CX700_IGA2_FIFO_MAX_DEPTH;
1348                         iga2_fifo_threshold = CX700_IGA2_FIFO_THRESHOLD;
1349                         iga2_fifo_high_threshold =
1350                             CX700_IGA2_FIFO_HIGH_THRESHOLD;
1351                         iga2_display_queue_expire_num =
1352                             CX700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1353                 }
1354
1355                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890) {
1356                         iga2_fifo_max_depth = K8M890_IGA2_FIFO_MAX_DEPTH;
1357                         iga2_fifo_threshold = K8M890_IGA2_FIFO_THRESHOLD;
1358                         iga2_fifo_high_threshold =
1359                             K8M890_IGA2_FIFO_HIGH_THRESHOLD;
1360                         iga2_display_queue_expire_num =
1361                             K8M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1362                 }
1363
1364                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M890) {
1365                         iga2_fifo_max_depth = P4M890_IGA2_FIFO_MAX_DEPTH;
1366                         iga2_fifo_threshold = P4M890_IGA2_FIFO_THRESHOLD;
1367                         iga2_fifo_high_threshold =
1368                             P4M890_IGA2_FIFO_HIGH_THRESHOLD;
1369                         iga2_display_queue_expire_num =
1370                             P4M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1371                 }
1372
1373                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M900) {
1374                         iga2_fifo_max_depth = P4M900_IGA2_FIFO_MAX_DEPTH;
1375                         iga2_fifo_threshold = P4M900_IGA2_FIFO_THRESHOLD;
1376                         iga2_fifo_high_threshold =
1377                             P4M900_IGA2_FIFO_HIGH_THRESHOLD;
1378                         iga2_display_queue_expire_num =
1379                             P4M900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1380                 }
1381
1382                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX800) {
1383                         iga2_fifo_max_depth = VX800_IGA2_FIFO_MAX_DEPTH;
1384                         iga2_fifo_threshold = VX800_IGA2_FIFO_THRESHOLD;
1385                         iga2_fifo_high_threshold =
1386                             VX800_IGA2_FIFO_HIGH_THRESHOLD;
1387                         iga2_display_queue_expire_num =
1388                             VX800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1389                 }
1390
1391                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX855) {
1392                         iga2_fifo_max_depth = VX855_IGA2_FIFO_MAX_DEPTH;
1393                         iga2_fifo_threshold = VX855_IGA2_FIFO_THRESHOLD;
1394                         iga2_fifo_high_threshold =
1395                             VX855_IGA2_FIFO_HIGH_THRESHOLD;
1396                         iga2_display_queue_expire_num =
1397                             VX855_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1398                 }
1399
1400                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1401                         /* Set Display FIFO Depath Select */
1402                         reg_value =
1403                             IGA2_FIFO_DEPTH_SELECT_FORMULA(iga2_fifo_max_depth)
1404                             - 1;
1405                         /* Patch LCD in IGA2 case */
1406                         viafb_load_reg_num =
1407                             display_fifo_depth_reg.
1408                             iga2_fifo_depth_select_reg.reg_num;
1409                         reg =
1410                             display_fifo_depth_reg.
1411                             iga2_fifo_depth_select_reg.reg;
1412                         viafb_load_reg(reg_value,
1413                                 viafb_load_reg_num, reg, VIACR);
1414                 } else {
1415
1416                         /* Set Display FIFO Depath Select */
1417                         reg_value =
1418                             IGA2_FIFO_DEPTH_SELECT_FORMULA(iga2_fifo_max_depth);
1419                         viafb_load_reg_num =
1420                             display_fifo_depth_reg.
1421                             iga2_fifo_depth_select_reg.reg_num;
1422                         reg =
1423                             display_fifo_depth_reg.
1424                             iga2_fifo_depth_select_reg.reg;
1425                         viafb_load_reg(reg_value,
1426                                 viafb_load_reg_num, reg, VIACR);
1427                 }
1428
1429                 /* Set Display FIFO Threshold Select */
1430                 reg_value = IGA2_FIFO_THRESHOLD_FORMULA(iga2_fifo_threshold);
1431                 viafb_load_reg_num =
1432                     fifo_threshold_select_reg.
1433                     iga2_fifo_threshold_select_reg.reg_num;
1434                 reg =
1435                     fifo_threshold_select_reg.
1436                     iga2_fifo_threshold_select_reg.reg;
1437                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1438
1439                 /* Set FIFO High Threshold Select */
1440                 reg_value =
1441                     IGA2_FIFO_HIGH_THRESHOLD_FORMULA(iga2_fifo_high_threshold);
1442                 viafb_load_reg_num =
1443                     fifo_high_threshold_select_reg.
1444                     iga2_fifo_high_threshold_select_reg.reg_num;
1445                 reg =
1446                     fifo_high_threshold_select_reg.
1447                     iga2_fifo_high_threshold_select_reg.reg;
1448                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1449
1450                 /* Set Display Queue Expire Num */
1451                 reg_value =
1452                     IGA2_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA
1453                     (iga2_display_queue_expire_num);
1454                 viafb_load_reg_num =
1455                     display_queue_expire_num_reg.
1456                     iga2_display_queue_expire_num_reg.reg_num;
1457                 reg =
1458                     display_queue_expire_num_reg.
1459                     iga2_display_queue_expire_num_reg.reg;
1460                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1461
1462         }
1463
1464 }
1465
1466 u32 viafb_get_clk_value(int clk)
1467 {
1468         int i;
1469
1470         for (i = 0; i < NUM_TOTAL_PLL_TABLE; i++) {
1471                 if (clk == pll_value[i].clk) {
1472                         switch (viaparinfo->chip_info->gfx_chip_name) {
1473                         case UNICHROME_CLE266:
1474                         case UNICHROME_K400:
1475                                 return pll_value[i].cle266_pll;
1476
1477                         case UNICHROME_K800:
1478                         case UNICHROME_PM800:
1479                         case UNICHROME_CN700:
1480                                 return pll_value[i].k800_pll;
1481
1482                         case UNICHROME_CX700:
1483                         case UNICHROME_K8M890:
1484                         case UNICHROME_P4M890:
1485                         case UNICHROME_P4M900:
1486                         case UNICHROME_VX800:
1487                                 return pll_value[i].cx700_pll;
1488                         case UNICHROME_VX855:
1489                                 return pll_value[i].vx855_pll;
1490                         }
1491                 }
1492         }
1493
1494         DEBUG_MSG(KERN_INFO "Can't find match PLL value\n\n");
1495         return 0;
1496 }
1497
1498 /* Set VCLK*/
1499 void viafb_set_vclock(u32 CLK, int set_iga)
1500 {
1501         unsigned char RegTemp;
1502
1503         /* H.W. Reset : ON */
1504         viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
1505
1506         if ((set_iga == IGA1) || (set_iga == IGA1_IGA2)) {
1507                 /* Change D,N FOR VCLK */
1508                 switch (viaparinfo->chip_info->gfx_chip_name) {
1509                 case UNICHROME_CLE266:
1510                 case UNICHROME_K400:
1511                         viafb_write_reg(SR46, VIASR, CLK / 0x100);
1512                         viafb_write_reg(SR47, VIASR, CLK % 0x100);
1513                         break;
1514
1515                 case UNICHROME_K800:
1516                 case UNICHROME_PM800:
1517                 case UNICHROME_CN700:
1518                 case UNICHROME_CX700:
1519                 case UNICHROME_K8M890:
1520                 case UNICHROME_P4M890:
1521                 case UNICHROME_P4M900:
1522                 case UNICHROME_VX800:
1523                 case UNICHROME_VX855:
1524                         viafb_write_reg(SR44, VIASR, CLK / 0x10000);
1525                         DEBUG_MSG(KERN_INFO "\nSR44=%x", CLK / 0x10000);
1526                         viafb_write_reg(SR45, VIASR, (CLK & 0xFFFF) / 0x100);
1527                         DEBUG_MSG(KERN_INFO "\nSR45=%x",
1528                                   (CLK & 0xFFFF) / 0x100);
1529                         viafb_write_reg(SR46, VIASR, CLK % 0x100);
1530                         DEBUG_MSG(KERN_INFO "\nSR46=%x", CLK % 0x100);
1531                         break;
1532                 }
1533         }
1534
1535         if ((set_iga == IGA2) || (set_iga == IGA1_IGA2)) {
1536                 /* Change D,N FOR LCK */
1537                 switch (viaparinfo->chip_info->gfx_chip_name) {
1538                 case UNICHROME_CLE266:
1539                 case UNICHROME_K400:
1540                         viafb_write_reg(SR44, VIASR, CLK / 0x100);
1541                         viafb_write_reg(SR45, VIASR, CLK % 0x100);
1542                         break;
1543
1544                 case UNICHROME_K800:
1545                 case UNICHROME_PM800:
1546                 case UNICHROME_CN700:
1547                 case UNICHROME_CX700:
1548                 case UNICHROME_K8M890:
1549                 case UNICHROME_P4M890:
1550                 case UNICHROME_P4M900:
1551                 case UNICHROME_VX800:
1552                 case UNICHROME_VX855:
1553                         viafb_write_reg(SR4A, VIASR, CLK / 0x10000);
1554                         viafb_write_reg(SR4B, VIASR, (CLK & 0xFFFF) / 0x100);
1555                         viafb_write_reg(SR4C, VIASR, CLK % 0x100);
1556                         break;
1557                 }
1558         }
1559
1560         /* H.W. Reset : OFF */
1561         viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
1562
1563         /* Reset PLL */
1564         if ((set_iga == IGA1) || (set_iga == IGA1_IGA2)) {
1565                 viafb_write_reg_mask(SR40, VIASR, 0x02, BIT1);
1566                 viafb_write_reg_mask(SR40, VIASR, 0x00, BIT1);
1567         }
1568
1569         if ((set_iga == IGA2) || (set_iga == IGA1_IGA2)) {
1570                 viafb_write_reg_mask(SR40, VIASR, 0x01, BIT0);
1571                 viafb_write_reg_mask(SR40, VIASR, 0x00, BIT0);
1572         }
1573
1574         /* Fire! */
1575         RegTemp = inb(VIARMisc);
1576         outb(RegTemp | (BIT2 + BIT3), VIAWMisc);
1577 }
1578
1579 void viafb_load_crtc_timing(struct display_timing device_timing,
1580         int set_iga)
1581 {
1582         int i;
1583         int viafb_load_reg_num = 0;
1584         int reg_value = 0;
1585         struct io_register *reg = NULL;
1586
1587         viafb_unlock_crt();
1588
1589         for (i = 0; i < 12; i++) {
1590                 if (set_iga == IGA1) {
1591                         switch (i) {
1592                         case H_TOTAL_INDEX:
1593                                 reg_value =
1594                                     IGA1_HOR_TOTAL_FORMULA(device_timing.
1595                                                            hor_total);
1596                                 viafb_load_reg_num =
1597                                         iga1_crtc_reg.hor_total.reg_num;
1598                                 reg = iga1_crtc_reg.hor_total.reg;
1599                                 break;
1600                         case H_ADDR_INDEX:
1601                                 reg_value =
1602                                     IGA1_HOR_ADDR_FORMULA(device_timing.
1603                                                           hor_addr);
1604                                 viafb_load_reg_num =
1605                                         iga1_crtc_reg.hor_addr.reg_num;
1606                                 reg = iga1_crtc_reg.hor_addr.reg;
1607                                 break;
1608                         case H_BLANK_START_INDEX:
1609                                 reg_value =
1610                                     IGA1_HOR_BLANK_START_FORMULA
1611                                     (device_timing.hor_blank_start);
1612                                 viafb_load_reg_num =
1613                                     iga1_crtc_reg.hor_blank_start.reg_num;
1614                                 reg = iga1_crtc_reg.hor_blank_start.reg;
1615                                 break;
1616                         case H_BLANK_END_INDEX:
1617                                 reg_value =
1618                                     IGA1_HOR_BLANK_END_FORMULA
1619                                     (device_timing.hor_blank_start,
1620                                      device_timing.hor_blank_end);
1621                                 viafb_load_reg_num =
1622                                     iga1_crtc_reg.hor_blank_end.reg_num;
1623                                 reg = iga1_crtc_reg.hor_blank_end.reg;
1624                                 break;
1625                         case H_SYNC_START_INDEX:
1626                                 reg_value =
1627                                     IGA1_HOR_SYNC_START_FORMULA
1628                                     (device_timing.hor_sync_start);
1629                                 viafb_load_reg_num =
1630                                     iga1_crtc_reg.hor_sync_start.reg_num;
1631                                 reg = iga1_crtc_reg.hor_sync_start.reg;
1632                                 break;
1633                         case H_SYNC_END_INDEX:
1634                                 reg_value =
1635                                     IGA1_HOR_SYNC_END_FORMULA
1636                                     (device_timing.hor_sync_start,
1637                                      device_timing.hor_sync_end);
1638                                 viafb_load_reg_num =
1639                                     iga1_crtc_reg.hor_sync_end.reg_num;
1640                                 reg = iga1_crtc_reg.hor_sync_end.reg;
1641                                 break;
1642                         case V_TOTAL_INDEX:
1643                                 reg_value =
1644                                     IGA1_VER_TOTAL_FORMULA(device_timing.
1645                                                            ver_total);
1646                                 viafb_load_reg_num =
1647                                         iga1_crtc_reg.ver_total.reg_num;
1648                                 reg = iga1_crtc_reg.ver_total.reg;
1649                                 break;
1650                         case V_ADDR_INDEX:
1651                                 reg_value =
1652                                     IGA1_VER_ADDR_FORMULA(device_timing.
1653                                                           ver_addr);
1654                                 viafb_load_reg_num =
1655                                         iga1_crtc_reg.ver_addr.reg_num;
1656                                 reg = iga1_crtc_reg.ver_addr.reg;
1657                                 break;
1658                         case V_BLANK_START_INDEX:
1659                                 reg_value =
1660                                     IGA1_VER_BLANK_START_FORMULA
1661                                     (device_timing.ver_blank_start);
1662                                 viafb_load_reg_num =
1663                                     iga1_crtc_reg.ver_blank_start.reg_num;
1664                                 reg = iga1_crtc_reg.ver_blank_start.reg;
1665                                 break;
1666                         case V_BLANK_END_INDEX:
1667                                 reg_value =
1668                                     IGA1_VER_BLANK_END_FORMULA
1669                                     (device_timing.ver_blank_start,
1670                                      device_timing.ver_blank_end);
1671                                 viafb_load_reg_num =
1672                                     iga1_crtc_reg.ver_blank_end.reg_num;
1673                                 reg = iga1_crtc_reg.ver_blank_end.reg;
1674                                 break;
1675                         case V_SYNC_START_INDEX:
1676                                 reg_value =
1677                                     IGA1_VER_SYNC_START_FORMULA
1678                                     (device_timing.ver_sync_start);
1679                                 viafb_load_reg_num =
1680                                     iga1_crtc_reg.ver_sync_start.reg_num;
1681                                 reg = iga1_crtc_reg.ver_sync_start.reg;
1682                                 break;
1683                         case V_SYNC_END_INDEX:
1684                                 reg_value =
1685                                     IGA1_VER_SYNC_END_FORMULA
1686                                     (device_timing.ver_sync_start,
1687                                      device_timing.ver_sync_end);
1688                                 viafb_load_reg_num =
1689                                     iga1_crtc_reg.ver_sync_end.reg_num;
1690                                 reg = iga1_crtc_reg.ver_sync_end.reg;
1691                                 break;
1692
1693                         }
1694                 }
1695
1696                 if (set_iga == IGA2) {
1697                         switch (i) {
1698                         case H_TOTAL_INDEX:
1699                                 reg_value =
1700                                     IGA2_HOR_TOTAL_FORMULA(device_timing.
1701                                                            hor_total);
1702                                 viafb_load_reg_num =
1703                                         iga2_crtc_reg.hor_total.reg_num;
1704                                 reg = iga2_crtc_reg.hor_total.reg;
1705                                 break;
1706                         case H_ADDR_INDEX:
1707                                 reg_value =
1708                                     IGA2_HOR_ADDR_FORMULA(device_timing.
1709                                                           hor_addr);
1710                                 viafb_load_reg_num =
1711                                         iga2_crtc_reg.hor_addr.reg_num;
1712                                 reg = iga2_crtc_reg.hor_addr.reg;
1713                                 break;
1714                         case H_BLANK_START_INDEX:
1715                                 reg_value =
1716                                     IGA2_HOR_BLANK_START_FORMULA
1717                                     (device_timing.hor_blank_start);
1718                                 viafb_load_reg_num =
1719                                     iga2_crtc_reg.hor_blank_start.reg_num;
1720                                 reg = iga2_crtc_reg.hor_blank_start.reg;
1721                                 break;
1722                         case H_BLANK_END_INDEX:
1723                                 reg_value =
1724                                     IGA2_HOR_BLANK_END_FORMULA
1725                                     (device_timing.hor_blank_start,
1726                                      device_timing.hor_blank_end);
1727                                 viafb_load_reg_num =
1728                                     iga2_crtc_reg.hor_blank_end.reg_num;
1729                                 reg = iga2_crtc_reg.hor_blank_end.reg;
1730                                 break;
1731                         case H_SYNC_START_INDEX:
1732                                 reg_value =
1733                                     IGA2_HOR_SYNC_START_FORMULA
1734                                     (device_timing.hor_sync_start);
1735                                 if (UNICHROME_CN700 <=
1736                                         viaparinfo->chip_info->gfx_chip_name)
1737                                         viafb_load_reg_num =
1738                                             iga2_crtc_reg.hor_sync_start.
1739                                             reg_num;
1740                                 else
1741                                         viafb_load_reg_num = 3;
1742                                 reg = iga2_crtc_reg.hor_sync_start.reg;
1743                                 break;
1744                         case H_SYNC_END_INDEX:
1745                                 reg_value =
1746                                     IGA2_HOR_SYNC_END_FORMULA
1747                                     (device_timing.hor_sync_start,
1748                                      device_timing.hor_sync_end);
1749                                 viafb_load_reg_num =
1750                                     iga2_crtc_reg.hor_sync_end.reg_num;
1751                                 reg = iga2_crtc_reg.hor_sync_end.reg;
1752                                 break;
1753                         case V_TOTAL_INDEX:
1754                                 reg_value =
1755                                     IGA2_VER_TOTAL_FORMULA(device_timing.
1756                                                            ver_total);
1757                                 viafb_load_reg_num =
1758                                         iga2_crtc_reg.ver_total.reg_num;
1759                                 reg = iga2_crtc_reg.ver_total.reg;
1760                                 break;
1761                         case V_ADDR_INDEX:
1762                                 reg_value =
1763                                     IGA2_VER_ADDR_FORMULA(device_timing.
1764                                                           ver_addr);
1765                                 viafb_load_reg_num =
1766                                         iga2_crtc_reg.ver_addr.reg_num;
1767                                 reg = iga2_crtc_reg.ver_addr.reg;
1768                                 break;
1769                         case V_BLANK_START_INDEX:
1770                                 reg_value =
1771                                     IGA2_VER_BLANK_START_FORMULA
1772                                     (device_timing.ver_blank_start);
1773                                 viafb_load_reg_num =
1774                                     iga2_crtc_reg.ver_blank_start.reg_num;
1775                                 reg = iga2_crtc_reg.ver_blank_start.reg;
1776                                 break;
1777                         case V_BLANK_END_INDEX:
1778                                 reg_value =
1779                                     IGA2_VER_BLANK_END_FORMULA
1780                                     (device_timing.ver_blank_start,
1781                                      device_timing.ver_blank_end);
1782                                 viafb_load_reg_num =
1783                                     iga2_crtc_reg.ver_blank_end.reg_num;
1784                                 reg = iga2_crtc_reg.ver_blank_end.reg;
1785                                 break;
1786                         case V_SYNC_START_INDEX:
1787                                 reg_value =
1788                                     IGA2_VER_SYNC_START_FORMULA
1789                                     (device_timing.ver_sync_start);
1790                                 viafb_load_reg_num =
1791                                     iga2_crtc_reg.ver_sync_start.reg_num;
1792                                 reg = iga2_crtc_reg.ver_sync_start.reg;
1793                                 break;
1794                         case V_SYNC_END_INDEX:
1795                                 reg_value =
1796                                     IGA2_VER_SYNC_END_FORMULA
1797                                     (device_timing.ver_sync_start,
1798                                      device_timing.ver_sync_end);
1799                                 viafb_load_reg_num =
1800                                     iga2_crtc_reg.ver_sync_end.reg_num;
1801                                 reg = iga2_crtc_reg.ver_sync_end.reg;
1802                                 break;
1803
1804                         }
1805                 }
1806                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1807         }
1808
1809         viafb_lock_crt();
1810 }
1811
1812 void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
1813         struct VideoModeTable *video_mode, int bpp_byte, int set_iga)
1814 {
1815         struct display_timing crt_reg;
1816         int i;
1817         int index = 0;
1818         int h_addr, v_addr;
1819         u32 pll_D_N;
1820
1821         for (i = 0; i < video_mode->mode_array; i++) {
1822                 index = i;
1823
1824                 if (crt_table[i].refresh_rate == viaparinfo->
1825                         crt_setting_info->refresh_rate)
1826                         break;
1827         }
1828
1829         crt_reg = crt_table[index].crtc;
1830
1831         /* Mode 640x480 has border, but LCD/DFP didn't have border. */
1832         /* So we would delete border. */
1833         if ((viafb_LCD_ON | viafb_DVI_ON)
1834             && video_mode->crtc[0].crtc.hor_addr == 640
1835             && video_mode->crtc[0].crtc.ver_addr == 480
1836             && viaparinfo->crt_setting_info->refresh_rate == 60) {
1837                 /* The border is 8 pixels. */
1838                 crt_reg.hor_blank_start = crt_reg.hor_blank_start - 8;
1839
1840                 /* Blanking time should add left and right borders. */
1841                 crt_reg.hor_blank_end = crt_reg.hor_blank_end + 16;
1842         }
1843
1844         h_addr = crt_reg.hor_addr;
1845         v_addr = crt_reg.ver_addr;
1846
1847         /* update polarity for CRT timing */
1848         if (crt_table[index].h_sync_polarity == NEGATIVE) {
1849                 if (crt_table[index].v_sync_polarity == NEGATIVE)
1850                         outb((inb(VIARMisc) & (~(BIT6 + BIT7))) |
1851                              (BIT6 + BIT7), VIAWMisc);
1852                 else
1853                         outb((inb(VIARMisc) & (~(BIT6 + BIT7))) | (BIT6),
1854                              VIAWMisc);
1855         } else {
1856                 if (crt_table[index].v_sync_polarity == NEGATIVE)
1857                         outb((inb(VIARMisc) & (~(BIT6 + BIT7))) | (BIT7),
1858                              VIAWMisc);
1859                 else
1860                         outb((inb(VIARMisc) & (~(BIT6 + BIT7))), VIAWMisc);
1861         }
1862
1863         if (set_iga == IGA1) {
1864                 viafb_unlock_crt();
1865                 viafb_write_reg(CR09, VIACR, 0x00);     /*initial CR09=0 */
1866                 viafb_write_reg_mask(CR11, VIACR, 0x00, BIT4 + BIT5 + BIT6);
1867                 viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
1868         }
1869
1870         switch (set_iga) {
1871         case IGA1:
1872                 viafb_load_crtc_timing(crt_reg, IGA1);
1873                 break;
1874         case IGA2:
1875                 viafb_load_crtc_timing(crt_reg, IGA2);
1876                 break;
1877         }
1878
1879         load_fix_bit_crtc_reg();
1880         viafb_lock_crt();
1881         viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
1882         viafb_load_fetch_count_reg(h_addr, bpp_byte, set_iga);
1883
1884         /* load FIFO */
1885         if ((viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266)
1886             && (viaparinfo->chip_info->gfx_chip_name != UNICHROME_K400))
1887                 viafb_load_FIFO_reg(set_iga, h_addr, v_addr);
1888
1889         pll_D_N = viafb_get_clk_value(crt_table[index].clk);
1890         DEBUG_MSG(KERN_INFO "PLL=%x", pll_D_N);
1891         viafb_set_vclock(pll_D_N, set_iga);
1892
1893 }
1894
1895 void viafb_init_chip_info(struct pci_dev *pdev,
1896                           const struct pci_device_id *pdi)
1897 {
1898         init_gfx_chip_info(pdev, pdi);
1899         init_tmds_chip_info();
1900         init_lvds_chip_info();
1901
1902         viaparinfo->crt_setting_info->iga_path = IGA1;
1903         viaparinfo->crt_setting_info->refresh_rate = viafb_refresh;
1904
1905         /*Set IGA path for each device */
1906         viafb_set_iga_path();
1907
1908         viaparinfo->lvds_setting_info->display_method = viafb_lcd_dsp_method;
1909         viaparinfo->lvds_setting_info->get_lcd_size_method =
1910                 GET_LCD_SIZE_BY_USER_SETTING;
1911         viaparinfo->lvds_setting_info->lcd_mode = viafb_lcd_mode;
1912         viaparinfo->lvds_setting_info2->display_method =
1913                 viaparinfo->lvds_setting_info->display_method;
1914         viaparinfo->lvds_setting_info2->lcd_mode =
1915                 viaparinfo->lvds_setting_info->lcd_mode;
1916 }
1917
1918 void viafb_update_device_setting(int hres, int vres,
1919         int bpp, int vmode_refresh, int flag)
1920 {
1921         if (flag == 0) {
1922                 viaparinfo->crt_setting_info->h_active = hres;
1923                 viaparinfo->crt_setting_info->v_active = vres;
1924                 viaparinfo->crt_setting_info->bpp = bpp;
1925                 viaparinfo->crt_setting_info->refresh_rate =
1926                         vmode_refresh;
1927
1928                 viaparinfo->tmds_setting_info->h_active = hres;
1929                 viaparinfo->tmds_setting_info->v_active = vres;
1930
1931                 viaparinfo->lvds_setting_info->h_active = hres;
1932                 viaparinfo->lvds_setting_info->v_active = vres;
1933                 viaparinfo->lvds_setting_info->bpp = bpp;
1934                 viaparinfo->lvds_setting_info->refresh_rate =
1935                         vmode_refresh;
1936                 viaparinfo->lvds_setting_info2->h_active = hres;
1937                 viaparinfo->lvds_setting_info2->v_active = vres;
1938                 viaparinfo->lvds_setting_info2->bpp = bpp;
1939                 viaparinfo->lvds_setting_info2->refresh_rate =
1940                         vmode_refresh;
1941         } else {
1942
1943                 if (viaparinfo->tmds_setting_info->iga_path == IGA2) {
1944                         viaparinfo->tmds_setting_info->h_active = hres;
1945                         viaparinfo->tmds_setting_info->v_active = vres;
1946                 }
1947
1948                 if (viaparinfo->lvds_setting_info->iga_path == IGA2) {
1949                         viaparinfo->lvds_setting_info->h_active = hres;
1950                         viaparinfo->lvds_setting_info->v_active = vres;
1951                         viaparinfo->lvds_setting_info->bpp = bpp;
1952                         viaparinfo->lvds_setting_info->refresh_rate =
1953                                 vmode_refresh;
1954                 }
1955                 if (IGA2 == viaparinfo->lvds_setting_info2->iga_path) {
1956                         viaparinfo->lvds_setting_info2->h_active = hres;
1957                         viaparinfo->lvds_setting_info2->v_active = vres;
1958                         viaparinfo->lvds_setting_info2->bpp = bpp;
1959                         viaparinfo->lvds_setting_info2->refresh_rate =
1960                                 vmode_refresh;
1961                 }
1962         }
1963 }
1964
1965 static void init_gfx_chip_info(struct pci_dev *pdev,
1966                                const struct pci_device_id *pdi)
1967 {
1968         u8 tmp;
1969
1970         viaparinfo->chip_info->gfx_chip_name = pdi->driver_data;
1971
1972         /* Check revision of CLE266 Chip */
1973         if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
1974                 /* CR4F only define in CLE266.CX chip */
1975                 tmp = viafb_read_reg(VIACR, CR4F);
1976                 viafb_write_reg(CR4F, VIACR, 0x55);
1977                 if (viafb_read_reg(VIACR, CR4F) != 0x55)
1978                         viaparinfo->chip_info->gfx_chip_revision =
1979                         CLE266_REVISION_AX;
1980                 else
1981                         viaparinfo->chip_info->gfx_chip_revision =
1982                         CLE266_REVISION_CX;
1983                 /* restore orignal CR4F value */
1984                 viafb_write_reg(CR4F, VIACR, tmp);
1985         }
1986
1987         if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
1988                 tmp = viafb_read_reg(VIASR, SR43);
1989                 DEBUG_MSG(KERN_INFO "SR43:%X\n", tmp);
1990                 if (tmp & 0x02) {
1991                         viaparinfo->chip_info->gfx_chip_revision =
1992                                 CX700_REVISION_700M2;
1993                 } else if (tmp & 0x40) {
1994                         viaparinfo->chip_info->gfx_chip_revision =
1995                                 CX700_REVISION_700M;
1996                 } else {
1997                         viaparinfo->chip_info->gfx_chip_revision =
1998                                 CX700_REVISION_700;
1999                 }
2000         }
2001 }
2002
2003 static void init_tmds_chip_info(void)
2004 {
2005         viafb_tmds_trasmitter_identify();
2006
2007         if (INTERFACE_NONE == viaparinfo->chip_info->tmds_chip_info.
2008                 output_interface) {
2009                 switch (viaparinfo->chip_info->gfx_chip_name) {
2010                 case UNICHROME_CX700:
2011                         {
2012                                 /* we should check support by hardware layout.*/
2013                                 if ((viafb_display_hardware_layout ==
2014                                      HW_LAYOUT_DVI_ONLY)
2015                                     || (viafb_display_hardware_layout ==
2016                                         HW_LAYOUT_LCD_DVI)) {
2017                                         viaparinfo->chip_info->tmds_chip_info.
2018                                             output_interface = INTERFACE_TMDS;
2019                                 } else {
2020                                         viaparinfo->chip_info->tmds_chip_info.
2021                                                 output_interface =
2022                                                 INTERFACE_NONE;
2023                                 }
2024                                 break;
2025                         }
2026                 case UNICHROME_K8M890:
2027                 case UNICHROME_P4M900:
2028                 case UNICHROME_P4M890:
2029                         /* TMDS on PCIE, we set DFPLOW as default. */
2030                         viaparinfo->chip_info->tmds_chip_info.output_interface =
2031                             INTERFACE_DFP_LOW;
2032                         break;
2033                 default:
2034                         {
2035                                 /* set DVP1 default for DVI */
2036                                 viaparinfo->chip_info->tmds_chip_info
2037                                 .output_interface = INTERFACE_DVP1;
2038                         }
2039                 }
2040         }
2041
2042         DEBUG_MSG(KERN_INFO "TMDS Chip = %d\n",
2043                   viaparinfo->chip_info->tmds_chip_info.tmds_chip_name);
2044         viafb_init_dvi_size(&viaparinfo->shared->chip_info.tmds_chip_info,
2045                 &viaparinfo->shared->tmds_setting_info);
2046 }
2047
2048 static void init_lvds_chip_info(void)
2049 {
2050         if (viafb_lcd_panel_id > LCD_PANEL_ID_MAXIMUM)
2051                 viaparinfo->lvds_setting_info->get_lcd_size_method =
2052                     GET_LCD_SIZE_BY_VGA_BIOS;
2053         else
2054                 viaparinfo->lvds_setting_info->get_lcd_size_method =
2055                     GET_LCD_SIZE_BY_USER_SETTING;
2056
2057         viafb_lvds_trasmitter_identify();
2058         viafb_init_lcd_size();
2059         viafb_init_lvds_output_interface(&viaparinfo->chip_info->lvds_chip_info,
2060                                    viaparinfo->lvds_setting_info);
2061         if (viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name) {
2062                 viafb_init_lvds_output_interface(&viaparinfo->chip_info->
2063                         lvds_chip_info2, viaparinfo->lvds_setting_info2);
2064         }
2065         /*If CX700,two singel LCD, we need to reassign
2066            LCD interface to different LVDS port */
2067         if ((UNICHROME_CX700 == viaparinfo->chip_info->gfx_chip_name)
2068             && (HW_LAYOUT_LCD1_LCD2 == viafb_display_hardware_layout)) {
2069                 if ((INTEGRATED_LVDS == viaparinfo->chip_info->lvds_chip_info.
2070                         lvds_chip_name) && (INTEGRATED_LVDS ==
2071                         viaparinfo->chip_info->
2072                         lvds_chip_info2.lvds_chip_name)) {
2073                         viaparinfo->chip_info->lvds_chip_info.output_interface =
2074                                 INTERFACE_LVDS0;
2075                         viaparinfo->chip_info->lvds_chip_info2.
2076                                 output_interface =
2077                             INTERFACE_LVDS1;
2078                 }
2079         }
2080
2081         DEBUG_MSG(KERN_INFO "LVDS Chip = %d\n",
2082                   viaparinfo->chip_info->lvds_chip_info.lvds_chip_name);
2083         DEBUG_MSG(KERN_INFO "LVDS1 output_interface = %d\n",
2084                   viaparinfo->chip_info->lvds_chip_info.output_interface);
2085         DEBUG_MSG(KERN_INFO "LVDS2 output_interface = %d\n",
2086                   viaparinfo->chip_info->lvds_chip_info.output_interface);
2087 }
2088
2089 void viafb_init_dac(int set_iga)
2090 {
2091         int i;
2092         u8 tmp;
2093
2094         if (set_iga == IGA1) {
2095                 /* access Primary Display's LUT */
2096                 viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0);
2097                 /* turn off LCK */
2098                 viafb_write_reg_mask(SR1B, VIASR, 0x00, BIT7 + BIT6);
2099                 for (i = 0; i < 256; i++) {
2100                         write_dac_reg(i, palLUT_table[i].red,
2101                                       palLUT_table[i].green,
2102                                       palLUT_table[i].blue);
2103                 }
2104                 /* turn on LCK */
2105                 viafb_write_reg_mask(SR1B, VIASR, 0xC0, BIT7 + BIT6);
2106         } else {
2107                 tmp = viafb_read_reg(VIACR, CR6A);
2108                 /* access Secondary Display's LUT */
2109                 viafb_write_reg_mask(CR6A, VIACR, 0x40, BIT6);
2110                 viafb_write_reg_mask(SR1A, VIASR, 0x01, BIT0);
2111                 for (i = 0; i < 256; i++) {
2112                         write_dac_reg(i, palLUT_table[i].red,
2113                                       palLUT_table[i].green,
2114                                       palLUT_table[i].blue);
2115                 }
2116                 /* set IGA1 DAC for default */
2117                 viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0);
2118                 viafb_write_reg(CR6A, VIACR, tmp);
2119         }
2120 }
2121
2122 static void device_screen_off(void)
2123 {
2124         /* turn off CRT screen (IGA1) */
2125         viafb_write_reg_mask(SR01, VIASR, 0x20, BIT5);
2126 }
2127
2128 static void device_screen_on(void)
2129 {
2130         /* turn on CRT screen (IGA1) */
2131         viafb_write_reg_mask(SR01, VIASR, 0x00, BIT5);
2132 }
2133
2134 static void set_display_channel(void)
2135 {
2136         /*If viafb_LCD2_ON, on cx700, internal lvds's information
2137         is keeped on lvds_setting_info2 */
2138         if (viafb_LCD2_ON &&
2139                 viaparinfo->lvds_setting_info2->device_lcd_dualedge) {
2140                 /* For dual channel LCD: */
2141                 /* Set to Dual LVDS channel. */
2142                 viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);
2143         } else if (viafb_LCD_ON && viafb_DVI_ON) {
2144                 /* For LCD+DFP: */
2145                 /* Set to LVDS1 + TMDS channel. */
2146                 viafb_write_reg_mask(CRD2, VIACR, 0x10, BIT4 + BIT5);
2147         } else if (viafb_DVI_ON) {
2148                 /* Set to single TMDS channel. */
2149                 viafb_write_reg_mask(CRD2, VIACR, 0x30, BIT4 + BIT5);
2150         } else if (viafb_LCD_ON) {
2151                 if (viaparinfo->lvds_setting_info->device_lcd_dualedge) {
2152                         /* For dual channel LCD: */
2153                         /* Set to Dual LVDS channel. */
2154                         viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);
2155                 } else {
2156                         /* Set to LVDS0 + LVDS1 channel. */
2157                         viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT4 + BIT5);
2158                 }
2159         }
2160 }
2161
2162 int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp,
2163         struct VideoModeTable *vmode_tbl1, int video_bpp1)
2164 {
2165         int i, j;
2166         int port;
2167         u8 value, index, mask;
2168         struct crt_mode_table *crt_timing;
2169         struct crt_mode_table *crt_timing1 = NULL;
2170
2171         device_screen_off();
2172         crt_timing = vmode_tbl->crtc;
2173
2174         if (viafb_SAMM_ON == 1) {
2175                 crt_timing1 = vmode_tbl1->crtc;
2176         }
2177
2178         inb(VIAStatus);
2179         outb(0x00, VIAAR);
2180
2181         /* Write Common Setting for Video Mode */
2182         switch (viaparinfo->chip_info->gfx_chip_name) {
2183         case UNICHROME_CLE266:
2184                 viafb_write_regx(CLE266_ModeXregs, NUM_TOTAL_CLE266_ModeXregs);
2185                 break;
2186
2187         case UNICHROME_K400:
2188                 viafb_write_regx(KM400_ModeXregs, NUM_TOTAL_KM400_ModeXregs);
2189                 break;
2190
2191         case UNICHROME_K800:
2192         case UNICHROME_PM800:
2193                 viafb_write_regx(CN400_ModeXregs, NUM_TOTAL_CN400_ModeXregs);
2194                 break;
2195
2196         case UNICHROME_CN700:
2197         case UNICHROME_K8M890:
2198         case UNICHROME_P4M890:
2199         case UNICHROME_P4M900:
2200                 viafb_write_regx(CN700_ModeXregs, NUM_TOTAL_CN700_ModeXregs);
2201                 break;
2202
2203         case UNICHROME_CX700:
2204         case UNICHROME_VX800:
2205                 viafb_write_regx(CX700_ModeXregs, NUM_TOTAL_CX700_ModeXregs);
2206                 break;
2207
2208         case UNICHROME_VX855:
2209                 viafb_write_regx(VX855_ModeXregs, NUM_TOTAL_VX855_ModeXregs);
2210                 break;
2211         }
2212
2213         device_off();
2214
2215         /* Fill VPIT Parameters */
2216         /* Write Misc Register */
2217         outb(VPIT.Misc, VIAWMisc);
2218
2219         /* Write Sequencer */
2220         for (i = 1; i <= StdSR; i++) {
2221                 outb(i, VIASR);
2222                 outb(VPIT.SR[i - 1], VIASR + 1);
2223         }
2224
2225         viafb_write_reg_mask(0x15, VIASR, viafbinfo->fix.visual
2226                 == FB_VISUAL_PSEUDOCOLOR ? 0x22 : 0xA2, 0xA2);
2227         viafb_set_iga_path();
2228
2229         /* Write CRTC */
2230         viafb_fill_crtc_timing(crt_timing, vmode_tbl, video_bpp / 8, IGA1);
2231
2232         /* Write Graphic Controller */
2233         for (i = 0; i < StdGR; i++) {
2234                 outb(i, VIAGR);
2235                 outb(VPIT.GR[i], VIAGR + 1);
2236         }
2237
2238         /* Write Attribute Controller */
2239         for (i = 0; i < StdAR; i++) {
2240                 inb(VIAStatus);
2241                 outb(i, VIAAR);
2242                 outb(VPIT.AR[i], VIAAR);
2243         }
2244
2245         inb(VIAStatus);
2246         outb(0x20, VIAAR);
2247
2248         /* Update Patch Register */
2249
2250         if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266
2251             || viaparinfo->chip_info->gfx_chip_name == UNICHROME_K400)
2252             && vmode_tbl->crtc[0].crtc.hor_addr == 1024
2253             && vmode_tbl->crtc[0].crtc.ver_addr == 768) {
2254                 for (j = 0; j < res_patch_table[0].table_length; j++) {
2255                         index = res_patch_table[0].io_reg_table[j].index;
2256                         port = res_patch_table[0].io_reg_table[j].port;
2257                         value = res_patch_table[0].io_reg_table[j].value;
2258                         mask = res_patch_table[0].io_reg_table[j].mask;
2259                         viafb_write_reg_mask(index, port, value, mask);
2260                 }
2261         }
2262
2263         viafb_set_primary_pitch(viafbinfo->fix.line_length);
2264         viafb_set_secondary_pitch(viafb_dual_fb ? viafbinfo1->fix.line_length
2265                 : viafbinfo->fix.line_length);
2266         viafb_set_primary_color_depth(viaparinfo->depth);
2267         viafb_set_secondary_color_depth(viafb_dual_fb ? viaparinfo1->depth
2268                 : viaparinfo->depth);
2269         /* Update Refresh Rate Setting */
2270
2271         /* Clear On Screen */
2272
2273         /* CRT set mode */
2274         if (viafb_CRT_ON) {
2275                 if (viafb_SAMM_ON && (viaparinfo->crt_setting_info->iga_path ==
2276                         IGA2)) {
2277                         viafb_fill_crtc_timing(crt_timing1, vmode_tbl1,
2278                                 video_bpp1 / 8,
2279                                 viaparinfo->crt_setting_info->iga_path);
2280                 } else {
2281                         viafb_fill_crtc_timing(crt_timing, vmode_tbl,
2282                                 video_bpp / 8,
2283                                 viaparinfo->crt_setting_info->iga_path);
2284                 }
2285
2286                 set_crt_output_path(viaparinfo->crt_setting_info->iga_path);
2287
2288                 /* Patch if set_hres is not 8 alignment (1366) to viafb_setmode
2289                 to 8 alignment (1368),there is several pixels (2 pixels)
2290                 on right side of screen. */
2291                 if (vmode_tbl->crtc[0].crtc.hor_addr % 8) {
2292                         viafb_unlock_crt();
2293                         viafb_write_reg(CR02, VIACR,
2294                                 viafb_read_reg(VIACR, CR02) - 1);
2295                         viafb_lock_crt();
2296                 }
2297         }
2298
2299         if (viafb_DVI_ON) {
2300                 if (viafb_SAMM_ON &&
2301                         (viaparinfo->tmds_setting_info->iga_path == IGA2)) {
2302                         viafb_dvi_set_mode(viafb_get_mode
2303                                      (viaparinfo->tmds_setting_info->h_active,
2304                                       viaparinfo->tmds_setting_info->
2305                                       v_active),
2306                                      video_bpp1, viaparinfo->
2307                                      tmds_setting_info->iga_path);
2308                 } else {
2309                         viafb_dvi_set_mode(viafb_get_mode
2310                                      (viaparinfo->tmds_setting_info->h_active,
2311                                       viaparinfo->
2312                                       tmds_setting_info->v_active),
2313                                      video_bpp, viaparinfo->
2314                                      tmds_setting_info->iga_path);
2315                 }
2316         }
2317
2318         if (viafb_LCD_ON) {
2319                 if (viafb_SAMM_ON &&
2320                         (viaparinfo->lvds_setting_info->iga_path == IGA2)) {
2321                         viaparinfo->lvds_setting_info->bpp = video_bpp1;
2322                         viafb_lcd_set_mode(crt_timing1, viaparinfo->
2323                                 lvds_setting_info,
2324                                      &viaparinfo->chip_info->lvds_chip_info);
2325                 } else {
2326                         /* IGA1 doesn't have LCD scaling, so set it center. */
2327                         if (viaparinfo->lvds_setting_info->iga_path == IGA1) {
2328                                 viaparinfo->lvds_setting_info->display_method =
2329                                     LCD_CENTERING;
2330                         }
2331                         viaparinfo->lvds_setting_info->bpp = video_bpp;
2332                         viafb_lcd_set_mode(crt_timing, viaparinfo->
2333                                 lvds_setting_info,
2334                                      &viaparinfo->chip_info->lvds_chip_info);
2335                 }
2336         }
2337         if (viafb_LCD2_ON) {
2338                 if (viafb_SAMM_ON &&
2339                         (viaparinfo->lvds_setting_info2->iga_path == IGA2)) {
2340                         viaparinfo->lvds_setting_info2->bpp = video_bpp1;
2341                         viafb_lcd_set_mode(crt_timing1, viaparinfo->
2342                                 lvds_setting_info2,
2343                                      &viaparinfo->chip_info->lvds_chip_info2);
2344                 } else {
2345                         /* IGA1 doesn't have LCD scaling, so set it center. */
2346                         if (viaparinfo->lvds_setting_info2->iga_path == IGA1) {
2347                                 viaparinfo->lvds_setting_info2->display_method =
2348                                     LCD_CENTERING;
2349                         }
2350                         viaparinfo->lvds_setting_info2->bpp = video_bpp;
2351                         viafb_lcd_set_mode(crt_timing, viaparinfo->
2352                                 lvds_setting_info2,
2353                                      &viaparinfo->chip_info->lvds_chip_info2);
2354                 }
2355         }
2356
2357         if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700)
2358             && (viafb_LCD_ON || viafb_DVI_ON))
2359                 set_display_channel();
2360
2361         /* If set mode normally, save resolution information for hot-plug . */
2362         if (!viafb_hotplug) {
2363                 viafb_hotplug_Xres = vmode_tbl->crtc[0].crtc.hor_addr;
2364                 viafb_hotplug_Yres = vmode_tbl->crtc[0].crtc.ver_addr;
2365                 viafb_hotplug_bpp = video_bpp;
2366                 viafb_hotplug_refresh = viafb_refresh;
2367
2368                 if (viafb_DVI_ON)
2369                         viafb_DeviceStatus = DVI_Device;
2370                 else
2371                         viafb_DeviceStatus = CRT_Device;
2372         }
2373         device_on();
2374
2375         if (viafb_SAMM_ON == 1)
2376                 viafb_write_reg_mask(CR6A, VIACR, 0xC0, BIT6 + BIT7);
2377
2378         device_screen_on();
2379         return 1;
2380 }
2381
2382 int viafb_get_pixclock(int hres, int vres, int vmode_refresh)
2383 {
2384         int i;
2385
2386         for (i = 0; i < NUM_TOTAL_RES_MAP_REFRESH; i++) {
2387                 if ((hres == res_map_refresh_tbl[i].hres)
2388                     && (vres == res_map_refresh_tbl[i].vres)
2389                     && (vmode_refresh == res_map_refresh_tbl[i].vmode_refresh))
2390                         return res_map_refresh_tbl[i].pixclock;
2391         }
2392         return RES_640X480_60HZ_PIXCLOCK;
2393
2394 }
2395
2396 int viafb_get_refresh(int hres, int vres, u32 long_refresh)
2397 {
2398 #define REFRESH_TOLERANCE 3
2399         int i, nearest = -1, diff = REFRESH_TOLERANCE;
2400         for (i = 0; i < NUM_TOTAL_RES_MAP_REFRESH; i++) {
2401                 if ((hres == res_map_refresh_tbl[i].hres)
2402                     && (vres == res_map_refresh_tbl[i].vres)
2403                     && (diff > (abs(long_refresh -
2404                     res_map_refresh_tbl[i].vmode_refresh)))) {
2405                         diff = abs(long_refresh - res_map_refresh_tbl[i].
2406                                 vmode_refresh);
2407                         nearest = i;
2408                 }
2409         }
2410 #undef REFRESH_TOLERANCE
2411         if (nearest > 0)
2412                 return res_map_refresh_tbl[nearest].vmode_refresh;
2413         return 60;
2414 }
2415
2416 static void device_off(void)
2417 {
2418         viafb_crt_disable();
2419         viafb_dvi_disable();
2420         viafb_lcd_disable();
2421 }
2422
2423 static void device_on(void)
2424 {
2425         if (viafb_CRT_ON == 1)
2426                 viafb_crt_enable();
2427         if (viafb_DVI_ON == 1)
2428                 viafb_dvi_enable();
2429         if (viafb_LCD_ON == 1)
2430                 viafb_lcd_enable();
2431 }
2432
2433 void viafb_crt_disable(void)
2434 {
2435         viafb_write_reg_mask(CR36, VIACR, BIT5 + BIT4, BIT5 + BIT4);
2436 }
2437
2438 void viafb_crt_enable(void)
2439 {
2440         viafb_write_reg_mask(CR36, VIACR, 0x0, BIT5 + BIT4);
2441 }
2442
2443 static void enable_second_display_channel(void)
2444 {
2445         /* to enable second display channel. */
2446         viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6);
2447         viafb_write_reg_mask(CR6A, VIACR, BIT7, BIT7);
2448         viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6);
2449 }
2450
2451 static void disable_second_display_channel(void)
2452 {
2453         /* to disable second display channel. */
2454         viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6);
2455         viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT7);
2456         viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6);
2457 }
2458
2459 int viafb_get_fb_size_from_pci(void)
2460 {
2461         unsigned long configid, deviceid, FBSize = 0;
2462         int VideoMemSize;
2463         int DeviceFound = false;
2464
2465         for (configid = 0x80000000; configid < 0x80010800; configid += 0x100) {
2466                 outl(configid, (unsigned long)0xCF8);
2467                 deviceid = (inl((unsigned long)0xCFC) >> 16) & 0xffff;
2468
2469                 switch (deviceid) {
2470                 case CLE266:
2471                 case KM400:
2472                         outl(configid + 0xE0, (unsigned long)0xCF8);
2473                         FBSize = inl((unsigned long)0xCFC);
2474                         DeviceFound = true;     /* Found device id */
2475                         break;
2476
2477                 case CN400_FUNCTION3:
2478                 case CN700_FUNCTION3:
2479                 case CX700_FUNCTION3:
2480                 case KM800_FUNCTION3:
2481                 case KM890_FUNCTION3:
2482                 case P4M890_FUNCTION3:
2483                 case P4M900_FUNCTION3:
2484                 case VX800_FUNCTION3:
2485                 case VX855_FUNCTION3:
2486                         /*case CN750_FUNCTION3: */
2487                         outl(configid + 0xA0, (unsigned long)0xCF8);
2488                         FBSize = inl((unsigned long)0xCFC);
2489                         DeviceFound = true;     /* Found device id */
2490                         break;
2491
2492                 default:
2493                         break;
2494                 }
2495
2496                 if (DeviceFound)
2497                         break;
2498         }
2499
2500         DEBUG_MSG(KERN_INFO "Device ID = %lx\n", deviceid);
2501
2502         FBSize = FBSize & 0x00007000;
2503         DEBUG_MSG(KERN_INFO "FB Size = %x\n", FBSize);
2504
2505         if (viaparinfo->chip_info->gfx_chip_name < UNICHROME_CX700) {
2506                 switch (FBSize) {
2507                 case 0x00004000:
2508                         VideoMemSize = (16 << 20);      /*16M */
2509                         break;
2510
2511                 case 0x00005000:
2512                         VideoMemSize = (32 << 20);      /*32M */
2513                         break;
2514
2515                 case 0x00006000:
2516                         VideoMemSize = (64 << 20);      /*64M */
2517                         break;
2518
2519                 default:
2520                         VideoMemSize = (32 << 20);      /*32M */
2521                         break;
2522                 }
2523         } else {
2524                 switch (FBSize) {
2525                 case 0x00001000:
2526                         VideoMemSize = (8 << 20);       /*8M */
2527                         break;
2528
2529                 case 0x00002000:
2530                         VideoMemSize = (16 << 20);      /*16M */
2531                         break;
2532
2533                 case 0x00003000:
2534                         VideoMemSize = (32 << 20);      /*32M */
2535                         break;
2536
2537                 case 0x00004000:
2538                         VideoMemSize = (64 << 20);      /*64M */
2539                         break;
2540
2541                 case 0x00005000:
2542                         VideoMemSize = (128 << 20);     /*128M */
2543                         break;
2544
2545                 case 0x00006000:
2546                         VideoMemSize = (256 << 20);     /*256M */
2547                         break;
2548
2549                 case 0x00007000:        /* Only on VX855/875 */
2550                         VideoMemSize = (512 << 20);     /*512M */
2551                         break;
2552
2553                 default:
2554                         VideoMemSize = (32 << 20);      /*32M */
2555                         break;
2556                 }
2557         }
2558
2559         return VideoMemSize;
2560 }
2561
2562 void viafb_set_dpa_gfx(int output_interface, struct GFX_DPA_SETTING\
2563                                         *p_gfx_dpa_setting)
2564 {
2565         switch (output_interface) {
2566         case INTERFACE_DVP0:
2567                 {
2568                         /* DVP0 Clock Polarity and Adjust: */
2569                         viafb_write_reg_mask(CR96, VIACR,
2570                                        p_gfx_dpa_setting->DVP0, 0x0F);
2571
2572                         /* DVP0 Clock and Data Pads Driving: */
2573                         viafb_write_reg_mask(SR1E, VIASR,
2574                                        p_gfx_dpa_setting->DVP0ClockDri_S, BIT2);
2575                         viafb_write_reg_mask(SR2A, VIASR,
2576                                        p_gfx_dpa_setting->DVP0ClockDri_S1,
2577                                        BIT4);
2578                         viafb_write_reg_mask(SR1B, VIASR,
2579                                        p_gfx_dpa_setting->DVP0DataDri_S, BIT1);
2580                         viafb_write_reg_mask(SR2A, VIASR,
2581                                        p_gfx_dpa_setting->DVP0DataDri_S1, BIT5);
2582                         break;
2583                 }
2584
2585         case INTERFACE_DVP1:
2586                 {
2587                         /* DVP1 Clock Polarity and Adjust: */
2588                         viafb_write_reg_mask(CR9B, VIACR,
2589                                        p_gfx_dpa_setting->DVP1, 0x0F);
2590
2591                         /* DVP1 Clock and Data Pads Driving: */
2592                         viafb_write_reg_mask(SR65, VIASR,
2593                                        p_gfx_dpa_setting->DVP1Driving, 0x0F);
2594                         break;
2595                 }
2596
2597         case INTERFACE_DFP_HIGH:
2598                 {
2599                         viafb_write_reg_mask(CR97, VIACR,
2600                                        p_gfx_dpa_setting->DFPHigh, 0x0F);
2601                         break;
2602                 }
2603
2604         case INTERFACE_DFP_LOW:
2605                 {
2606                         viafb_write_reg_mask(CR99, VIACR,
2607                                        p_gfx_dpa_setting->DFPLow, 0x0F);
2608                         break;
2609                 }
2610
2611         case INTERFACE_DFP:
2612                 {
2613                         viafb_write_reg_mask(CR97, VIACR,
2614                                        p_gfx_dpa_setting->DFPHigh, 0x0F);
2615                         viafb_write_reg_mask(CR99, VIACR,
2616                                        p_gfx_dpa_setting->DFPLow, 0x0F);
2617                         break;
2618                 }
2619         }
2620 }
2621
2622 /*According var's xres, yres fill var's other timing information*/
2623 void viafb_fill_var_timing_info(struct fb_var_screeninfo *var, int refresh,
2624         struct VideoModeTable *vmode_tbl)
2625 {
2626         struct crt_mode_table *crt_timing = NULL;
2627         struct display_timing crt_reg;
2628         int i = 0, index = 0;
2629         crt_timing = vmode_tbl->crtc;
2630         for (i = 0; i < vmode_tbl->mode_array; i++) {
2631                 index = i;
2632                 if (crt_timing[i].refresh_rate == refresh)
2633                         break;
2634         }
2635
2636         crt_reg = crt_timing[index].crtc;
2637         switch (var->bits_per_pixel) {
2638         case 8:
2639                 var->red.offset = 0;
2640                 var->green.offset = 0;
2641                 var->blue.offset = 0;
2642                 var->red.length = 6;
2643                 var->green.length = 6;
2644                 var->blue.length = 6;
2645                 break;
2646         case 16:
2647                 var->red.offset = 11;
2648                 var->green.offset = 5;
2649                 var->blue.offset = 0;
2650                 var->red.length = 5;
2651                 var->green.length = 6;
2652                 var->blue.length = 5;
2653                 break;
2654         case 32:
2655                 var->red.offset = 16;
2656                 var->green.offset = 8;
2657                 var->blue.offset = 0;
2658                 var->red.length = 8;
2659                 var->green.length = 8;
2660                 var->blue.length = 8;
2661                 break;
2662         default:
2663                 /* never happed, put here to keep consistent */
2664                 break;
2665         }
2666
2667         var->pixclock = viafb_get_pixclock(var->xres, var->yres, refresh);
2668         var->left_margin =
2669             crt_reg.hor_total - (crt_reg.hor_sync_start + crt_reg.hor_sync_end);
2670         var->right_margin = crt_reg.hor_sync_start - crt_reg.hor_addr;
2671         var->hsync_len = crt_reg.hor_sync_end;
2672         var->upper_margin =
2673             crt_reg.ver_total - (crt_reg.ver_sync_start + crt_reg.ver_sync_end);
2674         var->lower_margin = crt_reg.ver_sync_start - crt_reg.ver_addr;
2675         var->vsync_len = crt_reg.ver_sync_end;
2676 }