2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public
7 * License as published by the Free Software Foundation;
8 * either version 2, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12 * the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE.See the GNU General Public License
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 #include <linux/via-core.h>
25 static struct pll_map pll_value[] = {
28 {85, 3, 4}, /* ignoring bit difference: 0x00008000 */
33 {66, 2, 4}, /* ignoring bit difference: 0x00808000 */
34 {166, 5, 4}, /* ignoring bit difference: 0x00008000 */
38 {30, 2, 3}, /* ignoring bit difference: 0x00808000 */
42 {53, 3, 3}, /* ignoring bit difference: 0x00008000 */
43 {141, 4, 4}, /* ignoring bit difference: 0x00008000 */
48 {177, 5, 4}, /* ignoring bit difference: 0x00008000 */
53 {146, 4, 4}, /* ignoring bit difference: 0x00008000 */
57 {101, 5, 3}, /* ignoring bit difference: 0x00008000 */
58 {161, 4, 4}, /* ignoring bit difference: 0x00008000 */
63 {89, 4, 3}, /* ignoring bit difference: 0x00008000 */
68 {69, 3, 3}, /* ignoring bit difference: 0x00008000 */
73 {121, 5, 3}, /* ignoring bit difference: 0x00008000 */
78 {127, 5, 3}, /* ignoring bit difference: 0x00808000 */
83 {103, 4, 3}, /* ignoring bit difference: 0x00008000 */
87 {105, 4, 3}, /* ignoring bit difference: 0x00008000 */
88 {131, 5, 3}, /* ignoring bit difference: 0x00808000 */
89 {131, 5, 3}, /* ignoring bit difference: 0x00808000 */
93 {134, 5, 3}, /* ignoring bit difference: 0x00808000 */
98 {82, 3, 3}, /* ignoring bit difference: 0x00808000 */
99 {82, 3, 3}, /* ignoring bit difference: 0x00808000 */
103 {83, 3, 3}, /* ignoring bit difference: 0x00008000 */
108 {117, 4, 3}, /* ignoring bit difference: 0x00008000 */
113 {148, 5, 3}, /* ignoring bit difference: 0x00808000 */
117 {55, 7, 1}, /* ignoring bit difference: 0x00008000 */
118 {126, 4, 3}, /* ignoring bit difference: 0x00008000 */
125 {157, 5, 3} }, /* ignoring bit difference: 0x00808000 */
128 {169, 5, 3}, /* ignoring bit difference: 0x00808000 */
129 {169, 5, 3}, /* FIXED: old = {72, 2, 3} */
133 {172, 5, 3}, /* ignoring bit difference: 0x00808000 */
137 {109, 6, 2}, /* ignoring bit difference: 0x00008000 */
138 {109, 3, 3}, /* ignoring bit difference: 0x00008000 */
143 {182, 5, 3}, /* ignoring bit difference: 0x00808000 */
148 {150, 4, 3}, /* ignoring bit difference: 0x00808000 */
153 {114, 3, 3}, /* ignoring bit difference: 0x00008000 */
158 {195, 5, 3}, /* ignoring bit difference: 0x00808000 */
163 {196, 5, 3}, /* ignoring bit difference: 0x00808000 */
168 {161, 4, 3}, /* ignoring bit difference: 0x00808000 */
173 {66, 3, 2}, /* ignoring bit difference: 0x00008000 */
178 {68, 3, 2}, /* ignoring bit difference: 0x00008000 */
183 {93, 4, 2}, /* ignoring bit difference: 0x00800000 */
184 {93, 4, 2}, /* ignoring bit difference: 0x00800000 */
188 {117, 5, 2}, /* ignoring bit difference: 0x00008000 */
193 {118, 5, 2}, /* ignoring bit difference: 0x00808000 */
198 {120, 5, 2}, /* ignoring bit difference: 0x00808000 */
203 {124, 5, 2}, /* ignoring bit difference: 0x00808000 */
204 {174, 7, 2}, /* ignoring bit difference: 0x00808000 */
208 {132, 5, 2}, /* ignoring bit difference: 0x00008000 */
213 {137, 5, 2}, /* ignoring bit difference: 0x00808000 */
218 {141, 5, 2}, /* ignoring bit difference: 0x00808000 */
223 {119, 4, 2}, /* ignoring bit difference: 0x00808000 */
228 {121, 4, 2}, /* ignoring bit difference: 0x00808000 */
233 {95, 3, 2}, /* ignoring bit difference: 0x00808000 */
238 {166, 5, 2}, /* ignoring bit difference: 0x00808000 */
243 {133, 4, 2}, /* ignoring bit difference: 0x00808000 */
248 {170, 5, 2}, /* ignoring bit difference: 0x00808000 */
252 {53, 6, 0}, /* ignoring bit difference: 0x00008000 */
253 {106, 3, 2}, /* ignoring bit difference: 0x00008000 */
258 {28, 3, 0}, /* ignoring bit difference: 0x00804000 */
263 {191, 5, 2}, /* ignoring bit difference: 0x00808000 */
268 {116, 3, 2}, /* ignoring bit difference: 0x00808000 */
273 {206, 5, 2}, /* ignoring bit difference: 0x00808000 */
278 {86, 4, 1}, /* ignoring bit difference: 0x00808000 */
280 {86, 4, 1} }, /* FIXED: old = {84, 2, 1} */
283 {109, 5, 1}, /* ignoring bit difference: 0x00808000 */
287 {55, 5, 0}, /* ignoring bit difference: 0x00008000 */
288 {22, 2, 0}, /* ignoring bit difference: 0x00802000 */
293 {113, 5, 1}, /* ignoring bit difference: 0x00808000 */
298 {131, 5, 1}, /* ignoring bit difference: 0x00808000 */
303 {81, 3, 1}, /* ignoring bit difference: 0x00808000 */
308 {85, 3, 1}, /* ignoring bit difference: 0x00808000 */
313 {143, 5, 1}, /* ignoring bit difference: 0x00808000 */
318 {153, 5, 1}, /* ignoring bit difference: 0x00808000 */
323 {98, 3, 1}, /* ignoring bit difference: 0x00008000 */
328 {112, 3, 1}, /* ignoring bit difference: 0x00808000 */
332 {102, 5, 0}, /* ignoring bit difference: 0x00008000 */
333 {166, 4, 1}, /* ignoring bit difference: 0x00008000 */
338 {125, 3, 3}, /* ignoring bit difference: 0x00808000 */
343 {121, 5, 1}, /* ignoring bit difference: 0x00808000 */
348 {137, 4, 2}, /* ignoring bit difference: 0x00808000 */
363 static struct fifo_depth_select display_fifo_depth_reg = {
364 /* IGA1 FIFO Depth_Select */
365 {IGA1_FIFO_DEPTH_SELECT_REG_NUM, {{SR17, 0, 7} } },
366 /* IGA2 FIFO Depth_Select */
367 {IGA2_FIFO_DEPTH_SELECT_REG_NUM,
368 {{CR68, 4, 7}, {CR94, 7, 7}, {CR95, 7, 7} } }
371 static struct fifo_threshold_select fifo_threshold_select_reg = {
372 /* IGA1 FIFO Threshold Select */
373 {IGA1_FIFO_THRESHOLD_REG_NUM, {{SR16, 0, 5}, {SR16, 7, 7} } },
374 /* IGA2 FIFO Threshold Select */
375 {IGA2_FIFO_THRESHOLD_REG_NUM, {{CR68, 0, 3}, {CR95, 4, 6} } }
378 static struct fifo_high_threshold_select fifo_high_threshold_select_reg = {
379 /* IGA1 FIFO High Threshold Select */
380 {IGA1_FIFO_HIGH_THRESHOLD_REG_NUM, {{SR18, 0, 5}, {SR18, 7, 7} } },
381 /* IGA2 FIFO High Threshold Select */
382 {IGA2_FIFO_HIGH_THRESHOLD_REG_NUM, {{CR92, 0, 3}, {CR95, 0, 2} } }
385 static struct display_queue_expire_num display_queue_expire_num_reg = {
386 /* IGA1 Display Queue Expire Num */
387 {IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{SR22, 0, 4} } },
388 /* IGA2 Display Queue Expire Num */
389 {IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{CR94, 0, 6} } }
392 /* Definition Fetch Count Registers*/
393 static struct fetch_count fetch_count_reg = {
394 /* IGA1 Fetch Count Register */
395 {IGA1_FETCH_COUNT_REG_NUM, {{SR1C, 0, 7}, {SR1D, 0, 1} } },
396 /* IGA2 Fetch Count Register */
397 {IGA2_FETCH_COUNT_REG_NUM, {{CR65, 0, 7}, {CR67, 2, 3} } }
400 static struct iga1_crtc_timing iga1_crtc_reg = {
401 /* IGA1 Horizontal Total */
402 {IGA1_HOR_TOTAL_REG_NUM, {{CR00, 0, 7}, {CR36, 3, 3} } },
403 /* IGA1 Horizontal Addressable Video */
404 {IGA1_HOR_ADDR_REG_NUM, {{CR01, 0, 7} } },
405 /* IGA1 Horizontal Blank Start */
406 {IGA1_HOR_BLANK_START_REG_NUM, {{CR02, 0, 7} } },
407 /* IGA1 Horizontal Blank End */
408 {IGA1_HOR_BLANK_END_REG_NUM,
409 {{CR03, 0, 4}, {CR05, 7, 7}, {CR33, 5, 5} } },
410 /* IGA1 Horizontal Sync Start */
411 {IGA1_HOR_SYNC_START_REG_NUM, {{CR04, 0, 7}, {CR33, 4, 4} } },
412 /* IGA1 Horizontal Sync End */
413 {IGA1_HOR_SYNC_END_REG_NUM, {{CR05, 0, 4} } },
414 /* IGA1 Vertical Total */
415 {IGA1_VER_TOTAL_REG_NUM,
416 {{CR06, 0, 7}, {CR07, 0, 0}, {CR07, 5, 5}, {CR35, 0, 0} } },
417 /* IGA1 Vertical Addressable Video */
418 {IGA1_VER_ADDR_REG_NUM,
419 {{CR12, 0, 7}, {CR07, 1, 1}, {CR07, 6, 6}, {CR35, 2, 2} } },
420 /* IGA1 Vertical Blank Start */
421 {IGA1_VER_BLANK_START_REG_NUM,
422 {{CR15, 0, 7}, {CR07, 3, 3}, {CR09, 5, 5}, {CR35, 3, 3} } },
423 /* IGA1 Vertical Blank End */
424 {IGA1_VER_BLANK_END_REG_NUM, {{CR16, 0, 7} } },
425 /* IGA1 Vertical Sync Start */
426 {IGA1_VER_SYNC_START_REG_NUM,
427 {{CR10, 0, 7}, {CR07, 2, 2}, {CR07, 7, 7}, {CR35, 1, 1} } },
428 /* IGA1 Vertical Sync End */
429 {IGA1_VER_SYNC_END_REG_NUM, {{CR11, 0, 3} } }
432 static struct iga2_crtc_timing iga2_crtc_reg = {
433 /* IGA2 Horizontal Total */
434 {IGA2_HOR_TOTAL_REG_NUM, {{CR50, 0, 7}, {CR55, 0, 3} } },
435 /* IGA2 Horizontal Addressable Video */
436 {IGA2_HOR_ADDR_REG_NUM, {{CR51, 0, 7}, {CR55, 4, 6} } },
437 /* IGA2 Horizontal Blank Start */
438 {IGA2_HOR_BLANK_START_REG_NUM, {{CR52, 0, 7}, {CR54, 0, 2} } },
439 /* IGA2 Horizontal Blank End */
440 {IGA2_HOR_BLANK_END_REG_NUM,
441 {{CR53, 0, 7}, {CR54, 3, 5}, {CR5D, 6, 6} } },
442 /* IGA2 Horizontal Sync Start */
443 {IGA2_HOR_SYNC_START_REG_NUM,
444 {{CR56, 0, 7}, {CR54, 6, 7}, {CR5C, 7, 7}, {CR5D, 7, 7} } },
445 /* IGA2 Horizontal Sync End */
446 {IGA2_HOR_SYNC_END_REG_NUM, {{CR57, 0, 7}, {CR5C, 6, 6} } },
447 /* IGA2 Vertical Total */
448 {IGA2_VER_TOTAL_REG_NUM, {{CR58, 0, 7}, {CR5D, 0, 2} } },
449 /* IGA2 Vertical Addressable Video */
450 {IGA2_VER_ADDR_REG_NUM, {{CR59, 0, 7}, {CR5D, 3, 5} } },
451 /* IGA2 Vertical Blank Start */
452 {IGA2_VER_BLANK_START_REG_NUM, {{CR5A, 0, 7}, {CR5C, 0, 2} } },
453 /* IGA2 Vertical Blank End */
454 {IGA2_VER_BLANK_END_REG_NUM, {{CR5B, 0, 7}, {CR5C, 3, 5} } },
455 /* IGA2 Vertical Sync Start */
456 {IGA2_VER_SYNC_START_REG_NUM, {{CR5E, 0, 7}, {CR5F, 5, 7} } },
457 /* IGA2 Vertical Sync End */
458 {IGA2_VER_SYNC_END_REG_NUM, {{CR5F, 0, 4} } }
461 static struct rgbLUT palLUT_table[] = {
463 /* Index 0x00~0x03 */
464 {0x00, 0x00, 0x00}, {0x00, 0x00, 0x2A}, {0x00, 0x2A, 0x00}, {0x00,
467 /* Index 0x04~0x07 */
468 {0x2A, 0x00, 0x00}, {0x2A, 0x00, 0x2A}, {0x2A, 0x15, 0x00}, {0x2A,
471 /* Index 0x08~0x0B */
472 {0x15, 0x15, 0x15}, {0x15, 0x15, 0x3F}, {0x15, 0x3F, 0x15}, {0x15,
475 /* Index 0x0C~0x0F */
476 {0x3F, 0x15, 0x15}, {0x3F, 0x15, 0x3F}, {0x3F, 0x3F, 0x15}, {0x3F,
479 /* Index 0x10~0x13 */
480 {0x00, 0x00, 0x00}, {0x05, 0x05, 0x05}, {0x08, 0x08, 0x08}, {0x0B,
483 /* Index 0x14~0x17 */
484 {0x0E, 0x0E, 0x0E}, {0x11, 0x11, 0x11}, {0x14, 0x14, 0x14}, {0x18,
487 /* Index 0x18~0x1B */
488 {0x1C, 0x1C, 0x1C}, {0x20, 0x20, 0x20}, {0x24, 0x24, 0x24}, {0x28,
491 /* Index 0x1C~0x1F */
492 {0x2D, 0x2D, 0x2D}, {0x32, 0x32, 0x32}, {0x38, 0x38, 0x38}, {0x3F,
495 /* Index 0x20~0x23 */
496 {0x00, 0x00, 0x3F}, {0x10, 0x00, 0x3F}, {0x1F, 0x00, 0x3F}, {0x2F,
499 /* Index 0x24~0x27 */
500 {0x3F, 0x00, 0x3F}, {0x3F, 0x00, 0x2F}, {0x3F, 0x00, 0x1F}, {0x3F,
503 /* Index 0x28~0x2B */
504 {0x3F, 0x00, 0x00}, {0x3F, 0x10, 0x00}, {0x3F, 0x1F, 0x00}, {0x3F,
507 /* Index 0x2C~0x2F */
508 {0x3F, 0x3F, 0x00}, {0x2F, 0x3F, 0x00}, {0x1F, 0x3F, 0x00}, {0x10,
511 /* Index 0x30~0x33 */
512 {0x00, 0x3F, 0x00}, {0x00, 0x3F, 0x10}, {0x00, 0x3F, 0x1F}, {0x00,
515 /* Index 0x34~0x37 */
516 {0x00, 0x3F, 0x3F}, {0x00, 0x2F, 0x3F}, {0x00, 0x1F, 0x3F}, {0x00,
519 /* Index 0x38~0x3B */
520 {0x1F, 0x1F, 0x3F}, {0x27, 0x1F, 0x3F}, {0x2F, 0x1F, 0x3F}, {0x37,
523 /* Index 0x3C~0x3F */
524 {0x3F, 0x1F, 0x3F}, {0x3F, 0x1F, 0x37}, {0x3F, 0x1F, 0x2F}, {0x3F,
527 /* Index 0x40~0x43 */
528 {0x3F, 0x1F, 0x1F}, {0x3F, 0x27, 0x1F}, {0x3F, 0x2F, 0x1F}, {0x3F,
531 /* Index 0x44~0x47 */
532 {0x3F, 0x3F, 0x1F}, {0x37, 0x3F, 0x1F}, {0x2F, 0x3F, 0x1F}, {0x27,
535 /* Index 0x48~0x4B */
536 {0x1F, 0x3F, 0x1F}, {0x1F, 0x3F, 0x27}, {0x1F, 0x3F, 0x2F}, {0x1F,
539 /* Index 0x4C~0x4F */
540 {0x1F, 0x3F, 0x3F}, {0x1F, 0x37, 0x3F}, {0x1F, 0x2F, 0x3F}, {0x1F,
543 /* Index 0x50~0x53 */
544 {0x2D, 0x2D, 0x3F}, {0x31, 0x2D, 0x3F}, {0x36, 0x2D, 0x3F}, {0x3A,
547 /* Index 0x54~0x57 */
548 {0x3F, 0x2D, 0x3F}, {0x3F, 0x2D, 0x3A}, {0x3F, 0x2D, 0x36}, {0x3F,
551 /* Index 0x58~0x5B */
552 {0x3F, 0x2D, 0x2D}, {0x3F, 0x31, 0x2D}, {0x3F, 0x36, 0x2D}, {0x3F,
555 /* Index 0x5C~0x5F */
556 {0x3F, 0x3F, 0x2D}, {0x3A, 0x3F, 0x2D}, {0x36, 0x3F, 0x2D}, {0x31,
559 /* Index 0x60~0x63 */
560 {0x2D, 0x3F, 0x2D}, {0x2D, 0x3F, 0x31}, {0x2D, 0x3F, 0x36}, {0x2D,
563 /* Index 0x64~0x67 */
564 {0x2D, 0x3F, 0x3F}, {0x2D, 0x3A, 0x3F}, {0x2D, 0x36, 0x3F}, {0x2D,
567 /* Index 0x68~0x6B */
568 {0x00, 0x00, 0x1C}, {0x07, 0x00, 0x1C}, {0x0E, 0x00, 0x1C}, {0x15,
571 /* Index 0x6C~0x6F */
572 {0x1C, 0x00, 0x1C}, {0x1C, 0x00, 0x15}, {0x1C, 0x00, 0x0E}, {0x1C,
575 /* Index 0x70~0x73 */
576 {0x1C, 0x00, 0x00}, {0x1C, 0x07, 0x00}, {0x1C, 0x0E, 0x00}, {0x1C,
579 /* Index 0x74~0x77 */
580 {0x1C, 0x1C, 0x00}, {0x15, 0x1C, 0x00}, {0x0E, 0x1C, 0x00}, {0x07,
583 /* Index 0x78~0x7B */
584 {0x00, 0x1C, 0x00}, {0x00, 0x1C, 0x07}, {0x00, 0x1C, 0x0E}, {0x00,
587 /* Index 0x7C~0x7F */
588 {0x00, 0x1C, 0x1C}, {0x00, 0x15, 0x1C}, {0x00, 0x0E, 0x1C}, {0x00,
591 /* Index 0x80~0x83 */
592 {0x0E, 0x0E, 0x1C}, {0x11, 0x0E, 0x1C}, {0x15, 0x0E, 0x1C}, {0x18,
595 /* Index 0x84~0x87 */
596 {0x1C, 0x0E, 0x1C}, {0x1C, 0x0E, 0x18}, {0x1C, 0x0E, 0x15}, {0x1C,
599 /* Index 0x88~0x8B */
600 {0x1C, 0x0E, 0x0E}, {0x1C, 0x11, 0x0E}, {0x1C, 0x15, 0x0E}, {0x1C,
603 /* Index 0x8C~0x8F */
604 {0x1C, 0x1C, 0x0E}, {0x18, 0x1C, 0x0E}, {0x15, 0x1C, 0x0E}, {0x11,
607 /* Index 0x90~0x93 */
608 {0x0E, 0x1C, 0x0E}, {0x0E, 0x1C, 0x11}, {0x0E, 0x1C, 0x15}, {0x0E,
611 /* Index 0x94~0x97 */
612 {0x0E, 0x1C, 0x1C}, {0x0E, 0x18, 0x1C}, {0x0E, 0x15, 0x1C}, {0x0E,
615 /* Index 0x98~0x9B */
616 {0x14, 0x14, 0x1C}, {0x16, 0x14, 0x1C}, {0x18, 0x14, 0x1C}, {0x1A,
619 /* Index 0x9C~0x9F */
620 {0x1C, 0x14, 0x1C}, {0x1C, 0x14, 0x1A}, {0x1C, 0x14, 0x18}, {0x1C,
623 /* Index 0xA0~0xA3 */
624 {0x1C, 0x14, 0x14}, {0x1C, 0x16, 0x14}, {0x1C, 0x18, 0x14}, {0x1C,
627 /* Index 0xA4~0xA7 */
628 {0x1C, 0x1C, 0x14}, {0x1A, 0x1C, 0x14}, {0x18, 0x1C, 0x14}, {0x16,
631 /* Index 0xA8~0xAB */
632 {0x14, 0x1C, 0x14}, {0x14, 0x1C, 0x16}, {0x14, 0x1C, 0x18}, {0x14,
635 /* Index 0xAC~0xAF */
636 {0x14, 0x1C, 0x1C}, {0x14, 0x1A, 0x1C}, {0x14, 0x18, 0x1C}, {0x14,
639 /* Index 0xB0~0xB3 */
640 {0x00, 0x00, 0x10}, {0x04, 0x00, 0x10}, {0x08, 0x00, 0x10}, {0x0C,
643 /* Index 0xB4~0xB7 */
644 {0x10, 0x00, 0x10}, {0x10, 0x00, 0x0C}, {0x10, 0x00, 0x08}, {0x10,
647 /* Index 0xB8~0xBB */
648 {0x10, 0x00, 0x00}, {0x10, 0x04, 0x00}, {0x10, 0x08, 0x00}, {0x10,
651 /* Index 0xBC~0xBF */
652 {0x10, 0x10, 0x00}, {0x0C, 0x10, 0x00}, {0x08, 0x10, 0x00}, {0x04,
655 /* Index 0xC0~0xC3 */
656 {0x00, 0x10, 0x00}, {0x00, 0x10, 0x04}, {0x00, 0x10, 0x08}, {0x00,
659 /* Index 0xC4~0xC7 */
660 {0x00, 0x10, 0x10}, {0x00, 0x0C, 0x10}, {0x00, 0x08, 0x10}, {0x00,
663 /* Index 0xC8~0xCB */
664 {0x08, 0x08, 0x10}, {0x0A, 0x08, 0x10}, {0x0C, 0x08, 0x10}, {0x0E,
667 /* Index 0xCC~0xCF */
668 {0x10, 0x08, 0x10}, {0x10, 0x08, 0x0E}, {0x10, 0x08, 0x0C}, {0x10,
671 /* Index 0xD0~0xD3 */
672 {0x10, 0x08, 0x08}, {0x10, 0x0A, 0x08}, {0x10, 0x0C, 0x08}, {0x10,
675 /* Index 0xD4~0xD7 */
676 {0x10, 0x10, 0x08}, {0x0E, 0x10, 0x08}, {0x0C, 0x10, 0x08}, {0x0A,
679 /* Index 0xD8~0xDB */
680 {0x08, 0x10, 0x08}, {0x08, 0x10, 0x0A}, {0x08, 0x10, 0x0C}, {0x08,
683 /* Index 0xDC~0xDF */
684 {0x08, 0x10, 0x10}, {0x08, 0x0E, 0x10}, {0x08, 0x0C, 0x10}, {0x08,
687 /* Index 0xE0~0xE3 */
688 {0x0B, 0x0B, 0x10}, {0x0C, 0x0B, 0x10}, {0x0D, 0x0B, 0x10}, {0x0F,
691 /* Index 0xE4~0xE7 */
692 {0x10, 0x0B, 0x10}, {0x10, 0x0B, 0x0F}, {0x10, 0x0B, 0x0D}, {0x10,
695 /* Index 0xE8~0xEB */
696 {0x10, 0x0B, 0x0B}, {0x10, 0x0C, 0x0B}, {0x10, 0x0D, 0x0B}, {0x10,
699 /* Index 0xEC~0xEF */
700 {0x10, 0x10, 0x0B}, {0x0F, 0x10, 0x0B}, {0x0D, 0x10, 0x0B}, {0x0C,
703 /* Index 0xF0~0xF3 */
704 {0x0B, 0x10, 0x0B}, {0x0B, 0x10, 0x0C}, {0x0B, 0x10, 0x0D}, {0x0B,
707 /* Index 0xF4~0xF7 */
708 {0x0B, 0x10, 0x10}, {0x0B, 0x0F, 0x10}, {0x0B, 0x0D, 0x10}, {0x0B,
711 /* Index 0xF8~0xFB */
712 {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00,
715 /* Index 0xFC~0xFF */
716 {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00,
721 static struct via_device_mapping device_mapping[] = {
727 {VIA_LVDS1, "LVDS1"},
731 static void load_fix_bit_crtc_reg(void);
732 static void __devinit init_gfx_chip_info(int chip_type);
733 static void __devinit init_tmds_chip_info(void);
734 static void __devinit init_lvds_chip_info(void);
735 static void device_screen_off(void);
736 static void device_screen_on(void);
737 static void set_display_channel(void);
738 static void device_off(void);
739 static void device_on(void);
740 static void enable_second_display_channel(void);
741 static void disable_second_display_channel(void);
743 void viafb_lock_crt(void)
745 viafb_write_reg_mask(CR11, VIACR, BIT7, BIT7);
748 void viafb_unlock_crt(void)
750 viafb_write_reg_mask(CR11, VIACR, 0, BIT7);
751 viafb_write_reg_mask(CR47, VIACR, 0, BIT0);
754 void write_dac_reg(u8 index, u8 r, u8 g, u8 b)
756 outb(index, LUT_INDEX_WRITE);
762 static u32 get_dvi_devices(int output_interface)
764 switch (output_interface) {
766 return VIA_96 | VIA_6C;
769 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
774 case INTERFACE_DFP_HIGH:
775 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
778 return VIA_LVDS2 | VIA_96;
780 case INTERFACE_DFP_LOW:
781 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
784 return VIA_DVP1 | VIA_LVDS1;
793 static u32 get_lcd_devices(int output_interface)
795 switch (output_interface) {
802 case INTERFACE_DFP_HIGH:
803 return VIA_LVDS2 | VIA_96;
805 case INTERFACE_DFP_LOW:
806 return VIA_LVDS1 | VIA_DVP1;
809 return VIA_LVDS1 | VIA_LVDS2;
811 case INTERFACE_LVDS0:
812 case INTERFACE_LVDS0LVDS1:
815 case INTERFACE_LVDS1:
822 /*Set IGA path for each device*/
823 void viafb_set_iga_path(void)
826 if (viafb_SAMM_ON == 1) {
828 if (viafb_primary_dev == CRT_Device)
829 viaparinfo->crt_setting_info->iga_path = IGA1;
831 viaparinfo->crt_setting_info->iga_path = IGA2;
835 if (viafb_primary_dev == DVI_Device)
836 viaparinfo->tmds_setting_info->iga_path = IGA1;
838 viaparinfo->tmds_setting_info->iga_path = IGA2;
842 if (viafb_primary_dev == LCD_Device) {
844 (viaparinfo->chip_info->gfx_chip_name ==
847 lvds_setting_info->iga_path = IGA2;
849 crt_setting_info->iga_path = IGA1;
851 tmds_setting_info->iga_path = IGA1;
854 lvds_setting_info->iga_path = IGA1;
856 viaparinfo->lvds_setting_info->iga_path = IGA2;
860 if (LCD2_Device == viafb_primary_dev)
861 viaparinfo->lvds_setting_info2->iga_path = IGA1;
863 viaparinfo->lvds_setting_info2->iga_path = IGA2;
868 if (viafb_CRT_ON && viafb_LCD_ON) {
869 viaparinfo->crt_setting_info->iga_path = IGA1;
870 viaparinfo->lvds_setting_info->iga_path = IGA2;
871 } else if (viafb_CRT_ON && viafb_DVI_ON) {
872 viaparinfo->crt_setting_info->iga_path = IGA1;
873 viaparinfo->tmds_setting_info->iga_path = IGA2;
874 } else if (viafb_LCD_ON && viafb_DVI_ON) {
875 viaparinfo->tmds_setting_info->iga_path = IGA1;
876 viaparinfo->lvds_setting_info->iga_path = IGA2;
877 } else if (viafb_LCD_ON && viafb_LCD2_ON) {
878 viaparinfo->lvds_setting_info->iga_path = IGA2;
879 viaparinfo->lvds_setting_info2->iga_path = IGA2;
880 } else if (viafb_CRT_ON) {
881 viaparinfo->crt_setting_info->iga_path = IGA1;
882 } else if (viafb_LCD_ON) {
883 viaparinfo->lvds_setting_info->iga_path = IGA2;
884 } else if (viafb_DVI_ON) {
885 viaparinfo->tmds_setting_info->iga_path = IGA1;
889 viaparinfo->shared->iga1_devices = 0;
890 viaparinfo->shared->iga2_devices = 0;
892 if (viaparinfo->crt_setting_info->iga_path == IGA1)
893 viaparinfo->shared->iga1_devices |= VIA_CRT;
895 viaparinfo->shared->iga2_devices |= VIA_CRT;
899 if (viaparinfo->tmds_setting_info->iga_path == IGA1)
900 viaparinfo->shared->iga1_devices |= get_dvi_devices(
901 viaparinfo->chip_info->
902 tmds_chip_info.output_interface);
904 viaparinfo->shared->iga2_devices |= get_dvi_devices(
905 viaparinfo->chip_info->
906 tmds_chip_info.output_interface);
910 if (viaparinfo->lvds_setting_info->iga_path == IGA1)
911 viaparinfo->shared->iga1_devices |= get_lcd_devices(
912 viaparinfo->chip_info->
913 lvds_chip_info.output_interface);
915 viaparinfo->shared->iga2_devices |= get_lcd_devices(
916 viaparinfo->chip_info->
917 lvds_chip_info.output_interface);
921 if (viaparinfo->lvds_setting_info2->iga_path == IGA1)
922 viaparinfo->shared->iga1_devices |= get_lcd_devices(
923 viaparinfo->chip_info->
924 lvds_chip_info2.output_interface);
926 viaparinfo->shared->iga2_devices |= get_lcd_devices(
927 viaparinfo->chip_info->
928 lvds_chip_info2.output_interface);
932 static void set_color_register(u8 index, u8 red, u8 green, u8 blue)
934 outb(0xFF, 0x3C6); /* bit mask of palette */
941 void viafb_set_primary_color_register(u8 index, u8 red, u8 green, u8 blue)
943 viafb_write_reg_mask(0x1A, VIASR, 0x00, 0x01);
944 set_color_register(index, red, green, blue);
947 void viafb_set_secondary_color_register(u8 index, u8 red, u8 green, u8 blue)
949 viafb_write_reg_mask(0x1A, VIASR, 0x01, 0x01);
950 set_color_register(index, red, green, blue);
953 static void set_source_common(u8 index, u8 offset, u8 iga)
955 u8 value, mask = 1 << offset;
965 printk(KERN_WARNING "viafb: Unsupported source: %d\n", iga);
969 via_write_reg_mask(VIACR, index, value, mask);
972 static void set_crt_source(u8 iga)
984 printk(KERN_WARNING "viafb: Unsupported source: %d\n", iga);
988 via_write_reg_mask(VIASR, 0x16, value, 0x40);
991 static inline void set_6C_source(u8 iga)
993 set_source_common(0x6C, 7, iga);
996 static inline void set_93_source(u8 iga)
998 set_source_common(0x93, 7, iga);
1001 static inline void set_96_source(u8 iga)
1003 set_source_common(0x96, 4, iga);
1006 static inline void set_dvp1_source(u8 iga)
1008 set_source_common(0x9B, 4, iga);
1011 static inline void set_lvds1_source(u8 iga)
1013 set_source_common(0x99, 4, iga);
1016 static inline void set_lvds2_source(u8 iga)
1018 set_source_common(0x97, 4, iga);
1021 void via_set_source(u32 devices, u8 iga)
1023 if (devices & VIA_6C)
1025 if (devices & VIA_93)
1027 if (devices & VIA_96)
1029 if (devices & VIA_CRT)
1030 set_crt_source(iga);
1031 if (devices & VIA_DVP1)
1032 set_dvp1_source(iga);
1033 if (devices & VIA_LVDS1)
1034 set_lvds1_source(iga);
1035 if (devices & VIA_LVDS2)
1036 set_lvds2_source(iga);
1039 u32 via_parse_odev(char *input, char **end)
1048 for (i = 0; i < ARRAY_SIZE(device_mapping); i++) {
1049 len = strlen(device_mapping[i].name);
1050 if (!strncmp(ptr, device_mapping[i].name, len)) {
1051 odev |= device_mapping[i].device;
1065 void via_odev_to_seq(struct seq_file *m, u32 odev)
1069 for (i = 0; i < ARRAY_SIZE(device_mapping); i++) {
1070 if (odev & device_mapping[i].device) {
1074 seq_puts(m, device_mapping[i].name);
1082 static void load_fix_bit_crtc_reg(void)
1084 /* always set to 1 */
1085 viafb_write_reg_mask(CR03, VIACR, 0x80, BIT7);
1086 /* line compare should set all bits = 1 (extend modes) */
1087 viafb_write_reg(CR18, VIACR, 0xff);
1088 /* line compare should set all bits = 1 (extend modes) */
1089 viafb_write_reg_mask(CR07, VIACR, 0x10, BIT4);
1090 /* line compare should set all bits = 1 (extend modes) */
1091 viafb_write_reg_mask(CR09, VIACR, 0x40, BIT6);
1092 /* line compare should set all bits = 1 (extend modes) */
1093 viafb_write_reg_mask(CR35, VIACR, 0x10, BIT4);
1094 /* line compare should set all bits = 1 (extend modes) */
1095 viafb_write_reg_mask(CR33, VIACR, 0x06, BIT0 + BIT1 + BIT2);
1096 /*viafb_write_reg_mask(CR32, VIACR, 0x01, BIT0); */
1097 /* extend mode always set to e3h */
1098 viafb_write_reg(CR17, VIACR, 0xe3);
1099 /* extend mode always set to 0h */
1100 viafb_write_reg(CR08, VIACR, 0x00);
1101 /* extend mode always set to 0h */
1102 viafb_write_reg(CR14, VIACR, 0x00);
1104 /* If K8M800, enable Prefetch Mode. */
1105 if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800)
1106 || (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890))
1107 viafb_write_reg_mask(CR33, VIACR, 0x08, BIT3);
1108 if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
1109 && (viaparinfo->chip_info->gfx_chip_revision == CLE266_REVISION_AX))
1110 viafb_write_reg_mask(SR1A, VIASR, 0x02, BIT1);
1114 void viafb_load_reg(int timing_value, int viafb_load_reg_num,
1115 struct io_register *reg,
1123 int start_index, end_index, cr_index;
1126 for (i = 0; i < viafb_load_reg_num; i++) {
1129 start_index = reg[i].start_bit;
1130 end_index = reg[i].end_bit;
1131 cr_index = reg[i].io_addr;
1133 shift_next_reg = bit_num;
1134 for (j = start_index; j <= end_index; j++) {
1135 /*if (bit_num==8) timing_value = timing_value >>8; */
1136 reg_mask = reg_mask | (BIT0 << j);
1137 get_bit = (timing_value & (BIT0 << bit_num));
1139 data | ((get_bit >> shift_next_reg) << start_index);
1142 if (io_type == VIACR)
1143 viafb_write_reg_mask(cr_index, VIACR, data, reg_mask);
1145 viafb_write_reg_mask(cr_index, VIASR, data, reg_mask);
1150 /* Write Registers */
1151 void viafb_write_regx(struct io_reg RegTable[], int ItemNum)
1155 /*DEBUG_MSG(KERN_INFO "Table Size : %x!!\n",ItemNum ); */
1157 for (i = 0; i < ItemNum; i++)
1158 via_write_reg_mask(RegTable[i].port, RegTable[i].index,
1159 RegTable[i].value, RegTable[i].mask);
1162 void viafb_load_fetch_count_reg(int h_addr, int bpp_byte, int set_iga)
1165 int viafb_load_reg_num;
1166 struct io_register *reg = NULL;
1170 reg_value = IGA1_FETCH_COUNT_FORMULA(h_addr, bpp_byte);
1171 viafb_load_reg_num = fetch_count_reg.
1172 iga1_fetch_count_reg.reg_num;
1173 reg = fetch_count_reg.iga1_fetch_count_reg.reg;
1174 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1177 reg_value = IGA2_FETCH_COUNT_FORMULA(h_addr, bpp_byte);
1178 viafb_load_reg_num = fetch_count_reg.
1179 iga2_fetch_count_reg.reg_num;
1180 reg = fetch_count_reg.iga2_fetch_count_reg.reg;
1181 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1187 void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active)
1190 int viafb_load_reg_num;
1191 struct io_register *reg = NULL;
1192 int iga1_fifo_max_depth = 0, iga1_fifo_threshold =
1193 0, iga1_fifo_high_threshold = 0, iga1_display_queue_expire_num = 0;
1194 int iga2_fifo_max_depth = 0, iga2_fifo_threshold =
1195 0, iga2_fifo_high_threshold = 0, iga2_display_queue_expire_num = 0;
1197 if (set_iga == IGA1) {
1198 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1199 iga1_fifo_max_depth = K800_IGA1_FIFO_MAX_DEPTH;
1200 iga1_fifo_threshold = K800_IGA1_FIFO_THRESHOLD;
1201 iga1_fifo_high_threshold =
1202 K800_IGA1_FIFO_HIGH_THRESHOLD;
1203 /* If resolution > 1280x1024, expire length = 64, else
1204 expire length = 128 */
1205 if ((hor_active > 1280) && (ver_active > 1024))
1206 iga1_display_queue_expire_num = 16;
1208 iga1_display_queue_expire_num =
1209 K800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1213 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_PM800) {
1214 iga1_fifo_max_depth = P880_IGA1_FIFO_MAX_DEPTH;
1215 iga1_fifo_threshold = P880_IGA1_FIFO_THRESHOLD;
1216 iga1_fifo_high_threshold =
1217 P880_IGA1_FIFO_HIGH_THRESHOLD;
1218 iga1_display_queue_expire_num =
1219 P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1221 /* If resolution > 1280x1024, expire length = 64, else
1222 expire length = 128 */
1223 if ((hor_active > 1280) && (ver_active > 1024))
1224 iga1_display_queue_expire_num = 16;
1226 iga1_display_queue_expire_num =
1227 P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1230 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CN700) {
1231 iga1_fifo_max_depth = CN700_IGA1_FIFO_MAX_DEPTH;
1232 iga1_fifo_threshold = CN700_IGA1_FIFO_THRESHOLD;
1233 iga1_fifo_high_threshold =
1234 CN700_IGA1_FIFO_HIGH_THRESHOLD;
1236 /* If resolution > 1280x1024, expire length = 64,
1237 else expire length = 128 */
1238 if ((hor_active > 1280) && (ver_active > 1024))
1239 iga1_display_queue_expire_num = 16;
1241 iga1_display_queue_expire_num =
1242 CN700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1245 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
1246 iga1_fifo_max_depth = CX700_IGA1_FIFO_MAX_DEPTH;
1247 iga1_fifo_threshold = CX700_IGA1_FIFO_THRESHOLD;
1248 iga1_fifo_high_threshold =
1249 CX700_IGA1_FIFO_HIGH_THRESHOLD;
1250 iga1_display_queue_expire_num =
1251 CX700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1254 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890) {
1255 iga1_fifo_max_depth = K8M890_IGA1_FIFO_MAX_DEPTH;
1256 iga1_fifo_threshold = K8M890_IGA1_FIFO_THRESHOLD;
1257 iga1_fifo_high_threshold =
1258 K8M890_IGA1_FIFO_HIGH_THRESHOLD;
1259 iga1_display_queue_expire_num =
1260 K8M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1263 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M890) {
1264 iga1_fifo_max_depth = P4M890_IGA1_FIFO_MAX_DEPTH;
1265 iga1_fifo_threshold = P4M890_IGA1_FIFO_THRESHOLD;
1266 iga1_fifo_high_threshold =
1267 P4M890_IGA1_FIFO_HIGH_THRESHOLD;
1268 iga1_display_queue_expire_num =
1269 P4M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1272 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M900) {
1273 iga1_fifo_max_depth = P4M900_IGA1_FIFO_MAX_DEPTH;
1274 iga1_fifo_threshold = P4M900_IGA1_FIFO_THRESHOLD;
1275 iga1_fifo_high_threshold =
1276 P4M900_IGA1_FIFO_HIGH_THRESHOLD;
1277 iga1_display_queue_expire_num =
1278 P4M900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1281 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX800) {
1282 iga1_fifo_max_depth = VX800_IGA1_FIFO_MAX_DEPTH;
1283 iga1_fifo_threshold = VX800_IGA1_FIFO_THRESHOLD;
1284 iga1_fifo_high_threshold =
1285 VX800_IGA1_FIFO_HIGH_THRESHOLD;
1286 iga1_display_queue_expire_num =
1287 VX800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1290 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX855) {
1291 iga1_fifo_max_depth = VX855_IGA1_FIFO_MAX_DEPTH;
1292 iga1_fifo_threshold = VX855_IGA1_FIFO_THRESHOLD;
1293 iga1_fifo_high_threshold =
1294 VX855_IGA1_FIFO_HIGH_THRESHOLD;
1295 iga1_display_queue_expire_num =
1296 VX855_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1299 /* Set Display FIFO Depath Select */
1300 reg_value = IGA1_FIFO_DEPTH_SELECT_FORMULA(iga1_fifo_max_depth);
1301 viafb_load_reg_num =
1302 display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg_num;
1303 reg = display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg;
1304 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1306 /* Set Display FIFO Threshold Select */
1307 reg_value = IGA1_FIFO_THRESHOLD_FORMULA(iga1_fifo_threshold);
1308 viafb_load_reg_num =
1309 fifo_threshold_select_reg.
1310 iga1_fifo_threshold_select_reg.reg_num;
1312 fifo_threshold_select_reg.
1313 iga1_fifo_threshold_select_reg.reg;
1314 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1316 /* Set FIFO High Threshold Select */
1318 IGA1_FIFO_HIGH_THRESHOLD_FORMULA(iga1_fifo_high_threshold);
1319 viafb_load_reg_num =
1320 fifo_high_threshold_select_reg.
1321 iga1_fifo_high_threshold_select_reg.reg_num;
1323 fifo_high_threshold_select_reg.
1324 iga1_fifo_high_threshold_select_reg.reg;
1325 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1327 /* Set Display Queue Expire Num */
1329 IGA1_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA
1330 (iga1_display_queue_expire_num);
1331 viafb_load_reg_num =
1332 display_queue_expire_num_reg.
1333 iga1_display_queue_expire_num_reg.reg_num;
1335 display_queue_expire_num_reg.
1336 iga1_display_queue_expire_num_reg.reg;
1337 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1340 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1341 iga2_fifo_max_depth = K800_IGA2_FIFO_MAX_DEPTH;
1342 iga2_fifo_threshold = K800_IGA2_FIFO_THRESHOLD;
1343 iga2_fifo_high_threshold =
1344 K800_IGA2_FIFO_HIGH_THRESHOLD;
1346 /* If resolution > 1280x1024, expire length = 64,
1347 else expire length = 128 */
1348 if ((hor_active > 1280) && (ver_active > 1024))
1349 iga2_display_queue_expire_num = 16;
1351 iga2_display_queue_expire_num =
1352 K800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1355 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_PM800) {
1356 iga2_fifo_max_depth = P880_IGA2_FIFO_MAX_DEPTH;
1357 iga2_fifo_threshold = P880_IGA2_FIFO_THRESHOLD;
1358 iga2_fifo_high_threshold =
1359 P880_IGA2_FIFO_HIGH_THRESHOLD;
1361 /* If resolution > 1280x1024, expire length = 64,
1362 else expire length = 128 */
1363 if ((hor_active > 1280) && (ver_active > 1024))
1364 iga2_display_queue_expire_num = 16;
1366 iga2_display_queue_expire_num =
1367 P880_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1370 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CN700) {
1371 iga2_fifo_max_depth = CN700_IGA2_FIFO_MAX_DEPTH;
1372 iga2_fifo_threshold = CN700_IGA2_FIFO_THRESHOLD;
1373 iga2_fifo_high_threshold =
1374 CN700_IGA2_FIFO_HIGH_THRESHOLD;
1376 /* If resolution > 1280x1024, expire length = 64,
1377 else expire length = 128 */
1378 if ((hor_active > 1280) && (ver_active > 1024))
1379 iga2_display_queue_expire_num = 16;
1381 iga2_display_queue_expire_num =
1382 CN700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1385 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
1386 iga2_fifo_max_depth = CX700_IGA2_FIFO_MAX_DEPTH;
1387 iga2_fifo_threshold = CX700_IGA2_FIFO_THRESHOLD;
1388 iga2_fifo_high_threshold =
1389 CX700_IGA2_FIFO_HIGH_THRESHOLD;
1390 iga2_display_queue_expire_num =
1391 CX700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1394 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890) {
1395 iga2_fifo_max_depth = K8M890_IGA2_FIFO_MAX_DEPTH;
1396 iga2_fifo_threshold = K8M890_IGA2_FIFO_THRESHOLD;
1397 iga2_fifo_high_threshold =
1398 K8M890_IGA2_FIFO_HIGH_THRESHOLD;
1399 iga2_display_queue_expire_num =
1400 K8M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1403 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M890) {
1404 iga2_fifo_max_depth = P4M890_IGA2_FIFO_MAX_DEPTH;
1405 iga2_fifo_threshold = P4M890_IGA2_FIFO_THRESHOLD;
1406 iga2_fifo_high_threshold =
1407 P4M890_IGA2_FIFO_HIGH_THRESHOLD;
1408 iga2_display_queue_expire_num =
1409 P4M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1412 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M900) {
1413 iga2_fifo_max_depth = P4M900_IGA2_FIFO_MAX_DEPTH;
1414 iga2_fifo_threshold = P4M900_IGA2_FIFO_THRESHOLD;
1415 iga2_fifo_high_threshold =
1416 P4M900_IGA2_FIFO_HIGH_THRESHOLD;
1417 iga2_display_queue_expire_num =
1418 P4M900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1421 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX800) {
1422 iga2_fifo_max_depth = VX800_IGA2_FIFO_MAX_DEPTH;
1423 iga2_fifo_threshold = VX800_IGA2_FIFO_THRESHOLD;
1424 iga2_fifo_high_threshold =
1425 VX800_IGA2_FIFO_HIGH_THRESHOLD;
1426 iga2_display_queue_expire_num =
1427 VX800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1430 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX855) {
1431 iga2_fifo_max_depth = VX855_IGA2_FIFO_MAX_DEPTH;
1432 iga2_fifo_threshold = VX855_IGA2_FIFO_THRESHOLD;
1433 iga2_fifo_high_threshold =
1434 VX855_IGA2_FIFO_HIGH_THRESHOLD;
1435 iga2_display_queue_expire_num =
1436 VX855_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1439 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1440 /* Set Display FIFO Depath Select */
1442 IGA2_FIFO_DEPTH_SELECT_FORMULA(iga2_fifo_max_depth)
1444 /* Patch LCD in IGA2 case */
1445 viafb_load_reg_num =
1446 display_fifo_depth_reg.
1447 iga2_fifo_depth_select_reg.reg_num;
1449 display_fifo_depth_reg.
1450 iga2_fifo_depth_select_reg.reg;
1451 viafb_load_reg(reg_value,
1452 viafb_load_reg_num, reg, VIACR);
1455 /* Set Display FIFO Depath Select */
1457 IGA2_FIFO_DEPTH_SELECT_FORMULA(iga2_fifo_max_depth);
1458 viafb_load_reg_num =
1459 display_fifo_depth_reg.
1460 iga2_fifo_depth_select_reg.reg_num;
1462 display_fifo_depth_reg.
1463 iga2_fifo_depth_select_reg.reg;
1464 viafb_load_reg(reg_value,
1465 viafb_load_reg_num, reg, VIACR);
1468 /* Set Display FIFO Threshold Select */
1469 reg_value = IGA2_FIFO_THRESHOLD_FORMULA(iga2_fifo_threshold);
1470 viafb_load_reg_num =
1471 fifo_threshold_select_reg.
1472 iga2_fifo_threshold_select_reg.reg_num;
1474 fifo_threshold_select_reg.
1475 iga2_fifo_threshold_select_reg.reg;
1476 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1478 /* Set FIFO High Threshold Select */
1480 IGA2_FIFO_HIGH_THRESHOLD_FORMULA(iga2_fifo_high_threshold);
1481 viafb_load_reg_num =
1482 fifo_high_threshold_select_reg.
1483 iga2_fifo_high_threshold_select_reg.reg_num;
1485 fifo_high_threshold_select_reg.
1486 iga2_fifo_high_threshold_select_reg.reg;
1487 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1489 /* Set Display Queue Expire Num */
1491 IGA2_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA
1492 (iga2_display_queue_expire_num);
1493 viafb_load_reg_num =
1494 display_queue_expire_num_reg.
1495 iga2_display_queue_expire_num_reg.reg_num;
1497 display_queue_expire_num_reg.
1498 iga2_display_queue_expire_num_reg.reg;
1499 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1505 static u32 cle266_encode_pll(struct pll_config pll)
1507 return (pll.multiplier << 8)
1512 static u32 k800_encode_pll(struct pll_config pll)
1514 return ((pll.divisor - 2) << 16)
1515 | (pll.rshift << 10)
1516 | (pll.multiplier - 2);
1519 static u32 vx855_encode_pll(struct pll_config pll)
1521 return (pll.divisor << 16)
1522 | (pll.rshift << 10)
1526 u32 viafb_get_clk_value(int clk)
1531 while (i < NUM_TOTAL_PLL_TABLE && clk != pll_value[i].clk)
1534 if (i == NUM_TOTAL_PLL_TABLE) {
1535 printk(KERN_WARNING "viafb_get_clk_value: PLL lookup failed!");
1537 switch (viaparinfo->chip_info->gfx_chip_name) {
1538 case UNICHROME_CLE266:
1539 case UNICHROME_K400:
1540 value = cle266_encode_pll(pll_value[i].cle266_pll);
1543 case UNICHROME_K800:
1544 case UNICHROME_PM800:
1545 case UNICHROME_CN700:
1546 value = k800_encode_pll(pll_value[i].k800_pll);
1549 case UNICHROME_CX700:
1550 case UNICHROME_CN750:
1551 case UNICHROME_K8M890:
1552 case UNICHROME_P4M890:
1553 case UNICHROME_P4M900:
1554 case UNICHROME_VX800:
1555 value = k800_encode_pll(pll_value[i].cx700_pll);
1558 case UNICHROME_VX855:
1559 value = vx855_encode_pll(pll_value[i].vx855_pll);
1568 void viafb_set_vclock(u32 clk, int set_iga)
1570 /* H.W. Reset : ON */
1571 viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
1573 if (set_iga == IGA1) {
1574 /* Change D,N FOR VCLK */
1575 switch (viaparinfo->chip_info->gfx_chip_name) {
1576 case UNICHROME_CLE266:
1577 case UNICHROME_K400:
1578 via_write_reg(VIASR, SR46, (clk & 0x00FF));
1579 via_write_reg(VIASR, SR47, (clk & 0xFF00) >> 8);
1582 case UNICHROME_K800:
1583 case UNICHROME_PM800:
1584 case UNICHROME_CN700:
1585 case UNICHROME_CX700:
1586 case UNICHROME_CN750:
1587 case UNICHROME_K8M890:
1588 case UNICHROME_P4M890:
1589 case UNICHROME_P4M900:
1590 case UNICHROME_VX800:
1591 case UNICHROME_VX855:
1592 via_write_reg(VIASR, SR44, (clk & 0x0000FF));
1593 via_write_reg(VIASR, SR45, (clk & 0x00FF00) >> 8);
1594 via_write_reg(VIASR, SR46, (clk & 0xFF0000) >> 16);
1599 if (set_iga == IGA2) {
1600 /* Change D,N FOR LCK */
1601 switch (viaparinfo->chip_info->gfx_chip_name) {
1602 case UNICHROME_CLE266:
1603 case UNICHROME_K400:
1604 via_write_reg(VIASR, SR44, (clk & 0x00FF));
1605 via_write_reg(VIASR, SR45, (clk & 0xFF00) >> 8);
1608 case UNICHROME_K800:
1609 case UNICHROME_PM800:
1610 case UNICHROME_CN700:
1611 case UNICHROME_CX700:
1612 case UNICHROME_CN750:
1613 case UNICHROME_K8M890:
1614 case UNICHROME_P4M890:
1615 case UNICHROME_P4M900:
1616 case UNICHROME_VX800:
1617 case UNICHROME_VX855:
1618 via_write_reg(VIASR, SR4A, (clk & 0x0000FF));
1619 via_write_reg(VIASR, SR4B, (clk & 0x00FF00) >> 8);
1620 via_write_reg(VIASR, SR4C, (clk & 0xFF0000) >> 16);
1625 /* H.W. Reset : OFF */
1626 viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
1629 if (set_iga == IGA1) {
1630 viafb_write_reg_mask(SR40, VIASR, 0x02, BIT1);
1631 viafb_write_reg_mask(SR40, VIASR, 0x00, BIT1);
1634 if (set_iga == IGA2) {
1635 viafb_write_reg_mask(SR40, VIASR, 0x04, BIT2);
1636 viafb_write_reg_mask(SR40, VIASR, 0x00, BIT2);
1640 via_write_misc_reg_mask(0x0C, 0x0C); /* select external clock */
1643 void viafb_load_crtc_timing(struct display_timing device_timing,
1647 int viafb_load_reg_num = 0;
1649 struct io_register *reg = NULL;
1653 for (i = 0; i < 12; i++) {
1654 if (set_iga == IGA1) {
1658 IGA1_HOR_TOTAL_FORMULA(device_timing.
1660 viafb_load_reg_num =
1661 iga1_crtc_reg.hor_total.reg_num;
1662 reg = iga1_crtc_reg.hor_total.reg;
1666 IGA1_HOR_ADDR_FORMULA(device_timing.
1668 viafb_load_reg_num =
1669 iga1_crtc_reg.hor_addr.reg_num;
1670 reg = iga1_crtc_reg.hor_addr.reg;
1672 case H_BLANK_START_INDEX:
1674 IGA1_HOR_BLANK_START_FORMULA
1675 (device_timing.hor_blank_start);
1676 viafb_load_reg_num =
1677 iga1_crtc_reg.hor_blank_start.reg_num;
1678 reg = iga1_crtc_reg.hor_blank_start.reg;
1680 case H_BLANK_END_INDEX:
1682 IGA1_HOR_BLANK_END_FORMULA
1683 (device_timing.hor_blank_start,
1684 device_timing.hor_blank_end);
1685 viafb_load_reg_num =
1686 iga1_crtc_reg.hor_blank_end.reg_num;
1687 reg = iga1_crtc_reg.hor_blank_end.reg;
1689 case H_SYNC_START_INDEX:
1691 IGA1_HOR_SYNC_START_FORMULA
1692 (device_timing.hor_sync_start);
1693 viafb_load_reg_num =
1694 iga1_crtc_reg.hor_sync_start.reg_num;
1695 reg = iga1_crtc_reg.hor_sync_start.reg;
1697 case H_SYNC_END_INDEX:
1699 IGA1_HOR_SYNC_END_FORMULA
1700 (device_timing.hor_sync_start,
1701 device_timing.hor_sync_end);
1702 viafb_load_reg_num =
1703 iga1_crtc_reg.hor_sync_end.reg_num;
1704 reg = iga1_crtc_reg.hor_sync_end.reg;
1708 IGA1_VER_TOTAL_FORMULA(device_timing.
1710 viafb_load_reg_num =
1711 iga1_crtc_reg.ver_total.reg_num;
1712 reg = iga1_crtc_reg.ver_total.reg;
1716 IGA1_VER_ADDR_FORMULA(device_timing.
1718 viafb_load_reg_num =
1719 iga1_crtc_reg.ver_addr.reg_num;
1720 reg = iga1_crtc_reg.ver_addr.reg;
1722 case V_BLANK_START_INDEX:
1724 IGA1_VER_BLANK_START_FORMULA
1725 (device_timing.ver_blank_start);
1726 viafb_load_reg_num =
1727 iga1_crtc_reg.ver_blank_start.reg_num;
1728 reg = iga1_crtc_reg.ver_blank_start.reg;
1730 case V_BLANK_END_INDEX:
1732 IGA1_VER_BLANK_END_FORMULA
1733 (device_timing.ver_blank_start,
1734 device_timing.ver_blank_end);
1735 viafb_load_reg_num =
1736 iga1_crtc_reg.ver_blank_end.reg_num;
1737 reg = iga1_crtc_reg.ver_blank_end.reg;
1739 case V_SYNC_START_INDEX:
1741 IGA1_VER_SYNC_START_FORMULA
1742 (device_timing.ver_sync_start);
1743 viafb_load_reg_num =
1744 iga1_crtc_reg.ver_sync_start.reg_num;
1745 reg = iga1_crtc_reg.ver_sync_start.reg;
1747 case V_SYNC_END_INDEX:
1749 IGA1_VER_SYNC_END_FORMULA
1750 (device_timing.ver_sync_start,
1751 device_timing.ver_sync_end);
1752 viafb_load_reg_num =
1753 iga1_crtc_reg.ver_sync_end.reg_num;
1754 reg = iga1_crtc_reg.ver_sync_end.reg;
1760 if (set_iga == IGA2) {
1764 IGA2_HOR_TOTAL_FORMULA(device_timing.
1766 viafb_load_reg_num =
1767 iga2_crtc_reg.hor_total.reg_num;
1768 reg = iga2_crtc_reg.hor_total.reg;
1772 IGA2_HOR_ADDR_FORMULA(device_timing.
1774 viafb_load_reg_num =
1775 iga2_crtc_reg.hor_addr.reg_num;
1776 reg = iga2_crtc_reg.hor_addr.reg;
1778 case H_BLANK_START_INDEX:
1780 IGA2_HOR_BLANK_START_FORMULA
1781 (device_timing.hor_blank_start);
1782 viafb_load_reg_num =
1783 iga2_crtc_reg.hor_blank_start.reg_num;
1784 reg = iga2_crtc_reg.hor_blank_start.reg;
1786 case H_BLANK_END_INDEX:
1788 IGA2_HOR_BLANK_END_FORMULA
1789 (device_timing.hor_blank_start,
1790 device_timing.hor_blank_end);
1791 viafb_load_reg_num =
1792 iga2_crtc_reg.hor_blank_end.reg_num;
1793 reg = iga2_crtc_reg.hor_blank_end.reg;
1795 case H_SYNC_START_INDEX:
1797 IGA2_HOR_SYNC_START_FORMULA
1798 (device_timing.hor_sync_start);
1799 if (UNICHROME_CN700 <=
1800 viaparinfo->chip_info->gfx_chip_name)
1801 viafb_load_reg_num =
1802 iga2_crtc_reg.hor_sync_start.
1805 viafb_load_reg_num = 3;
1806 reg = iga2_crtc_reg.hor_sync_start.reg;
1808 case H_SYNC_END_INDEX:
1810 IGA2_HOR_SYNC_END_FORMULA
1811 (device_timing.hor_sync_start,
1812 device_timing.hor_sync_end);
1813 viafb_load_reg_num =
1814 iga2_crtc_reg.hor_sync_end.reg_num;
1815 reg = iga2_crtc_reg.hor_sync_end.reg;
1819 IGA2_VER_TOTAL_FORMULA(device_timing.
1821 viafb_load_reg_num =
1822 iga2_crtc_reg.ver_total.reg_num;
1823 reg = iga2_crtc_reg.ver_total.reg;
1827 IGA2_VER_ADDR_FORMULA(device_timing.
1829 viafb_load_reg_num =
1830 iga2_crtc_reg.ver_addr.reg_num;
1831 reg = iga2_crtc_reg.ver_addr.reg;
1833 case V_BLANK_START_INDEX:
1835 IGA2_VER_BLANK_START_FORMULA
1836 (device_timing.ver_blank_start);
1837 viafb_load_reg_num =
1838 iga2_crtc_reg.ver_blank_start.reg_num;
1839 reg = iga2_crtc_reg.ver_blank_start.reg;
1841 case V_BLANK_END_INDEX:
1843 IGA2_VER_BLANK_END_FORMULA
1844 (device_timing.ver_blank_start,
1845 device_timing.ver_blank_end);
1846 viafb_load_reg_num =
1847 iga2_crtc_reg.ver_blank_end.reg_num;
1848 reg = iga2_crtc_reg.ver_blank_end.reg;
1850 case V_SYNC_START_INDEX:
1852 IGA2_VER_SYNC_START_FORMULA
1853 (device_timing.ver_sync_start);
1854 viafb_load_reg_num =
1855 iga2_crtc_reg.ver_sync_start.reg_num;
1856 reg = iga2_crtc_reg.ver_sync_start.reg;
1858 case V_SYNC_END_INDEX:
1860 IGA2_VER_SYNC_END_FORMULA
1861 (device_timing.ver_sync_start,
1862 device_timing.ver_sync_end);
1863 viafb_load_reg_num =
1864 iga2_crtc_reg.ver_sync_end.reg_num;
1865 reg = iga2_crtc_reg.ver_sync_end.reg;
1870 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1876 void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
1877 struct VideoModeTable *video_mode, int bpp_byte, int set_iga)
1879 struct display_timing crt_reg;
1886 for (i = 0; i < video_mode->mode_array; i++) {
1889 if (crt_table[i].refresh_rate == viaparinfo->
1890 crt_setting_info->refresh_rate)
1894 crt_reg = crt_table[index].crtc;
1896 /* Mode 640x480 has border, but LCD/DFP didn't have border. */
1897 /* So we would delete border. */
1898 if ((viafb_LCD_ON | viafb_DVI_ON)
1899 && video_mode->crtc[0].crtc.hor_addr == 640
1900 && video_mode->crtc[0].crtc.ver_addr == 480
1901 && viaparinfo->crt_setting_info->refresh_rate == 60) {
1902 /* The border is 8 pixels. */
1903 crt_reg.hor_blank_start = crt_reg.hor_blank_start - 8;
1905 /* Blanking time should add left and right borders. */
1906 crt_reg.hor_blank_end = crt_reg.hor_blank_end + 16;
1909 h_addr = crt_reg.hor_addr;
1910 v_addr = crt_reg.ver_addr;
1912 /* update polarity for CRT timing */
1913 if (crt_table[index].h_sync_polarity == NEGATIVE)
1915 if (crt_table[index].v_sync_polarity == NEGATIVE)
1917 via_write_misc_reg_mask(polarity, BIT6 | BIT7);
1919 if (set_iga == IGA1) {
1921 viafb_write_reg(CR09, VIACR, 0x00); /*initial CR09=0 */
1922 viafb_write_reg_mask(CR11, VIACR, 0x00, BIT4 + BIT5 + BIT6);
1923 viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
1928 viafb_load_crtc_timing(crt_reg, IGA1);
1931 viafb_load_crtc_timing(crt_reg, IGA2);
1935 load_fix_bit_crtc_reg();
1937 viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
1938 viafb_load_fetch_count_reg(h_addr, bpp_byte, set_iga);
1941 if ((viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266)
1942 && (viaparinfo->chip_info->gfx_chip_name != UNICHROME_K400))
1943 viafb_load_FIFO_reg(set_iga, h_addr, v_addr);
1945 pll_D_N = viafb_get_clk_value(crt_table[index].clk);
1946 DEBUG_MSG(KERN_INFO "PLL=%x", pll_D_N);
1947 viafb_set_vclock(pll_D_N, set_iga);
1951 void __devinit viafb_init_chip_info(int chip_type)
1953 init_gfx_chip_info(chip_type);
1954 init_tmds_chip_info();
1955 init_lvds_chip_info();
1957 viaparinfo->crt_setting_info->iga_path = IGA1;
1958 viaparinfo->crt_setting_info->refresh_rate = viafb_refresh;
1960 /*Set IGA path for each device */
1961 viafb_set_iga_path();
1963 viaparinfo->lvds_setting_info->display_method = viafb_lcd_dsp_method;
1964 viaparinfo->lvds_setting_info->lcd_mode = viafb_lcd_mode;
1965 viaparinfo->lvds_setting_info2->display_method =
1966 viaparinfo->lvds_setting_info->display_method;
1967 viaparinfo->lvds_setting_info2->lcd_mode =
1968 viaparinfo->lvds_setting_info->lcd_mode;
1971 void viafb_update_device_setting(int hres, int vres,
1972 int bpp, int vmode_refresh, int flag)
1975 viaparinfo->crt_setting_info->h_active = hres;
1976 viaparinfo->crt_setting_info->v_active = vres;
1977 viaparinfo->crt_setting_info->bpp = bpp;
1978 viaparinfo->crt_setting_info->refresh_rate =
1981 viaparinfo->tmds_setting_info->h_active = hres;
1982 viaparinfo->tmds_setting_info->v_active = vres;
1984 viaparinfo->lvds_setting_info->h_active = hres;
1985 viaparinfo->lvds_setting_info->v_active = vres;
1986 viaparinfo->lvds_setting_info->bpp = bpp;
1987 viaparinfo->lvds_setting_info->refresh_rate =
1989 viaparinfo->lvds_setting_info2->h_active = hres;
1990 viaparinfo->lvds_setting_info2->v_active = vres;
1991 viaparinfo->lvds_setting_info2->bpp = bpp;
1992 viaparinfo->lvds_setting_info2->refresh_rate =
1996 if (viaparinfo->tmds_setting_info->iga_path == IGA2) {
1997 viaparinfo->tmds_setting_info->h_active = hres;
1998 viaparinfo->tmds_setting_info->v_active = vres;
2001 if (viaparinfo->lvds_setting_info->iga_path == IGA2) {
2002 viaparinfo->lvds_setting_info->h_active = hres;
2003 viaparinfo->lvds_setting_info->v_active = vres;
2004 viaparinfo->lvds_setting_info->bpp = bpp;
2005 viaparinfo->lvds_setting_info->refresh_rate =
2008 if (IGA2 == viaparinfo->lvds_setting_info2->iga_path) {
2009 viaparinfo->lvds_setting_info2->h_active = hres;
2010 viaparinfo->lvds_setting_info2->v_active = vres;
2011 viaparinfo->lvds_setting_info2->bpp = bpp;
2012 viaparinfo->lvds_setting_info2->refresh_rate =
2018 static void __devinit init_gfx_chip_info(int chip_type)
2022 viaparinfo->chip_info->gfx_chip_name = chip_type;
2024 /* Check revision of CLE266 Chip */
2025 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
2026 /* CR4F only define in CLE266.CX chip */
2027 tmp = viafb_read_reg(VIACR, CR4F);
2028 viafb_write_reg(CR4F, VIACR, 0x55);
2029 if (viafb_read_reg(VIACR, CR4F) != 0x55)
2030 viaparinfo->chip_info->gfx_chip_revision =
2033 viaparinfo->chip_info->gfx_chip_revision =
2035 /* restore orignal CR4F value */
2036 viafb_write_reg(CR4F, VIACR, tmp);
2039 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
2040 tmp = viafb_read_reg(VIASR, SR43);
2041 DEBUG_MSG(KERN_INFO "SR43:%X\n", tmp);
2043 viaparinfo->chip_info->gfx_chip_revision =
2044 CX700_REVISION_700M2;
2045 } else if (tmp & 0x40) {
2046 viaparinfo->chip_info->gfx_chip_revision =
2047 CX700_REVISION_700M;
2049 viaparinfo->chip_info->gfx_chip_revision =
2054 /* Determine which 2D engine we have */
2055 switch (viaparinfo->chip_info->gfx_chip_name) {
2056 case UNICHROME_VX800:
2057 case UNICHROME_VX855:
2058 viaparinfo->chip_info->twod_engine = VIA_2D_ENG_M1;
2060 case UNICHROME_K8M890:
2061 case UNICHROME_P4M900:
2062 viaparinfo->chip_info->twod_engine = VIA_2D_ENG_H5;
2065 viaparinfo->chip_info->twod_engine = VIA_2D_ENG_H2;
2070 static void __devinit init_tmds_chip_info(void)
2072 viafb_tmds_trasmitter_identify();
2074 if (INTERFACE_NONE == viaparinfo->chip_info->tmds_chip_info.
2076 switch (viaparinfo->chip_info->gfx_chip_name) {
2077 case UNICHROME_CX700:
2079 /* we should check support by hardware layout.*/
2080 if ((viafb_display_hardware_layout ==
2082 || (viafb_display_hardware_layout ==
2083 HW_LAYOUT_LCD_DVI)) {
2084 viaparinfo->chip_info->tmds_chip_info.
2085 output_interface = INTERFACE_TMDS;
2087 viaparinfo->chip_info->tmds_chip_info.
2093 case UNICHROME_K8M890:
2094 case UNICHROME_P4M900:
2095 case UNICHROME_P4M890:
2096 /* TMDS on PCIE, we set DFPLOW as default. */
2097 viaparinfo->chip_info->tmds_chip_info.output_interface =
2102 /* set DVP1 default for DVI */
2103 viaparinfo->chip_info->tmds_chip_info
2104 .output_interface = INTERFACE_DVP1;
2109 DEBUG_MSG(KERN_INFO "TMDS Chip = %d\n",
2110 viaparinfo->chip_info->tmds_chip_info.tmds_chip_name);
2111 viafb_init_dvi_size(&viaparinfo->shared->chip_info.tmds_chip_info,
2112 &viaparinfo->shared->tmds_setting_info);
2115 static void __devinit init_lvds_chip_info(void)
2117 viafb_lvds_trasmitter_identify();
2118 viafb_init_lcd_size();
2119 viafb_init_lvds_output_interface(&viaparinfo->chip_info->lvds_chip_info,
2120 viaparinfo->lvds_setting_info);
2121 if (viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name) {
2122 viafb_init_lvds_output_interface(&viaparinfo->chip_info->
2123 lvds_chip_info2, viaparinfo->lvds_setting_info2);
2125 /*If CX700,two singel LCD, we need to reassign
2126 LCD interface to different LVDS port */
2127 if ((UNICHROME_CX700 == viaparinfo->chip_info->gfx_chip_name)
2128 && (HW_LAYOUT_LCD1_LCD2 == viafb_display_hardware_layout)) {
2129 if ((INTEGRATED_LVDS == viaparinfo->chip_info->lvds_chip_info.
2130 lvds_chip_name) && (INTEGRATED_LVDS ==
2131 viaparinfo->chip_info->
2132 lvds_chip_info2.lvds_chip_name)) {
2133 viaparinfo->chip_info->lvds_chip_info.output_interface =
2135 viaparinfo->chip_info->lvds_chip_info2.
2141 DEBUG_MSG(KERN_INFO "LVDS Chip = %d\n",
2142 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name);
2143 DEBUG_MSG(KERN_INFO "LVDS1 output_interface = %d\n",
2144 viaparinfo->chip_info->lvds_chip_info.output_interface);
2145 DEBUG_MSG(KERN_INFO "LVDS2 output_interface = %d\n",
2146 viaparinfo->chip_info->lvds_chip_info.output_interface);
2149 void __devinit viafb_init_dac(int set_iga)
2154 if (set_iga == IGA1) {
2155 /* access Primary Display's LUT */
2156 viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0);
2158 viafb_write_reg_mask(SR1B, VIASR, 0x00, BIT7 + BIT6);
2159 for (i = 0; i < 256; i++) {
2160 write_dac_reg(i, palLUT_table[i].red,
2161 palLUT_table[i].green,
2162 palLUT_table[i].blue);
2165 viafb_write_reg_mask(SR1B, VIASR, 0xC0, BIT7 + BIT6);
2167 tmp = viafb_read_reg(VIACR, CR6A);
2168 /* access Secondary Display's LUT */
2169 viafb_write_reg_mask(CR6A, VIACR, 0x40, BIT6);
2170 viafb_write_reg_mask(SR1A, VIASR, 0x01, BIT0);
2171 for (i = 0; i < 256; i++) {
2172 write_dac_reg(i, palLUT_table[i].red,
2173 palLUT_table[i].green,
2174 palLUT_table[i].blue);
2176 /* set IGA1 DAC for default */
2177 viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0);
2178 viafb_write_reg(CR6A, VIACR, tmp);
2182 static void device_screen_off(void)
2184 /* turn off CRT screen (IGA1) */
2185 viafb_write_reg_mask(SR01, VIASR, 0x20, BIT5);
2188 static void device_screen_on(void)
2190 /* turn on CRT screen (IGA1) */
2191 viafb_write_reg_mask(SR01, VIASR, 0x00, BIT5);
2194 static void set_display_channel(void)
2196 /*If viafb_LCD2_ON, on cx700, internal lvds's information
2197 is keeped on lvds_setting_info2 */
2198 if (viafb_LCD2_ON &&
2199 viaparinfo->lvds_setting_info2->device_lcd_dualedge) {
2200 /* For dual channel LCD: */
2201 /* Set to Dual LVDS channel. */
2202 viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);
2203 } else if (viafb_LCD_ON && viafb_DVI_ON) {
2205 /* Set to LVDS1 + TMDS channel. */
2206 viafb_write_reg_mask(CRD2, VIACR, 0x10, BIT4 + BIT5);
2207 } else if (viafb_DVI_ON) {
2208 /* Set to single TMDS channel. */
2209 viafb_write_reg_mask(CRD2, VIACR, 0x30, BIT4 + BIT5);
2210 } else if (viafb_LCD_ON) {
2211 if (viaparinfo->lvds_setting_info->device_lcd_dualedge) {
2212 /* For dual channel LCD: */
2213 /* Set to Dual LVDS channel. */
2214 viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);
2216 /* Set to LVDS0 + LVDS1 channel. */
2217 viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT4 + BIT5);
2222 int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp,
2223 struct VideoModeTable *vmode_tbl1, int video_bpp1)
2227 u8 value, index, mask;
2228 struct crt_mode_table *crt_timing;
2229 struct crt_mode_table *crt_timing1 = NULL;
2231 device_screen_off();
2232 crt_timing = vmode_tbl->crtc;
2234 if (viafb_SAMM_ON == 1) {
2235 crt_timing1 = vmode_tbl1->crtc;
2241 /* Write Common Setting for Video Mode */
2242 switch (viaparinfo->chip_info->gfx_chip_name) {
2243 case UNICHROME_CLE266:
2244 viafb_write_regx(CLE266_ModeXregs, NUM_TOTAL_CLE266_ModeXregs);
2247 case UNICHROME_K400:
2248 viafb_write_regx(KM400_ModeXregs, NUM_TOTAL_KM400_ModeXregs);
2251 case UNICHROME_K800:
2252 case UNICHROME_PM800:
2253 viafb_write_regx(CN400_ModeXregs, NUM_TOTAL_CN400_ModeXregs);
2256 case UNICHROME_CN700:
2257 case UNICHROME_K8M890:
2258 case UNICHROME_P4M890:
2259 case UNICHROME_P4M900:
2260 viafb_write_regx(CN700_ModeXregs, NUM_TOTAL_CN700_ModeXregs);
2263 case UNICHROME_CX700:
2264 case UNICHROME_VX800:
2265 viafb_write_regx(CX700_ModeXregs, NUM_TOTAL_CX700_ModeXregs);
2268 case UNICHROME_VX855:
2269 viafb_write_regx(VX855_ModeXregs, NUM_TOTAL_VX855_ModeXregs);
2275 /* Fill VPIT Parameters */
2276 /* Write Misc Register */
2277 outb(VPIT.Misc, VIA_MISC_REG_WRITE);
2279 /* Write Sequencer */
2280 for (i = 1; i <= StdSR; i++)
2281 via_write_reg(VIASR, i, VPIT.SR[i - 1]);
2283 viafb_write_reg_mask(0x15, VIASR, 0xA2, 0xA2);
2286 viafb_fill_crtc_timing(crt_timing, vmode_tbl, video_bpp / 8, IGA1);
2288 /* Write Graphic Controller */
2289 for (i = 0; i < StdGR; i++)
2290 via_write_reg(VIAGR, i, VPIT.GR[i]);
2292 /* Write Attribute Controller */
2293 for (i = 0; i < StdAR; i++) {
2296 outb(VPIT.AR[i], VIAAR);
2302 /* Update Patch Register */
2304 if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266
2305 || viaparinfo->chip_info->gfx_chip_name == UNICHROME_K400)
2306 && vmode_tbl->crtc[0].crtc.hor_addr == 1024
2307 && vmode_tbl->crtc[0].crtc.ver_addr == 768) {
2308 for (j = 0; j < res_patch_table[0].table_length; j++) {
2309 index = res_patch_table[0].io_reg_table[j].index;
2310 port = res_patch_table[0].io_reg_table[j].port;
2311 value = res_patch_table[0].io_reg_table[j].value;
2312 mask = res_patch_table[0].io_reg_table[j].mask;
2313 viafb_write_reg_mask(index, port, value, mask);
2317 via_set_primary_pitch(viafbinfo->fix.line_length);
2318 via_set_secondary_pitch(viafb_dual_fb ? viafbinfo1->fix.line_length
2319 : viafbinfo->fix.line_length);
2320 via_set_primary_color_depth(viaparinfo->depth);
2321 via_set_secondary_color_depth(viafb_dual_fb ? viaparinfo1->depth
2322 : viaparinfo->depth);
2323 via_set_source(viaparinfo->shared->iga1_devices, IGA1);
2324 via_set_source(viaparinfo->shared->iga2_devices, IGA2);
2325 if (viaparinfo->shared->iga2_devices)
2326 enable_second_display_channel();
2328 disable_second_display_channel();
2330 /* Update Refresh Rate Setting */
2332 /* Clear On Screen */
2336 if (viafb_SAMM_ON && (viaparinfo->crt_setting_info->iga_path ==
2338 viafb_fill_crtc_timing(crt_timing1, vmode_tbl1,
2340 viaparinfo->crt_setting_info->iga_path);
2342 viafb_fill_crtc_timing(crt_timing, vmode_tbl,
2344 viaparinfo->crt_setting_info->iga_path);
2347 /* Patch if set_hres is not 8 alignment (1366) to viafb_setmode
2348 to 8 alignment (1368),there is several pixels (2 pixels)
2349 on right side of screen. */
2350 if (vmode_tbl->crtc[0].crtc.hor_addr % 8) {
2352 viafb_write_reg(CR02, VIACR,
2353 viafb_read_reg(VIACR, CR02) - 1);
2359 if (viafb_SAMM_ON &&
2360 (viaparinfo->tmds_setting_info->iga_path == IGA2)) {
2361 viafb_dvi_set_mode(viafb_get_mode
2362 (viaparinfo->tmds_setting_info->h_active,
2363 viaparinfo->tmds_setting_info->
2365 video_bpp1, viaparinfo->
2366 tmds_setting_info->iga_path);
2368 viafb_dvi_set_mode(viafb_get_mode
2369 (viaparinfo->tmds_setting_info->h_active,
2371 tmds_setting_info->v_active),
2372 video_bpp, viaparinfo->
2373 tmds_setting_info->iga_path);
2378 if (viafb_SAMM_ON &&
2379 (viaparinfo->lvds_setting_info->iga_path == IGA2)) {
2380 viaparinfo->lvds_setting_info->bpp = video_bpp1;
2381 viafb_lcd_set_mode(crt_timing1, viaparinfo->
2383 &viaparinfo->chip_info->lvds_chip_info);
2385 /* IGA1 doesn't have LCD scaling, so set it center. */
2386 if (viaparinfo->lvds_setting_info->iga_path == IGA1) {
2387 viaparinfo->lvds_setting_info->display_method =
2390 viaparinfo->lvds_setting_info->bpp = video_bpp;
2391 viafb_lcd_set_mode(crt_timing, viaparinfo->
2393 &viaparinfo->chip_info->lvds_chip_info);
2396 if (viafb_LCD2_ON) {
2397 if (viafb_SAMM_ON &&
2398 (viaparinfo->lvds_setting_info2->iga_path == IGA2)) {
2399 viaparinfo->lvds_setting_info2->bpp = video_bpp1;
2400 viafb_lcd_set_mode(crt_timing1, viaparinfo->
2402 &viaparinfo->chip_info->lvds_chip_info2);
2404 /* IGA1 doesn't have LCD scaling, so set it center. */
2405 if (viaparinfo->lvds_setting_info2->iga_path == IGA1) {
2406 viaparinfo->lvds_setting_info2->display_method =
2409 viaparinfo->lvds_setting_info2->bpp = video_bpp;
2410 viafb_lcd_set_mode(crt_timing, viaparinfo->
2412 &viaparinfo->chip_info->lvds_chip_info2);
2416 if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700)
2417 && (viafb_LCD_ON || viafb_DVI_ON))
2418 set_display_channel();
2420 /* If set mode normally, save resolution information for hot-plug . */
2421 if (!viafb_hotplug) {
2422 viafb_hotplug_Xres = vmode_tbl->crtc[0].crtc.hor_addr;
2423 viafb_hotplug_Yres = vmode_tbl->crtc[0].crtc.ver_addr;
2424 viafb_hotplug_bpp = video_bpp;
2425 viafb_hotplug_refresh = viafb_refresh;
2428 viafb_DeviceStatus = DVI_Device;
2430 viafb_DeviceStatus = CRT_Device;
2437 int viafb_get_pixclock(int hres, int vres, int vmode_refresh)
2441 for (i = 0; i < NUM_TOTAL_RES_MAP_REFRESH; i++) {
2442 if ((hres == res_map_refresh_tbl[i].hres)
2443 && (vres == res_map_refresh_tbl[i].vres)
2444 && (vmode_refresh == res_map_refresh_tbl[i].vmode_refresh))
2445 return res_map_refresh_tbl[i].pixclock;
2447 return RES_640X480_60HZ_PIXCLOCK;
2451 int viafb_get_refresh(int hres, int vres, u32 long_refresh)
2453 #define REFRESH_TOLERANCE 3
2454 int i, nearest = -1, diff = REFRESH_TOLERANCE;
2455 for (i = 0; i < NUM_TOTAL_RES_MAP_REFRESH; i++) {
2456 if ((hres == res_map_refresh_tbl[i].hres)
2457 && (vres == res_map_refresh_tbl[i].vres)
2458 && (diff > (abs(long_refresh -
2459 res_map_refresh_tbl[i].vmode_refresh)))) {
2460 diff = abs(long_refresh - res_map_refresh_tbl[i].
2465 #undef REFRESH_TOLERANCE
2467 return res_map_refresh_tbl[nearest].vmode_refresh;
2471 static void device_off(void)
2473 viafb_crt_disable();
2474 viafb_dvi_disable();
2475 viafb_lcd_disable();
2478 static void device_on(void)
2480 if (viafb_CRT_ON == 1)
2482 if (viafb_DVI_ON == 1)
2484 if (viafb_LCD_ON == 1)
2488 void viafb_crt_disable(void)
2490 viafb_write_reg_mask(CR36, VIACR, BIT5 + BIT4, BIT5 + BIT4);
2493 void viafb_crt_enable(void)
2495 viafb_write_reg_mask(CR36, VIACR, 0x0, BIT5 + BIT4);
2498 static void enable_second_display_channel(void)
2500 /* to enable second display channel. */
2501 viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6);
2502 viafb_write_reg_mask(CR6A, VIACR, BIT7, BIT7);
2503 viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6);
2506 static void disable_second_display_channel(void)
2508 /* to disable second display channel. */
2509 viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6);
2510 viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT7);
2511 viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6);
2514 void viafb_set_dpa_gfx(int output_interface, struct GFX_DPA_SETTING\
2517 switch (output_interface) {
2518 case INTERFACE_DVP0:
2520 /* DVP0 Clock Polarity and Adjust: */
2521 viafb_write_reg_mask(CR96, VIACR,
2522 p_gfx_dpa_setting->DVP0, 0x0F);
2524 /* DVP0 Clock and Data Pads Driving: */
2525 viafb_write_reg_mask(SR1E, VIASR,
2526 p_gfx_dpa_setting->DVP0ClockDri_S, BIT2);
2527 viafb_write_reg_mask(SR2A, VIASR,
2528 p_gfx_dpa_setting->DVP0ClockDri_S1,
2530 viafb_write_reg_mask(SR1B, VIASR,
2531 p_gfx_dpa_setting->DVP0DataDri_S, BIT1);
2532 viafb_write_reg_mask(SR2A, VIASR,
2533 p_gfx_dpa_setting->DVP0DataDri_S1, BIT5);
2537 case INTERFACE_DVP1:
2539 /* DVP1 Clock Polarity and Adjust: */
2540 viafb_write_reg_mask(CR9B, VIACR,
2541 p_gfx_dpa_setting->DVP1, 0x0F);
2543 /* DVP1 Clock and Data Pads Driving: */
2544 viafb_write_reg_mask(SR65, VIASR,
2545 p_gfx_dpa_setting->DVP1Driving, 0x0F);
2549 case INTERFACE_DFP_HIGH:
2551 viafb_write_reg_mask(CR97, VIACR,
2552 p_gfx_dpa_setting->DFPHigh, 0x0F);
2556 case INTERFACE_DFP_LOW:
2558 viafb_write_reg_mask(CR99, VIACR,
2559 p_gfx_dpa_setting->DFPLow, 0x0F);
2565 viafb_write_reg_mask(CR97, VIACR,
2566 p_gfx_dpa_setting->DFPHigh, 0x0F);
2567 viafb_write_reg_mask(CR99, VIACR,
2568 p_gfx_dpa_setting->DFPLow, 0x0F);
2574 /*According var's xres, yres fill var's other timing information*/
2575 void viafb_fill_var_timing_info(struct fb_var_screeninfo *var, int refresh,
2576 struct VideoModeTable *vmode_tbl)
2578 struct crt_mode_table *crt_timing = NULL;
2579 struct display_timing crt_reg;
2580 int i = 0, index = 0;
2581 crt_timing = vmode_tbl->crtc;
2582 for (i = 0; i < vmode_tbl->mode_array; i++) {
2584 if (crt_timing[i].refresh_rate == refresh)
2588 crt_reg = crt_timing[index].crtc;
2589 var->pixclock = viafb_get_pixclock(var->xres, var->yres, refresh);
2591 crt_reg.hor_total - (crt_reg.hor_sync_start + crt_reg.hor_sync_end);
2592 var->right_margin = crt_reg.hor_sync_start - crt_reg.hor_addr;
2593 var->hsync_len = crt_reg.hor_sync_end;
2595 crt_reg.ver_total - (crt_reg.ver_sync_start + crt_reg.ver_sync_end);
2596 var->lower_margin = crt_reg.ver_sync_start - crt_reg.ver_addr;
2597 var->vsync_len = crt_reg.ver_sync_end;