drivers/video/via/hw.c

   1 /*
   2  * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
   3  * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
   4
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public
   7  * License as published by the Free Software Foundation;
   8  * either version 2, or (at your option) any later version.
   9
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
  12  * the implied warranty of MERCHANTABILITY or FITNESS FOR
  13  * A PARTICULAR PURPOSE.See the GNU General Public License
  14  * for more details.
  15
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc.,
  19  * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  20  */
  21
  22 #include <linux/via-core.h>
  23 #include "global.h"
  24
  25 static struct pll_map pll_value[] = {
  26         {25175000,
  27                 {99, 7, 3},
  28                 {85, 3, 4},     /* ignoring bit difference: 0x00008000 */
  29                 {141, 5, 4},
  30                 {141, 5, 4} },
  31         {29581000,
  32                 {33, 4, 2},
  33                 {66, 2, 4},     /* ignoring bit difference: 0x00808000 */
  34                 {166, 5, 4},    /* ignoring bit difference: 0x00008000 */
  35                 {165, 5, 4} },
  36         {26880000,
  37                 {15, 4, 1},
  38                 {30, 2, 3},     /* ignoring bit difference: 0x00808000 */
  39                 {150, 5, 4},
  40                 {150, 5, 4} },
  41         {31500000,
  42                 {53, 3, 3},     /* ignoring bit difference: 0x00008000 */
  43                 {141, 4, 4},    /* ignoring bit difference: 0x00008000 */
  44                 {176, 5, 4},
  45                 {176, 5, 4} },
  46         {31728000,
  47                 {31, 7, 1},
  48                 {177, 5, 4},    /* ignoring bit difference: 0x00008000 */
  49                 {177, 5, 4},
  50                 {142, 4, 4} },
  51         {32688000,
  52                 {73, 4, 3},
  53                 {146, 4, 4},    /* ignoring bit difference: 0x00008000 */
  54                 {183, 5, 4},
  55                 {146, 4, 4} },
  56         {36000000,
  57                 {101, 5, 3},    /* ignoring bit difference: 0x00008000 */
  58                 {161, 4, 4},    /* ignoring bit difference: 0x00008000 */
  59                 {202, 5, 4},
  60                 {161, 4, 4} },
  61         {40000000,
  62                 {89, 4, 3},
  63                 {89, 4, 3},     /* ignoring bit difference: 0x00008000 */
  64                 {112, 5, 3},
  65                 {112, 5, 3} },
  66         {41291000,
  67                 {23, 4, 1},
  68                 {69, 3, 3},     /* ignoring bit difference: 0x00008000 */
  69                 {115, 5, 3},
  70                 {115, 5, 3} },
  71         {43163000,
  72                 {121, 5, 3},
  73                 {121, 5, 3},    /* ignoring bit difference: 0x00008000 */
  74                 {121, 5, 3},
  75                 {121, 5, 3} },
  76         {45250000,
  77                 {127, 5, 3},
  78                 {127, 5, 3},    /* ignoring bit difference: 0x00808000 */
  79                 {127, 5, 3},
  80                 {127, 5, 3} },
  81         {46000000,
  82                 {90, 7, 2},
  83                 {103, 4, 3},    /* ignoring bit difference: 0x00008000 */
  84                 {129, 5, 3},
  85                 {103, 4, 3} },
  86         {46996000,
  87                 {105, 4, 3},    /* ignoring bit difference: 0x00008000 */
  88                 {131, 5, 3},    /* ignoring bit difference: 0x00808000 */
  89                 {131, 5, 3},    /* ignoring bit difference: 0x00808000 */
  90                 {105, 4, 3} },
  91         {48000000,
  92                 {67, 20, 0},
  93                 {134, 5, 3},    /* ignoring bit difference: 0x00808000 */
  94                 {134, 5, 3},
  95                 {134, 5, 3} },
  96         {48875000,
  97                 {99, 29, 0},
  98                 {82, 3, 3},     /* ignoring bit difference: 0x00808000 */
  99                 {82, 3, 3},     /* ignoring bit difference: 0x00808000 */
 100                 {137, 5, 3} },
 101         {49500000,
 102                 {83, 6, 2},
 103                 {83, 3, 3},     /* ignoring bit difference: 0x00008000 */
 104                 {138, 5, 3},
 105                 {83, 3, 3} },
 106         {52406000,
 107                 {117, 4, 3},
 108                 {117, 4, 3},    /* ignoring bit difference: 0x00008000 */
 109                 {117, 4, 3},
 110                 {88, 3, 3} },
 111         {52977000,
 112                 {37, 5, 1},
 113                 {148, 5, 3},    /* ignoring bit difference: 0x00808000 */
 114                 {148, 5, 3},
 115                 {148, 5, 3} },
 116         {56250000,
 117                 {55, 7, 1},     /* ignoring bit difference: 0x00008000 */
 118                 {126, 4, 3},    /* ignoring bit difference: 0x00008000 */
 119                 {157, 5, 3},
 120                 {157, 5, 3} },
 121         {57275000,
 122                 {0, 0, 0},
 123                 {2, 2, 0},
 124                 {2, 2, 0},
 125                 {157, 5, 3} },  /* ignoring bit difference: 0x00808000 */
 126         {60466000,
 127                 {76, 9, 1},
 128                 {169, 5, 3},    /* ignoring bit difference: 0x00808000 */
 129                 {169, 5, 3},    /* FIXED: old = {72, 2, 3} */
 130                 {169, 5, 3} },
 131         {61500000,
 132                 {86, 20, 0},
 133                 {172, 5, 3},    /* ignoring bit difference: 0x00808000 */
 134                 {172, 5, 3},
 135                 {172, 5, 3} },
 136         {65000000,
 137                 {109, 6, 2},    /* ignoring bit difference: 0x00008000 */
 138                 {109, 3, 3},    /* ignoring bit difference: 0x00008000 */
 139                 {109, 3, 3},
 140                 {109, 3, 3} },
 141         {65178000,
 142                 {91, 5, 2},
 143                 {182, 5, 3},    /* ignoring bit difference: 0x00808000 */
 144                 {109, 3, 3},
 145                 {182, 5, 3} },
 146         {66750000,
 147                 {75, 4, 2},
 148                 {150, 4, 3},    /* ignoring bit difference: 0x00808000 */
 149                 {150, 4, 3},
 150                 {112, 3, 3} },
 151         {68179000,
 152                 {19, 4, 0},
 153                 {114, 3, 3},    /* ignoring bit difference: 0x00008000 */
 154                 {190, 5, 3},
 155                 {191, 5, 3} },
 156         {69924000,
 157                 {83, 17, 0},
 158                 {195, 5, 3},    /* ignoring bit difference: 0x00808000 */
 159                 {195, 5, 3},
 160                 {195, 5, 3} },
 161         {70159000,
 162                 {98, 20, 0},
 163                 {196, 5, 3},    /* ignoring bit difference: 0x00808000 */
 164                 {196, 5, 3},
 165                 {195, 5, 3} },
 166         {72000000,
 167                 {121, 24, 0},
 168                 {161, 4, 3},    /* ignoring bit difference: 0x00808000 */
 169                 {161, 4, 3},
 170                 {161, 4, 3} },
 171         {78750000,
 172                 {33, 3, 1},
 173                 {66, 3, 2},     /* ignoring bit difference: 0x00008000 */
 174                 {110, 5, 2},
 175                 {110, 5, 2} },
 176         {80136000,
 177                 {28, 5, 0},
 178                 {68, 3, 2},     /* ignoring bit difference: 0x00008000 */
 179                 {112, 5, 2},
 180                 {112, 5, 2} },
 181         {83375000,
 182                 {93, 2, 3},
 183                 {93, 4, 2},     /* ignoring bit difference: 0x00800000 */
 184                 {93, 4, 2},     /* ignoring bit difference: 0x00800000 */
 185                 {117, 5, 2} },
 186         {83950000,
 187                 {41, 7, 0},
 188                 {117, 5, 2},    /* ignoring bit difference: 0x00008000 */
 189                 {117, 5, 2},
 190                 {117, 5, 2} },
 191         {84750000,
 192                 {118, 5, 2},
 193                 {118, 5, 2},    /* ignoring bit difference: 0x00808000 */
 194                 {118, 5, 2},
 195                 {118, 5, 2} },
 196         {85860000,
 197                 {84, 7, 1},
 198                 {120, 5, 2},    /* ignoring bit difference: 0x00808000 */
 199                 {120, 5, 2},
 200                 {118, 5, 2} },
 201         {88750000,
 202                 {31, 5, 0},
 203                 {124, 5, 2},    /* ignoring bit difference: 0x00808000 */
 204                 {174, 7, 2},    /* ignoring bit difference: 0x00808000 */
 205                 {124, 5, 2} },
 206         {94500000,
 207                 {33, 5, 0},
 208                 {132, 5, 2},    /* ignoring bit difference: 0x00008000 */
 209                 {132, 5, 2},
 210                 {132, 5, 2} },
 211         {97750000,
 212                 {82, 6, 1},
 213                 {137, 5, 2},    /* ignoring bit difference: 0x00808000 */
 214                 {137, 5, 2},
 215                 {137, 5, 2} },
 216         {101000000,
 217                 {127, 9, 1},
 218                 {141, 5, 2},    /* ignoring bit difference: 0x00808000 */
 219                 {141, 5, 2},
 220                 {141, 5, 2} },
 221         {106500000,
 222                 {119, 4, 2},
 223                 {119, 4, 2},    /* ignoring bit difference: 0x00808000 */
 224                 {119, 4, 2},
 225                 {149, 5, 2} },
 226         {108000000,
 227                 {121, 4, 2},
 228                 {121, 4, 2},    /* ignoring bit difference: 0x00808000 */
 229                 {151, 5, 2},
 230                 {151, 5, 2} },
 231         {113309000,
 232                 {95, 12, 0},
 233                 {95, 3, 2},     /* ignoring bit difference: 0x00808000 */
 234                 {95, 3, 2},
 235                 {159, 5, 2} },
 236         {118840000,
 237                 {83, 5, 1},
 238                 {166, 5, 2},    /* ignoring bit difference: 0x00808000 */
 239                 {166, 5, 2},
 240                 {166, 5, 2} },
 241         {119000000,
 242                 {108, 13, 0},
 243                 {133, 4, 2},    /* ignoring bit difference: 0x00808000 */
 244                 {133, 4, 2},
 245                 {167, 5, 2} },
 246         {121750000,
 247                 {85, 5, 1},
 248                 {170, 5, 2},    /* ignoring bit difference: 0x00808000 */
 249                 {68, 2, 2},
 250                 {0, 0, 0} },
 251         {125104000,
 252                 {53, 6, 0},     /* ignoring bit difference: 0x00008000 */
 253                 {106, 3, 2},    /* ignoring bit difference: 0x00008000 */
 254                 {175, 5, 2},
 255                 {0, 0, 0} },
 256         {135000000,
 257                 {94, 5, 1},
 258                 {28, 3, 0},     /* ignoring bit difference: 0x00804000 */
 259                 {151, 4, 2},
 260                 {189, 5, 2} },
 261         {136700000,
 262                 {115, 12, 0},
 263                 {191, 5, 2},    /* ignoring bit difference: 0x00808000 */
 264                 {191, 5, 2},
 265                 {191, 5, 2} },
 266         {138400000,
 267                 {87, 9, 0},
 268                 {116, 3, 2},    /* ignoring bit difference: 0x00808000 */
 269                 {116, 3, 2},
 270                 {194, 5, 2} },
 271         {146760000,
 272                 {103, 5, 1},
 273                 {206, 5, 2},    /* ignoring bit difference: 0x00808000 */
 274                 {206, 5, 2},
 275                 {206, 5, 2} },
 276         {153920000,
 277                 {86, 8, 0},
 278                 {86, 4, 1},     /* ignoring bit difference: 0x00808000 */
 279                 {86, 4, 1},
 280                 {86, 4, 1} },   /* FIXED: old = {84, 2, 1} */
 281         {156000000,
 282                 {109, 5, 1},
 283                 {109, 5, 1},    /* ignoring bit difference: 0x00808000 */
 284                 {109, 5, 1},
 285                 {108, 5, 1} },
 286         {157500000,
 287                 {55, 5, 0},     /* ignoring bit difference: 0x00008000 */
 288                 {22, 2, 0},     /* ignoring bit difference: 0x00802000 */
 289                 {110, 5, 1},
 290                 {110, 5, 1} },
 291         {162000000,
 292                 {113, 5, 1},
 293                 {113, 5, 1},    /* ignoring bit difference: 0x00808000 */
 294                 {113, 5, 1},
 295                 {113, 5, 1} },
 296         {187000000,
 297                 {118, 9, 0},
 298                 {131, 5, 1},    /* ignoring bit difference: 0x00808000 */
 299                 {131, 5, 1},
 300                 {131, 5, 1} },
 301         {193295000,
 302                 {108, 8, 0},
 303                 {81, 3, 1},     /* ignoring bit difference: 0x00808000 */
 304                 {135, 5, 1},
 305                 {135, 5, 1} },
 306         {202500000,
 307                 {99, 7, 0},
 308                 {85, 3, 1},     /* ignoring bit difference: 0x00808000 */
 309                 {142, 5, 1},
 310                 {142, 5, 1} },
 311         {204000000,
 312                 {100, 7, 0},
 313                 {143, 5, 1},    /* ignoring bit difference: 0x00808000 */
 314                 {143, 5, 1},
 315                 {143, 5, 1} },
 316         {218500000,
 317                 {92, 6, 0},
 318                 {153, 5, 1},    /* ignoring bit difference: 0x00808000 */
 319                 {153, 5, 1},
 320                 {153, 5, 1} },
 321         {234000000,
 322                 {98, 6, 0},
 323                 {98, 3, 1},     /* ignoring bit difference: 0x00008000 */
 324                 {98, 3, 1},
 325                 {164, 5, 1} },
 326         {267250000,
 327                 {112, 6, 0},
 328                 {112, 3, 1},    /* ignoring bit difference: 0x00808000 */
 329                 {187, 5, 1},
 330                 {187, 5, 1} },
 331         {297500000,
 332                 {102, 5, 0},    /* ignoring bit difference: 0x00008000 */
 333                 {166, 4, 1},    /* ignoring bit difference: 0x00008000 */
 334                 {208, 5, 1},
 335                 {208, 5, 1} },
 336         {74481000,
 337                 {26, 5, 0},
 338                 {125, 3, 3},    /* ignoring bit difference: 0x00808000 */
 339                 {208, 5, 3},
 340                 {209, 5, 3} },
 341         {172798000,
 342                 {121, 5, 1},
 343                 {121, 5, 1},    /* ignoring bit difference: 0x00808000 */
 344                 {121, 5, 1},
 345                 {121, 5, 1} },
 346         {122614000,
 347                 {60, 7, 0},
 348                 {137, 4, 2},    /* ignoring bit difference: 0x00808000 */
 349                 {137, 4, 2},
 350                 {172, 5, 2} },
 351         {74270000,
 352                 {83, 8, 1},
 353                 {208, 5, 3},
 354                 {208, 5, 3},
 355                 {0, 0, 0} },
 356         {148500000,
 357                 {83, 8, 0},
 358                 {208, 5, 2},
 359                 {166, 4, 2},
 360                 {208, 5, 2} }
 361 };
 362
 363 /* according to VIA Technologies these values are based on experiment */
 364 static struct io_reg scaling_parameters[] = {
 365         {VIACR, CR7A, 0xFF, 0x01},      /* LCD Scaling Parameter 1 */
 366         {VIACR, CR7B, 0xFF, 0x02},      /* LCD Scaling Parameter 2 */
 367         {VIACR, CR7C, 0xFF, 0x03},      /* LCD Scaling Parameter 3 */
 368         {VIACR, CR7D, 0xFF, 0x04},      /* LCD Scaling Parameter 4 */
 369         {VIACR, CR7E, 0xFF, 0x07},      /* LCD Scaling Parameter 5 */
 370         {VIACR, CR7F, 0xFF, 0x0A},      /* LCD Scaling Parameter 6 */
 371         {VIACR, CR80, 0xFF, 0x0D},      /* LCD Scaling Parameter 7 */
 372         {VIACR, CR81, 0xFF, 0x13},      /* LCD Scaling Parameter 8 */
 373         {VIACR, CR82, 0xFF, 0x16},      /* LCD Scaling Parameter 9 */
 374         {VIACR, CR83, 0xFF, 0x19},      /* LCD Scaling Parameter 10 */
 375         {VIACR, CR84, 0xFF, 0x1C},      /* LCD Scaling Parameter 11 */
 376         {VIACR, CR85, 0xFF, 0x1D},      /* LCD Scaling Parameter 12 */
 377         {VIACR, CR86, 0xFF, 0x1E},      /* LCD Scaling Parameter 13 */
 378         {VIACR, CR87, 0xFF, 0x1F},      /* LCD Scaling Parameter 14 */
 379 };
 380
 381 static struct fifo_depth_select display_fifo_depth_reg = {
 382         /* IGA1 FIFO Depth_Select */
 383         {IGA1_FIFO_DEPTH_SELECT_REG_NUM, {{SR17, 0, 7} } },
 384         /* IGA2 FIFO Depth_Select */
 385         {IGA2_FIFO_DEPTH_SELECT_REG_NUM,
 386          {{CR68, 4, 7}, {CR94, 7, 7}, {CR95, 7, 7} } }
 387 };
 388
 389 static struct fifo_threshold_select fifo_threshold_select_reg = {
 390         /* IGA1 FIFO Threshold Select */
 391         {IGA1_FIFO_THRESHOLD_REG_NUM, {{SR16, 0, 5}, {SR16, 7, 7} } },
 392         /* IGA2 FIFO Threshold Select */
 393         {IGA2_FIFO_THRESHOLD_REG_NUM, {{CR68, 0, 3}, {CR95, 4, 6} } }
 394 };
 395
 396 static struct fifo_high_threshold_select fifo_high_threshold_select_reg = {
 397         /* IGA1 FIFO High Threshold Select */
 398         {IGA1_FIFO_HIGH_THRESHOLD_REG_NUM, {{SR18, 0, 5}, {SR18, 7, 7} } },
 399         /* IGA2 FIFO High Threshold Select */
 400         {IGA2_FIFO_HIGH_THRESHOLD_REG_NUM, {{CR92, 0, 3}, {CR95, 0, 2} } }
 401 };
 402
 403 static struct display_queue_expire_num display_queue_expire_num_reg = {
 404         /* IGA1 Display Queue Expire Num */
 405         {IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{SR22, 0, 4} } },
 406         /* IGA2 Display Queue Expire Num */
 407         {IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{CR94, 0, 6} } }
 408 };
 409
 410 /* Definition Fetch Count Registers*/
 411 static struct fetch_count fetch_count_reg = {
 412         /* IGA1 Fetch Count Register */
 413         {IGA1_FETCH_COUNT_REG_NUM, {{SR1C, 0, 7}, {SR1D, 0, 1} } },
 414         /* IGA2 Fetch Count Register */
 415         {IGA2_FETCH_COUNT_REG_NUM, {{CR65, 0, 7}, {CR67, 2, 3} } }
 416 };
 417
 418 static struct iga1_crtc_timing iga1_crtc_reg = {
 419         /* IGA1 Horizontal Total */
 420         {IGA1_HOR_TOTAL_REG_NUM, {{CR00, 0, 7}, {CR36, 3, 3} } },
 421         /* IGA1 Horizontal Addressable Video */
 422         {IGA1_HOR_ADDR_REG_NUM, {{CR01, 0, 7} } },
 423         /* IGA1 Horizontal Blank Start */
 424         {IGA1_HOR_BLANK_START_REG_NUM, {{CR02, 0, 7} } },
 425         /* IGA1 Horizontal Blank End */
 426         {IGA1_HOR_BLANK_END_REG_NUM,
 427          {{CR03, 0, 4}, {CR05, 7, 7}, {CR33, 5, 5} } },
 428         /* IGA1 Horizontal Sync Start */
 429         {IGA1_HOR_SYNC_START_REG_NUM, {{CR04, 0, 7}, {CR33, 4, 4} } },
 430         /* IGA1 Horizontal Sync End */
 431         {IGA1_HOR_SYNC_END_REG_NUM, {{CR05, 0, 4} } },
 432         /* IGA1 Vertical Total */
 433         {IGA1_VER_TOTAL_REG_NUM,
 434          {{CR06, 0, 7}, {CR07, 0, 0}, {CR07, 5, 5}, {CR35, 0, 0} } },
 435         /* IGA1 Vertical Addressable Video */
 436         {IGA1_VER_ADDR_REG_NUM,
 437          {{CR12, 0, 7}, {CR07, 1, 1}, {CR07, 6, 6}, {CR35, 2, 2} } },
 438         /* IGA1 Vertical Blank Start */
 439         {IGA1_VER_BLANK_START_REG_NUM,
 440          {{CR15, 0, 7}, {CR07, 3, 3}, {CR09, 5, 5}, {CR35, 3, 3} } },
 441         /* IGA1 Vertical Blank End */
 442         {IGA1_VER_BLANK_END_REG_NUM, {{CR16, 0, 7} } },
 443         /* IGA1 Vertical Sync Start */
 444         {IGA1_VER_SYNC_START_REG_NUM,
 445          {{CR10, 0, 7}, {CR07, 2, 2}, {CR07, 7, 7}, {CR35, 1, 1} } },
 446         /* IGA1 Vertical Sync End */
 447         {IGA1_VER_SYNC_END_REG_NUM, {{CR11, 0, 3} } }
 448 };
 449
 450 static struct iga2_crtc_timing iga2_crtc_reg = {
 451         /* IGA2 Horizontal Total */
 452         {IGA2_HOR_TOTAL_REG_NUM, {{CR50, 0, 7}, {CR55, 0, 3} } },
 453         /* IGA2 Horizontal Addressable Video */
 454         {IGA2_HOR_ADDR_REG_NUM, {{CR51, 0, 7}, {CR55, 4, 6} } },
 455         /* IGA2 Horizontal Blank Start */
 456         {IGA2_HOR_BLANK_START_REG_NUM, {{CR52, 0, 7}, {CR54, 0, 2} } },
 457         /* IGA2 Horizontal Blank End */
 458         {IGA2_HOR_BLANK_END_REG_NUM,
 459          {{CR53, 0, 7}, {CR54, 3, 5}, {CR5D, 6, 6} } },
 460         /* IGA2 Horizontal Sync Start */
 461         {IGA2_HOR_SYNC_START_REG_NUM,
 462          {{CR56, 0, 7}, {CR54, 6, 7}, {CR5C, 7, 7}, {CR5D, 7, 7} } },
 463         /* IGA2 Horizontal Sync End */
 464         {IGA2_HOR_SYNC_END_REG_NUM, {{CR57, 0, 7}, {CR5C, 6, 6} } },
 465         /* IGA2 Vertical Total */
 466         {IGA2_VER_TOTAL_REG_NUM, {{CR58, 0, 7}, {CR5D, 0, 2} } },
 467         /* IGA2 Vertical Addressable Video */
 468         {IGA2_VER_ADDR_REG_NUM, {{CR59, 0, 7}, {CR5D, 3, 5} } },
 469         /* IGA2 Vertical Blank Start */
 470         {IGA2_VER_BLANK_START_REG_NUM, {{CR5A, 0, 7}, {CR5C, 0, 2} } },
 471         /* IGA2 Vertical Blank End */
 472         {IGA2_VER_BLANK_END_REG_NUM, {{CR5B, 0, 7}, {CR5C, 3, 5} } },
 473         /* IGA2 Vertical Sync Start */
 474         {IGA2_VER_SYNC_START_REG_NUM, {{CR5E, 0, 7}, {CR5F, 5, 7} } },
 475         /* IGA2 Vertical Sync End */
 476         {IGA2_VER_SYNC_END_REG_NUM, {{CR5F, 0, 4} } }
 477 };
 478
 479 static struct rgbLUT palLUT_table[] = {
 480         /* {R,G,B} */
 481         /* Index 0x00~0x03 */
 482         {0x00, 0x00, 0x00}, {0x00, 0x00, 0x2A}, {0x00, 0x2A, 0x00}, {0x00,
 483                                                                      0x2A,
 484                                                                      0x2A},
 485         /* Index 0x04~0x07 */
 486         {0x2A, 0x00, 0x00}, {0x2A, 0x00, 0x2A}, {0x2A, 0x15, 0x00}, {0x2A,
 487                                                                      0x2A,
 488                                                                      0x2A},
 489         /* Index 0x08~0x0B */
 490         {0x15, 0x15, 0x15}, {0x15, 0x15, 0x3F}, {0x15, 0x3F, 0x15}, {0x15,
 491                                                                      0x3F,
 492                                                                      0x3F},
 493         /* Index 0x0C~0x0F */
 494         {0x3F, 0x15, 0x15}, {0x3F, 0x15, 0x3F}, {0x3F, 0x3F, 0x15}, {0x3F,
 495                                                                      0x3F,
 496                                                                      0x3F},
 497         /* Index 0x10~0x13 */
 498         {0x00, 0x00, 0x00}, {0x05, 0x05, 0x05}, {0x08, 0x08, 0x08}, {0x0B,
 499                                                                      0x0B,
 500                                                                      0x0B},
 501         /* Index 0x14~0x17 */
 502         {0x0E, 0x0E, 0x0E}, {0x11, 0x11, 0x11}, {0x14, 0x14, 0x14}, {0x18,
 503                                                                      0x18,
 504                                                                      0x18},
 505         /* Index 0x18~0x1B */
 506         {0x1C, 0x1C, 0x1C}, {0x20, 0x20, 0x20}, {0x24, 0x24, 0x24}, {0x28,
 507                                                                      0x28,
 508                                                                      0x28},
 509         /* Index 0x1C~0x1F */
 510         {0x2D, 0x2D, 0x2D}, {0x32, 0x32, 0x32}, {0x38, 0x38, 0x38}, {0x3F,
 511                                                                      0x3F,
 512                                                                      0x3F},
 513         /* Index 0x20~0x23 */
 514         {0x00, 0x00, 0x3F}, {0x10, 0x00, 0x3F}, {0x1F, 0x00, 0x3F}, {0x2F,
 515                                                                      0x00,
 516                                                                      0x3F},
 517         /* Index 0x24~0x27 */
 518         {0x3F, 0x00, 0x3F}, {0x3F, 0x00, 0x2F}, {0x3F, 0x00, 0x1F}, {0x3F,
 519                                                                      0x00,
 520                                                                      0x10},
 521         /* Index 0x28~0x2B */
 522         {0x3F, 0x00, 0x00}, {0x3F, 0x10, 0x00}, {0x3F, 0x1F, 0x00}, {0x3F,
 523                                                                      0x2F,
 524                                                                      0x00},
 525         /* Index 0x2C~0x2F */
 526         {0x3F, 0x3F, 0x00}, {0x2F, 0x3F, 0x00}, {0x1F, 0x3F, 0x00}, {0x10,
 527                                                                      0x3F,
 528                                                                      0x00},
 529         /* Index 0x30~0x33 */
 530         {0x00, 0x3F, 0x00}, {0x00, 0x3F, 0x10}, {0x00, 0x3F, 0x1F}, {0x00,
 531                                                                      0x3F,
 532                                                                      0x2F},
 533         /* Index 0x34~0x37 */
 534         {0x00, 0x3F, 0x3F}, {0x00, 0x2F, 0x3F}, {0x00, 0x1F, 0x3F}, {0x00,
 535                                                                      0x10,
 536                                                                      0x3F},
 537         /* Index 0x38~0x3B */
 538         {0x1F, 0x1F, 0x3F}, {0x27, 0x1F, 0x3F}, {0x2F, 0x1F, 0x3F}, {0x37,
 539                                                                      0x1F,
 540                                                                      0x3F},
 541         /* Index 0x3C~0x3F */
 542         {0x3F, 0x1F, 0x3F}, {0x3F, 0x1F, 0x37}, {0x3F, 0x1F, 0x2F}, {0x3F,
 543                                                                      0x1F,
 544                                                                      0x27},
 545         /* Index 0x40~0x43 */
 546         {0x3F, 0x1F, 0x1F}, {0x3F, 0x27, 0x1F}, {0x3F, 0x2F, 0x1F}, {0x3F,
 547                                                                      0x3F,
 548                                                                      0x1F},
 549         /* Index 0x44~0x47 */
 550         {0x3F, 0x3F, 0x1F}, {0x37, 0x3F, 0x1F}, {0x2F, 0x3F, 0x1F}, {0x27,
 551                                                                      0x3F,
 552                                                                      0x1F},
 553         /* Index 0x48~0x4B */
 554         {0x1F, 0x3F, 0x1F}, {0x1F, 0x3F, 0x27}, {0x1F, 0x3F, 0x2F}, {0x1F,
 555                                                                      0x3F,
 556                                                                      0x37},
 557         /* Index 0x4C~0x4F */
 558         {0x1F, 0x3F, 0x3F}, {0x1F, 0x37, 0x3F}, {0x1F, 0x2F, 0x3F}, {0x1F,
 559                                                                      0x27,
 560                                                                      0x3F},
 561         /* Index 0x50~0x53 */
 562         {0x2D, 0x2D, 0x3F}, {0x31, 0x2D, 0x3F}, {0x36, 0x2D, 0x3F}, {0x3A,
 563                                                                      0x2D,
 564                                                                      0x3F},
 565         /* Index 0x54~0x57 */
 566         {0x3F, 0x2D, 0x3F}, {0x3F, 0x2D, 0x3A}, {0x3F, 0x2D, 0x36}, {0x3F,
 567                                                                      0x2D,
 568                                                                      0x31},
 569         /* Index 0x58~0x5B */
 570         {0x3F, 0x2D, 0x2D}, {0x3F, 0x31, 0x2D}, {0x3F, 0x36, 0x2D}, {0x3F,
 571                                                                      0x3A,
 572                                                                      0x2D},
 573         /* Index 0x5C~0x5F */
 574         {0x3F, 0x3F, 0x2D}, {0x3A, 0x3F, 0x2D}, {0x36, 0x3F, 0x2D}, {0x31,
 575                                                                      0x3F,
 576                                                                      0x2D},
 577         /* Index 0x60~0x63 */
 578         {0x2D, 0x3F, 0x2D}, {0x2D, 0x3F, 0x31}, {0x2D, 0x3F, 0x36}, {0x2D,
 579                                                                      0x3F,
 580                                                                      0x3A},
 581         /* Index 0x64~0x67 */
 582         {0x2D, 0x3F, 0x3F}, {0x2D, 0x3A, 0x3F}, {0x2D, 0x36, 0x3F}, {0x2D,
 583                                                                      0x31,
 584                                                                      0x3F},
 585         /* Index 0x68~0x6B */
 586         {0x00, 0x00, 0x1C}, {0x07, 0x00, 0x1C}, {0x0E, 0x00, 0x1C}, {0x15,
 587                                                                      0x00,
 588                                                                      0x1C},
 589         /* Index 0x6C~0x6F */
 590         {0x1C, 0x00, 0x1C}, {0x1C, 0x00, 0x15}, {0x1C, 0x00, 0x0E}, {0x1C,
 591                                                                      0x00,
 592                                                                      0x07},
 593         /* Index 0x70~0x73 */
 594         {0x1C, 0x00, 0x00}, {0x1C, 0x07, 0x00}, {0x1C, 0x0E, 0x00}, {0x1C,
 595                                                                      0x15,
 596                                                                      0x00},
 597         /* Index 0x74~0x77 */
 598         {0x1C, 0x1C, 0x00}, {0x15, 0x1C, 0x00}, {0x0E, 0x1C, 0x00}, {0x07,
 599                                                                      0x1C,
 600                                                                      0x00},
 601         /* Index 0x78~0x7B */
 602         {0x00, 0x1C, 0x00}, {0x00, 0x1C, 0x07}, {0x00, 0x1C, 0x0E}, {0x00,
 603                                                                      0x1C,
 604                                                                      0x15},
 605         /* Index 0x7C~0x7F */
 606         {0x00, 0x1C, 0x1C}, {0x00, 0x15, 0x1C}, {0x00, 0x0E, 0x1C}, {0x00,
 607                                                                      0x07,
 608                                                                      0x1C},
 609         /* Index 0x80~0x83 */
 610         {0x0E, 0x0E, 0x1C}, {0x11, 0x0E, 0x1C}, {0x15, 0x0E, 0x1C}, {0x18,
 611                                                                      0x0E,
 612                                                                      0x1C},
 613         /* Index 0x84~0x87 */
 614         {0x1C, 0x0E, 0x1C}, {0x1C, 0x0E, 0x18}, {0x1C, 0x0E, 0x15}, {0x1C,
 615                                                                      0x0E,
 616                                                                      0x11},
 617         /* Index 0x88~0x8B */
 618         {0x1C, 0x0E, 0x0E}, {0x1C, 0x11, 0x0E}, {0x1C, 0x15, 0x0E}, {0x1C,
 619                                                                      0x18,
 620                                                                      0x0E},
 621         /* Index 0x8C~0x8F */
 622         {0x1C, 0x1C, 0x0E}, {0x18, 0x1C, 0x0E}, {0x15, 0x1C, 0x0E}, {0x11,
 623                                                                      0x1C,
 624                                                                      0x0E},
 625         /* Index 0x90~0x93 */
 626         {0x0E, 0x1C, 0x0E}, {0x0E, 0x1C, 0x11}, {0x0E, 0x1C, 0x15}, {0x0E,
 627                                                                      0x1C,
 628                                                                      0x18},
 629         /* Index 0x94~0x97 */
 630         {0x0E, 0x1C, 0x1C}, {0x0E, 0x18, 0x1C}, {0x0E, 0x15, 0x1C}, {0x0E,
 631                                                                      0x11,
 632                                                                      0x1C},
 633         /* Index 0x98~0x9B */
 634         {0x14, 0x14, 0x1C}, {0x16, 0x14, 0x1C}, {0x18, 0x14, 0x1C}, {0x1A,
 635                                                                      0x14,
 636                                                                      0x1C},
 637         /* Index 0x9C~0x9F */
 638         {0x1C, 0x14, 0x1C}, {0x1C, 0x14, 0x1A}, {0x1C, 0x14, 0x18}, {0x1C,
 639                                                                      0x14,
 640                                                                      0x16},
 641         /* Index 0xA0~0xA3 */
 642         {0x1C, 0x14, 0x14}, {0x1C, 0x16, 0x14}, {0x1C, 0x18, 0x14}, {0x1C,
 643                                                                      0x1A,
 644                                                                      0x14},
 645         /* Index 0xA4~0xA7 */
 646         {0x1C, 0x1C, 0x14}, {0x1A, 0x1C, 0x14}, {0x18, 0x1C, 0x14}, {0x16,
 647                                                                      0x1C,
 648                                                                      0x14},
 649         /* Index 0xA8~0xAB */
 650         {0x14, 0x1C, 0x14}, {0x14, 0x1C, 0x16}, {0x14, 0x1C, 0x18}, {0x14,
 651                                                                      0x1C,
 652                                                                      0x1A},
 653         /* Index 0xAC~0xAF */
 654         {0x14, 0x1C, 0x1C}, {0x14, 0x1A, 0x1C}, {0x14, 0x18, 0x1C}, {0x14,
 655                                                                      0x16,
 656                                                                      0x1C},
 657         /* Index 0xB0~0xB3 */
 658         {0x00, 0x00, 0x10}, {0x04, 0x00, 0x10}, {0x08, 0x00, 0x10}, {0x0C,
 659                                                                      0x00,
 660                                                                      0x10},
 661         /* Index 0xB4~0xB7 */
 662         {0x10, 0x00, 0x10}, {0x10, 0x00, 0x0C}, {0x10, 0x00, 0x08}, {0x10,
 663                                                                      0x00,
 664                                                                      0x04},
 665         /* Index 0xB8~0xBB */
 666         {0x10, 0x00, 0x00}, {0x10, 0x04, 0x00}, {0x10, 0x08, 0x00}, {0x10,
 667                                                                      0x0C,
 668                                                                      0x00},
 669         /* Index 0xBC~0xBF */
 670         {0x10, 0x10, 0x00}, {0x0C, 0x10, 0x00}, {0x08, 0x10, 0x00}, {0x04,
 671                                                                      0x10,
 672                                                                      0x00},
 673         /* Index 0xC0~0xC3 */
 674         {0x00, 0x10, 0x00}, {0x00, 0x10, 0x04}, {0x00, 0x10, 0x08}, {0x00,
 675                                                                      0x10,
 676                                                                      0x0C},
 677         /* Index 0xC4~0xC7 */
 678         {0x00, 0x10, 0x10}, {0x00, 0x0C, 0x10}, {0x00, 0x08, 0x10}, {0x00,
 679                                                                      0x04,
 680                                                                      0x10},
 681         /* Index 0xC8~0xCB */
 682         {0x08, 0x08, 0x10}, {0x0A, 0x08, 0x10}, {0x0C, 0x08, 0x10}, {0x0E,
 683                                                                      0x08,
 684                                                                      0x10},
 685         /* Index 0xCC~0xCF */
 686         {0x10, 0x08, 0x10}, {0x10, 0x08, 0x0E}, {0x10, 0x08, 0x0C}, {0x10,
 687                                                                      0x08,
 688                                                                      0x0A},
 689         /* Index 0xD0~0xD3 */
 690         {0x10, 0x08, 0x08}, {0x10, 0x0A, 0x08}, {0x10, 0x0C, 0x08}, {0x10,
 691                                                                      0x0E,
 692                                                                      0x08},
 693         /* Index 0xD4~0xD7 */
 694         {0x10, 0x10, 0x08}, {0x0E, 0x10, 0x08}, {0x0C, 0x10, 0x08}, {0x0A,
 695                                                                      0x10,
 696                                                                      0x08},
 697         /* Index 0xD8~0xDB */
 698         {0x08, 0x10, 0x08}, {0x08, 0x10, 0x0A}, {0x08, 0x10, 0x0C}, {0x08,
 699                                                                      0x10,
 700                                                                      0x0E},
 701         /* Index 0xDC~0xDF */
 702         {0x08, 0x10, 0x10}, {0x08, 0x0E, 0x10}, {0x08, 0x0C, 0x10}, {0x08,
 703                                                                      0x0A,
 704                                                                      0x10},
 705         /* Index 0xE0~0xE3 */
 706         {0x0B, 0x0B, 0x10}, {0x0C, 0x0B, 0x10}, {0x0D, 0x0B, 0x10}, {0x0F,
 707                                                                      0x0B,
 708                                                                      0x10},
 709         /* Index 0xE4~0xE7 */
 710         {0x10, 0x0B, 0x10}, {0x10, 0x0B, 0x0F}, {0x10, 0x0B, 0x0D}, {0x10,
 711                                                                      0x0B,
 712                                                                      0x0C},
 713         /* Index 0xE8~0xEB */
 714         {0x10, 0x0B, 0x0B}, {0x10, 0x0C, 0x0B}, {0x10, 0x0D, 0x0B}, {0x10,
 715                                                                      0x0F,
 716                                                                      0x0B},
 717         /* Index 0xEC~0xEF */
 718         {0x10, 0x10, 0x0B}, {0x0F, 0x10, 0x0B}, {0x0D, 0x10, 0x0B}, {0x0C,
 719                                                                      0x10,
 720                                                                      0x0B},
 721         /* Index 0xF0~0xF3 */
 722         {0x0B, 0x10, 0x0B}, {0x0B, 0x10, 0x0C}, {0x0B, 0x10, 0x0D}, {0x0B,
 723                                                                      0x10,
 724                                                                      0x0F},
 725         /* Index 0xF4~0xF7 */
 726         {0x0B, 0x10, 0x10}, {0x0B, 0x0F, 0x10}, {0x0B, 0x0D, 0x10}, {0x0B,
 727                                                                      0x0C,
 728                                                                      0x10},
 729         /* Index 0xF8~0xFB */
 730         {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00,
 731                                                                      0x00,
 732                                                                      0x00},
 733         /* Index 0xFC~0xFF */
 734         {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00,
 735                                                                      0x00,
 736                                                                      0x00}
 737 };
 738
 739 static struct via_device_mapping device_mapping[] = {
 740         {VIA_LDVP0, "LDVP0"},
 741         {VIA_LDVP1, "LDVP1"},
 742         {VIA_DVP0, "DVP0"},
 743         {VIA_CRT, "CRT"},
 744         {VIA_DVP1, "DVP1"},
 745         {VIA_LVDS1, "LVDS1"},
 746         {VIA_LVDS2, "LVDS2"}
 747 };
 748
 749 static void load_fix_bit_crtc_reg(void);
 750 static void __devinit init_gfx_chip_info(int chip_type);
 751 static void __devinit init_tmds_chip_info(void);
 752 static void __devinit init_lvds_chip_info(void);
 753 static void device_screen_off(void);
 754 static void device_screen_on(void);
 755 static void set_display_channel(void);
 756 static void device_off(void);
 757 static void device_on(void);
 758 static void enable_second_display_channel(void);
 759 static void disable_second_display_channel(void);
 760
 761 void viafb_lock_crt(void)
 762 {
 763         viafb_write_reg_mask(CR11, VIACR, BIT7, BIT7);
 764 }
 765
 766 void viafb_unlock_crt(void)
 767 {
 768         viafb_write_reg_mask(CR11, VIACR, 0, BIT7);
 769         viafb_write_reg_mask(CR47, VIACR, 0, BIT0);
 770 }
 771
 772 static void write_dac_reg(u8 index, u8 r, u8 g, u8 b)
 773 {
 774         outb(index, LUT_INDEX_WRITE);
 775         outb(r, LUT_DATA);
 776         outb(g, LUT_DATA);
 777         outb(b, LUT_DATA);
 778 }
 779
 780 static u32 get_dvi_devices(int output_interface)
 781 {
 782         switch (output_interface) {
 783         case INTERFACE_DVP0:
 784                 return VIA_DVP0 | VIA_LDVP0;
 785
 786         case INTERFACE_DVP1:
 787                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
 788                         return VIA_LDVP1;
 789                 else
 790                         return VIA_DVP1;
 791
 792         case INTERFACE_DFP_HIGH:
 793                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
 794                         return 0;
 795                 else
 796                         return VIA_LVDS2 | VIA_DVP0;
 797
 798         case INTERFACE_DFP_LOW:
 799                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
 800                         return 0;
 801                 else
 802                         return VIA_DVP1 | VIA_LVDS1;
 803
 804         case INTERFACE_TMDS:
 805                 return VIA_LVDS1;
 806         }
 807
 808         return 0;
 809 }
 810
 811 static u32 get_lcd_devices(int output_interface)
 812 {
 813         switch (output_interface) {
 814         case INTERFACE_DVP0:
 815                 return VIA_DVP0;
 816
 817         case INTERFACE_DVP1:
 818                 return VIA_DVP1;
 819
 820         case INTERFACE_DFP_HIGH:
 821                 return VIA_LVDS2 | VIA_DVP0;
 822
 823         case INTERFACE_DFP_LOW:
 824                 return VIA_LVDS1 | VIA_DVP1;
 825
 826         case INTERFACE_DFP:
 827                 return VIA_LVDS1 | VIA_LVDS2;
 828
 829         case INTERFACE_LVDS0:
 830         case INTERFACE_LVDS0LVDS1:
 831                 return VIA_LVDS1;
 832
 833         case INTERFACE_LVDS1:
 834                 return VIA_LVDS2;
 835         }
 836
 837         return 0;
 838 }
 839
 840 /*Set IGA path for each device*/
 841 void viafb_set_iga_path(void)
 842 {
 843
 844         if (viafb_SAMM_ON == 1) {
 845                 if (viafb_CRT_ON) {
 846                         if (viafb_primary_dev == CRT_Device)
 847                                 viaparinfo->crt_setting_info->iga_path = IGA1;
 848                         else
 849                                 viaparinfo->crt_setting_info->iga_path = IGA2;
 850                 }
 851
 852                 if (viafb_DVI_ON) {
 853                         if (viafb_primary_dev == DVI_Device)
 854                                 viaparinfo->tmds_setting_info->iga_path = IGA1;
 855                         else
 856                                 viaparinfo->tmds_setting_info->iga_path = IGA2;
 857                 }
 858
 859                 if (viafb_LCD_ON) {
 860                         if (viafb_primary_dev == LCD_Device) {
 861                                 if (viafb_dual_fb &&
 862                                         (viaparinfo->chip_info->gfx_chip_name ==
 863                                         UNICHROME_CLE266)) {
 864                                         viaparinfo->
 865                                         lvds_setting_info->iga_path = IGA2;
 866                                         viaparinfo->
 867                                         crt_setting_info->iga_path = IGA1;
 868                                         viaparinfo->
 869                                         tmds_setting_info->iga_path = IGA1;
 870                                 } else
 871                                         viaparinfo->
 872                                         lvds_setting_info->iga_path = IGA1;
 873                         } else {
 874                                 viaparinfo->lvds_setting_info->iga_path = IGA2;
 875                         }
 876                 }
 877                 if (viafb_LCD2_ON) {
 878                         if (LCD2_Device == viafb_primary_dev)
 879                                 viaparinfo->lvds_setting_info2->iga_path = IGA1;
 880                         else
 881                                 viaparinfo->lvds_setting_info2->iga_path = IGA2;
 882                 }
 883         } else {
 884                 viafb_SAMM_ON = 0;
 885
 886                 if (viafb_CRT_ON && viafb_LCD_ON) {
 887                         viaparinfo->crt_setting_info->iga_path = IGA1;
 888                         viaparinfo->lvds_setting_info->iga_path = IGA2;
 889                 } else if (viafb_CRT_ON && viafb_DVI_ON) {
 890                         viaparinfo->crt_setting_info->iga_path = IGA1;
 891                         viaparinfo->tmds_setting_info->iga_path = IGA2;
 892                 } else if (viafb_LCD_ON && viafb_DVI_ON) {
 893                         viaparinfo->tmds_setting_info->iga_path = IGA1;
 894                         viaparinfo->lvds_setting_info->iga_path = IGA2;
 895                 } else if (viafb_LCD_ON && viafb_LCD2_ON) {
 896                         viaparinfo->lvds_setting_info->iga_path = IGA2;
 897                         viaparinfo->lvds_setting_info2->iga_path = IGA2;
 898                 } else if (viafb_CRT_ON) {
 899                         viaparinfo->crt_setting_info->iga_path = IGA1;
 900                 } else if (viafb_LCD_ON) {
 901                         viaparinfo->lvds_setting_info->iga_path = IGA2;
 902                 } else if (viafb_DVI_ON) {
 903                         viaparinfo->tmds_setting_info->iga_path = IGA1;
 904                 }
 905         }
 906
 907         viaparinfo->shared->iga1_devices = 0;
 908         viaparinfo->shared->iga2_devices = 0;
 909         if (viafb_CRT_ON) {
 910                 if (viaparinfo->crt_setting_info->iga_path == IGA1)
 911                         viaparinfo->shared->iga1_devices |= VIA_CRT;
 912                 else
 913                         viaparinfo->shared->iga2_devices |= VIA_CRT;
 914         }
 915
 916         if (viafb_DVI_ON) {
 917                 if (viaparinfo->tmds_setting_info->iga_path == IGA1)
 918                         viaparinfo->shared->iga1_devices |= get_dvi_devices(
 919                                 viaparinfo->chip_info->
 920                                 tmds_chip_info.output_interface);
 921                 else
 922                         viaparinfo->shared->iga2_devices |= get_dvi_devices(
 923                                 viaparinfo->chip_info->
 924                                 tmds_chip_info.output_interface);
 925         }
 926
 927         if (viafb_LCD_ON) {
 928                 if (viaparinfo->lvds_setting_info->iga_path == IGA1)
 929                         viaparinfo->shared->iga1_devices |= get_lcd_devices(
 930                                 viaparinfo->chip_info->
 931                                 lvds_chip_info.output_interface);
 932                 else
 933                         viaparinfo->shared->iga2_devices |= get_lcd_devices(
 934                                 viaparinfo->chip_info->
 935                                 lvds_chip_info.output_interface);
 936         }
 937
 938         if (viafb_LCD2_ON) {
 939                 if (viaparinfo->lvds_setting_info2->iga_path == IGA1)
 940                         viaparinfo->shared->iga1_devices |= get_lcd_devices(
 941                                 viaparinfo->chip_info->
 942                                 lvds_chip_info2.output_interface);
 943                 else
 944                         viaparinfo->shared->iga2_devices |= get_lcd_devices(
 945                                 viaparinfo->chip_info->
 946                                 lvds_chip_info2.output_interface);
 947         }
 948 }
 949
 950 static void set_color_register(u8 index, u8 red, u8 green, u8 blue)
 951 {
 952         outb(0xFF, 0x3C6); /* bit mask of palette */
 953         outb(index, 0x3C8);
 954         outb(red, 0x3C9);
 955         outb(green, 0x3C9);
 956         outb(blue, 0x3C9);
 957 }
 958
 959 void viafb_set_primary_color_register(u8 index, u8 red, u8 green, u8 blue)
 960 {
 961         viafb_write_reg_mask(0x1A, VIASR, 0x00, 0x01);
 962         set_color_register(index, red, green, blue);
 963 }
 964
 965 void viafb_set_secondary_color_register(u8 index, u8 red, u8 green, u8 blue)
 966 {
 967         viafb_write_reg_mask(0x1A, VIASR, 0x01, 0x01);
 968         set_color_register(index, red, green, blue);
 969 }
 970
 971 static void set_source_common(u8 index, u8 offset, u8 iga)
 972 {
 973         u8 value, mask = 1 << offset;
 974
 975         switch (iga) {
 976         case IGA1:
 977                 value = 0x00;
 978                 break;
 979         case IGA2:
 980                 value = mask;
 981                 break;
 982         default:
 983                 printk(KERN_WARNING "viafb: Unsupported source: %d\n", iga);
 984                 return;
 985         }
 986
 987         via_write_reg_mask(VIACR, index, value, mask);
 988 }
 989
 990 static void set_crt_source(u8 iga)
 991 {
 992         u8 value;
 993
 994         switch (iga) {
 995         case IGA1:
 996                 value = 0x00;
 997                 break;
 998         case IGA2:
 999                 value = 0x40;
1000                 break;
1001         default:
1002                 printk(KERN_WARNING "viafb: Unsupported source: %d\n", iga);
1003                 return;
1004         }
1005
1006         via_write_reg_mask(VIASR, 0x16, value, 0x40);
1007 }
1008
1009 static inline void set_ldvp0_source(u8 iga)
1010 {
1011         set_source_common(0x6C, 7, iga);
1012 }
1013
1014 static inline void set_ldvp1_source(u8 iga)
1015 {
1016         set_source_common(0x93, 7, iga);
1017 }
1018
1019 static inline void set_dvp0_source(u8 iga)
1020 {
1021         set_source_common(0x96, 4, iga);
1022 }
1023
1024 static inline void set_dvp1_source(u8 iga)
1025 {
1026         set_source_common(0x9B, 4, iga);
1027 }
1028
1029 static inline void set_lvds1_source(u8 iga)
1030 {
1031         set_source_common(0x99, 4, iga);
1032 }
1033
1034 static inline void set_lvds2_source(u8 iga)
1035 {
1036         set_source_common(0x97, 4, iga);
1037 }
1038
1039 void via_set_source(u32 devices, u8 iga)
1040 {
1041         if (devices & VIA_LDVP0)
1042                 set_ldvp0_source(iga);
1043         if (devices & VIA_LDVP1)
1044                 set_ldvp1_source(iga);
1045         if (devices & VIA_DVP0)
1046                 set_dvp0_source(iga);
1047         if (devices & VIA_CRT)
1048                 set_crt_source(iga);
1049         if (devices & VIA_DVP1)
1050                 set_dvp1_source(iga);
1051         if (devices & VIA_LVDS1)
1052                 set_lvds1_source(iga);
1053         if (devices & VIA_LVDS2)
1054                 set_lvds2_source(iga);
1055 }
1056
1057 static void set_crt_state(u8 state)
1058 {
1059         u8 value;
1060
1061         switch (state) {
1062         case VIA_STATE_ON:
1063                 value = 0x00;
1064                 break;
1065         case VIA_STATE_STANDBY:
1066                 value = 0x10;
1067                 break;
1068         case VIA_STATE_SUSPEND:
1069                 value = 0x20;
1070                 break;
1071         case VIA_STATE_OFF:
1072                 value = 0x30;
1073                 break;
1074         default:
1075                 return;
1076         }
1077
1078         via_write_reg_mask(VIACR, 0x36, value, 0x30);
1079 }
1080
1081 static void set_dvp0_state(u8 state)
1082 {
1083         u8 value;
1084
1085         switch (state) {
1086         case VIA_STATE_ON:
1087                 value = 0xC0;
1088                 break;
1089         case VIA_STATE_OFF:
1090                 value = 0x00;
1091                 break;
1092         default:
1093                 return;
1094         }
1095
1096         via_write_reg_mask(VIASR, 0x1E, value, 0xC0);
1097 }
1098
1099 static void set_dvp1_state(u8 state)
1100 {
1101         u8 value;
1102
1103         switch (state) {
1104         case VIA_STATE_ON:
1105                 value = 0x30;
1106                 break;
1107         case VIA_STATE_OFF:
1108                 value = 0x00;
1109                 break;
1110         default:
1111                 return;
1112         }
1113
1114         via_write_reg_mask(VIASR, 0x1E, value, 0x30);
1115 }
1116
1117 static void set_lvds1_state(u8 state)
1118 {
1119         u8 value;
1120
1121         switch (state) {
1122         case VIA_STATE_ON:
1123                 value = 0x03;
1124                 break;
1125         case VIA_STATE_OFF:
1126                 value = 0x00;
1127                 break;
1128         default:
1129                 return;
1130         }
1131
1132         via_write_reg_mask(VIASR, 0x2A, value, 0x03);
1133 }
1134
1135 static void set_lvds2_state(u8 state)
1136 {
1137         u8 value;
1138
1139         switch (state) {
1140         case VIA_STATE_ON:
1141                 value = 0x0C;
1142                 break;
1143         case VIA_STATE_OFF:
1144                 value = 0x00;
1145                 break;
1146         default:
1147                 return;
1148         }
1149
1150         via_write_reg_mask(VIASR, 0x2A, value, 0x0C);
1151 }
1152
1153 void via_set_state(u32 devices, u8 state)
1154 {
1155         /*
1156         TODO: Can we enable/disable these devices? How?
1157         if (devices & VIA_LDVP0)
1158         if (devices & VIA_LDVP1)
1159         */
1160         if (devices & VIA_DVP0)
1161                 set_dvp0_state(state);
1162         if (devices & VIA_CRT)
1163                 set_crt_state(state);
1164         if (devices & VIA_DVP1)
1165                 set_dvp1_state(state);
1166         if (devices & VIA_LVDS1)
1167                 set_lvds1_state(state);
1168         if (devices & VIA_LVDS2)
1169                 set_lvds2_state(state);
1170 }
1171
1172 void via_set_sync_polarity(u32 devices, u8 polarity)
1173 {
1174         if (polarity & ~(VIA_HSYNC_NEGATIVE | VIA_VSYNC_NEGATIVE)) {
1175                 printk(KERN_WARNING "viafb: Unsupported polarity: %d\n",
1176                         polarity);
1177                 return;
1178         }
1179
1180         if (devices & VIA_CRT)
1181                 via_write_misc_reg_mask(polarity << 6, 0xC0);
1182         if (devices & VIA_DVP1)
1183                 via_write_reg_mask(VIACR, 0x9B, polarity << 5, 0x60);
1184         if (devices & VIA_LVDS1)
1185                 via_write_reg_mask(VIACR, 0x99, polarity << 5, 0x60);
1186         if (devices & VIA_LVDS2)
1187                 via_write_reg_mask(VIACR, 0x97, polarity << 5, 0x60);
1188 }
1189
1190 u32 via_parse_odev(char *input, char **end)
1191 {
1192         char *ptr = input;
1193         u32 odev = 0;
1194         bool next = true;
1195         int i, len;
1196
1197         while (next) {
1198                 next = false;
1199                 for (i = 0; i < ARRAY_SIZE(device_mapping); i++) {
1200                         len = strlen(device_mapping[i].name);
1201                         if (!strncmp(ptr, device_mapping[i].name, len)) {
1202                                 odev |= device_mapping[i].device;
1203                                 ptr += len;
1204                                 if (*ptr == ',') {
1205                                         ptr++;
1206                                         next = true;
1207                                 }
1208                         }
1209                 }
1210         }
1211
1212         *end = ptr;
1213         return odev;
1214 }
1215
1216 void via_odev_to_seq(struct seq_file *m, u32 odev)
1217 {
1218         int i, count = 0;
1219
1220         for (i = 0; i < ARRAY_SIZE(device_mapping); i++) {
1221                 if (odev & device_mapping[i].device) {
1222                         if (count > 0)
1223                                 seq_putc(m, ',');
1224
1225                         seq_puts(m, device_mapping[i].name);
1226                         count++;
1227                 }
1228         }
1229
1230         seq_putc(m, '\n');
1231 }
1232
1233 static void load_fix_bit_crtc_reg(void)
1234 {
1235         /* always set to 1 */
1236         viafb_write_reg_mask(CR03, VIACR, 0x80, BIT7);
1237         /* line compare should set all bits = 1 (extend modes) */
1238         viafb_write_reg(CR18, VIACR, 0xff);
1239         /* line compare should set all bits = 1 (extend modes) */
1240         viafb_write_reg_mask(CR07, VIACR, 0x10, BIT4);
1241         /* line compare should set all bits = 1 (extend modes) */
1242         viafb_write_reg_mask(CR09, VIACR, 0x40, BIT6);
1243         /* line compare should set all bits = 1 (extend modes) */
1244         viafb_write_reg_mask(CR35, VIACR, 0x10, BIT4);
1245         /* line compare should set all bits = 1 (extend modes) */
1246         viafb_write_reg_mask(CR33, VIACR, 0x06, BIT0 + BIT1 + BIT2);
1247         /*viafb_write_reg_mask(CR32, VIACR, 0x01, BIT0); */
1248         /* extend mode always set to e3h */
1249         viafb_write_reg(CR17, VIACR, 0xe3);
1250         /* extend mode always set to 0h */
1251         viafb_write_reg(CR08, VIACR, 0x00);
1252         /* extend mode always set to 0h */
1253         viafb_write_reg(CR14, VIACR, 0x00);
1254
1255         /* If K8M800, enable Prefetch Mode. */
1256         if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800)
1257                 || (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890))
1258                 viafb_write_reg_mask(CR33, VIACR, 0x08, BIT3);
1259         if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
1260             && (viaparinfo->chip_info->gfx_chip_revision == CLE266_REVISION_AX))
1261                 viafb_write_reg_mask(SR1A, VIASR, 0x02, BIT1);
1262
1263 }
1264
1265 void viafb_load_reg(int timing_value, int viafb_load_reg_num,
1266         struct io_register *reg,
1267               int io_type)
1268 {
1269         int reg_mask;
1270         int bit_num = 0;
1271         int data;
1272         int i, j;
1273         int shift_next_reg;
1274         int start_index, end_index, cr_index;
1275         u16 get_bit;
1276
1277         for (i = 0; i < viafb_load_reg_num; i++) {
1278                 reg_mask = 0;
1279                 data = 0;
1280                 start_index = reg[i].start_bit;
1281                 end_index = reg[i].end_bit;
1282                 cr_index = reg[i].io_addr;
1283
1284                 shift_next_reg = bit_num;
1285                 for (j = start_index; j <= end_index; j++) {
1286                         /*if (bit_num==8) timing_value = timing_value >>8; */
1287                         reg_mask = reg_mask | (BIT0 << j);
1288                         get_bit = (timing_value & (BIT0 << bit_num));
1289                         data =
1290                             data | ((get_bit >> shift_next_reg) << start_index);
1291                         bit_num++;
1292                 }
1293                 if (io_type == VIACR)
1294                         viafb_write_reg_mask(cr_index, VIACR, data, reg_mask);
1295                 else
1296                         viafb_write_reg_mask(cr_index, VIASR, data, reg_mask);
1297         }
1298
1299 }
1300
1301 /* Write Registers */
1302 void viafb_write_regx(struct io_reg RegTable[], int ItemNum)
1303 {
1304         int i;
1305
1306         /*DEBUG_MSG(KERN_INFO "Table Size : %x!!\n",ItemNum ); */
1307
1308         for (i = 0; i < ItemNum; i++)
1309                 via_write_reg_mask(RegTable[i].port, RegTable[i].index,
1310                         RegTable[i].value, RegTable[i].mask);
1311 }
1312
1313 void viafb_load_fetch_count_reg(int h_addr, int bpp_byte, int set_iga)
1314 {
1315         int reg_value;
1316         int viafb_load_reg_num;
1317         struct io_register *reg = NULL;
1318
1319         switch (set_iga) {
1320         case IGA1:
1321                 reg_value = IGA1_FETCH_COUNT_FORMULA(h_addr, bpp_byte);
1322                 viafb_load_reg_num = fetch_count_reg.
1323                         iga1_fetch_count_reg.reg_num;
1324                 reg = fetch_count_reg.iga1_fetch_count_reg.reg;
1325                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1326                 break;
1327         case IGA2:
1328                 reg_value = IGA2_FETCH_COUNT_FORMULA(h_addr, bpp_byte);
1329                 viafb_load_reg_num = fetch_count_reg.
1330                         iga2_fetch_count_reg.reg_num;
1331                 reg = fetch_count_reg.iga2_fetch_count_reg.reg;
1332                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1333                 break;
1334         }
1335
1336 }
1337
1338 void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active)
1339 {
1340         int reg_value;
1341         int viafb_load_reg_num;
1342         struct io_register *reg = NULL;
1343         int iga1_fifo_max_depth = 0, iga1_fifo_threshold =
1344             0, iga1_fifo_high_threshold = 0, iga1_display_queue_expire_num = 0;
1345         int iga2_fifo_max_depth = 0, iga2_fifo_threshold =
1346             0, iga2_fifo_high_threshold = 0, iga2_display_queue_expire_num = 0;
1347
1348         if (set_iga == IGA1) {
1349                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1350                         iga1_fifo_max_depth = K800_IGA1_FIFO_MAX_DEPTH;
1351                         iga1_fifo_threshold = K800_IGA1_FIFO_THRESHOLD;
1352                         iga1_fifo_high_threshold =
1353                             K800_IGA1_FIFO_HIGH_THRESHOLD;
1354                         /* If resolution > 1280x1024, expire length = 64, else
1355                            expire length = 128 */
1356                         if ((hor_active > 1280) && (ver_active > 1024))
1357                                 iga1_display_queue_expire_num = 16;
1358                         else
1359                                 iga1_display_queue_expire_num =
1360                                     K800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1361
1362                 }
1363
1364                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_PM800) {
1365                         iga1_fifo_max_depth = P880_IGA1_FIFO_MAX_DEPTH;
1366                         iga1_fifo_threshold = P880_IGA1_FIFO_THRESHOLD;
1367                         iga1_fifo_high_threshold =
1368                             P880_IGA1_FIFO_HIGH_THRESHOLD;
1369                         iga1_display_queue_expire_num =
1370                             P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1371
1372                         /* If resolution > 1280x1024, expire length = 64, else
1373                            expire length = 128 */
1374                         if ((hor_active > 1280) && (ver_active > 1024))
1375                                 iga1_display_queue_expire_num = 16;
1376                         else
1377                                 iga1_display_queue_expire_num =
1378                                     P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1379                 }
1380
1381                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CN700) {
1382                         iga1_fifo_max_depth = CN700_IGA1_FIFO_MAX_DEPTH;
1383                         iga1_fifo_threshold = CN700_IGA1_FIFO_THRESHOLD;
1384                         iga1_fifo_high_threshold =
1385                             CN700_IGA1_FIFO_HIGH_THRESHOLD;
1386
1387                         /* If resolution > 1280x1024, expire length = 64,
1388                            else expire length = 128 */
1389                         if ((hor_active > 1280) && (ver_active > 1024))
1390                                 iga1_display_queue_expire_num = 16;
1391                         else
1392                                 iga1_display_queue_expire_num =
1393                                     CN700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1394                 }
1395
1396                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
1397                         iga1_fifo_max_depth = CX700_IGA1_FIFO_MAX_DEPTH;
1398                         iga1_fifo_threshold = CX700_IGA1_FIFO_THRESHOLD;
1399                         iga1_fifo_high_threshold =
1400                             CX700_IGA1_FIFO_HIGH_THRESHOLD;
1401                         iga1_display_queue_expire_num =
1402                             CX700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1403                 }
1404
1405                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890) {
1406                         iga1_fifo_max_depth = K8M890_IGA1_FIFO_MAX_DEPTH;
1407                         iga1_fifo_threshold = K8M890_IGA1_FIFO_THRESHOLD;
1408                         iga1_fifo_high_threshold =
1409                             K8M890_IGA1_FIFO_HIGH_THRESHOLD;
1410                         iga1_display_queue_expire_num =
1411                             K8M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1412                 }
1413
1414                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M890) {
1415                         iga1_fifo_max_depth = P4M890_IGA1_FIFO_MAX_DEPTH;
1416                         iga1_fifo_threshold = P4M890_IGA1_FIFO_THRESHOLD;
1417                         iga1_fifo_high_threshold =
1418                             P4M890_IGA1_FIFO_HIGH_THRESHOLD;
1419                         iga1_display_queue_expire_num =
1420                             P4M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1421                 }
1422
1423                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M900) {
1424                         iga1_fifo_max_depth = P4M900_IGA1_FIFO_MAX_DEPTH;
1425                         iga1_fifo_threshold = P4M900_IGA1_FIFO_THRESHOLD;
1426                         iga1_fifo_high_threshold =
1427                             P4M900_IGA1_FIFO_HIGH_THRESHOLD;
1428                         iga1_display_queue_expire_num =
1429                             P4M900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1430                 }
1431
1432                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX800) {
1433                         iga1_fifo_max_depth = VX800_IGA1_FIFO_MAX_DEPTH;
1434                         iga1_fifo_threshold = VX800_IGA1_FIFO_THRESHOLD;
1435                         iga1_fifo_high_threshold =
1436                             VX800_IGA1_FIFO_HIGH_THRESHOLD;
1437                         iga1_display_queue_expire_num =
1438                             VX800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1439                 }
1440
1441                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX855) {
1442                         iga1_fifo_max_depth = VX855_IGA1_FIFO_MAX_DEPTH;
1443                         iga1_fifo_threshold = VX855_IGA1_FIFO_THRESHOLD;
1444                         iga1_fifo_high_threshold =
1445                             VX855_IGA1_FIFO_HIGH_THRESHOLD;
1446                         iga1_display_queue_expire_num =
1447                             VX855_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1448                 }
1449
1450                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX900) {
1451                         iga1_fifo_max_depth = VX900_IGA1_FIFO_MAX_DEPTH;
1452                         iga1_fifo_threshold = VX900_IGA1_FIFO_THRESHOLD;
1453                         iga1_fifo_high_threshold =
1454                             VX900_IGA1_FIFO_HIGH_THRESHOLD;
1455                         iga1_display_queue_expire_num =
1456                             VX900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1457                 }
1458
1459                 /* Set Display FIFO Depath Select */
1460                 reg_value = IGA1_FIFO_DEPTH_SELECT_FORMULA(iga1_fifo_max_depth);
1461                 viafb_load_reg_num =
1462                     display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg_num;
1463                 reg = display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg;
1464                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1465
1466                 /* Set Display FIFO Threshold Select */
1467                 reg_value = IGA1_FIFO_THRESHOLD_FORMULA(iga1_fifo_threshold);
1468                 viafb_load_reg_num =
1469                     fifo_threshold_select_reg.
1470                     iga1_fifo_threshold_select_reg.reg_num;
1471                 reg =
1472                     fifo_threshold_select_reg.
1473                     iga1_fifo_threshold_select_reg.reg;
1474                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1475
1476                 /* Set FIFO High Threshold Select */
1477                 reg_value =
1478                     IGA1_FIFO_HIGH_THRESHOLD_FORMULA(iga1_fifo_high_threshold);
1479                 viafb_load_reg_num =
1480                     fifo_high_threshold_select_reg.
1481                     iga1_fifo_high_threshold_select_reg.reg_num;
1482                 reg =
1483                     fifo_high_threshold_select_reg.
1484                     iga1_fifo_high_threshold_select_reg.reg;
1485                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1486
1487                 /* Set Display Queue Expire Num */
1488                 reg_value =
1489                     IGA1_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA
1490                     (iga1_display_queue_expire_num);
1491                 viafb_load_reg_num =
1492                     display_queue_expire_num_reg.
1493                     iga1_display_queue_expire_num_reg.reg_num;
1494                 reg =
1495                     display_queue_expire_num_reg.
1496                     iga1_display_queue_expire_num_reg.reg;
1497                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1498
1499         } else {
1500                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1501                         iga2_fifo_max_depth = K800_IGA2_FIFO_MAX_DEPTH;
1502                         iga2_fifo_threshold = K800_IGA2_FIFO_THRESHOLD;
1503                         iga2_fifo_high_threshold =
1504                             K800_IGA2_FIFO_HIGH_THRESHOLD;
1505
1506                         /* If resolution > 1280x1024, expire length = 64,
1507                            else  expire length = 128 */
1508                         if ((hor_active > 1280) && (ver_active > 1024))
1509                                 iga2_display_queue_expire_num = 16;
1510                         else
1511                                 iga2_display_queue_expire_num =
1512                                     K800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1513                 }
1514
1515                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_PM800) {
1516                         iga2_fifo_max_depth = P880_IGA2_FIFO_MAX_DEPTH;
1517                         iga2_fifo_threshold = P880_IGA2_FIFO_THRESHOLD;
1518                         iga2_fifo_high_threshold =
1519                             P880_IGA2_FIFO_HIGH_THRESHOLD;
1520
1521                         /* If resolution > 1280x1024, expire length = 64,
1522                            else  expire length = 128 */
1523                         if ((hor_active > 1280) && (ver_active > 1024))
1524                                 iga2_display_queue_expire_num = 16;
1525                         else
1526                                 iga2_display_queue_expire_num =
1527                                     P880_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1528                 }
1529
1530                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CN700) {
1531                         iga2_fifo_max_depth = CN700_IGA2_FIFO_MAX_DEPTH;
1532                         iga2_fifo_threshold = CN700_IGA2_FIFO_THRESHOLD;
1533                         iga2_fifo_high_threshold =
1534                             CN700_IGA2_FIFO_HIGH_THRESHOLD;
1535
1536                         /* If resolution > 1280x1024, expire length = 64,
1537                            else expire length = 128 */
1538                         if ((hor_active > 1280) && (ver_active > 1024))
1539                                 iga2_display_queue_expire_num = 16;
1540                         else
1541                                 iga2_display_queue_expire_num =
1542                                     CN700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1543                 }
1544
1545                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
1546                         iga2_fifo_max_depth = CX700_IGA2_FIFO_MAX_DEPTH;
1547                         iga2_fifo_threshold = CX700_IGA2_FIFO_THRESHOLD;
1548                         iga2_fifo_high_threshold =
1549                             CX700_IGA2_FIFO_HIGH_THRESHOLD;
1550                         iga2_display_queue_expire_num =
1551                             CX700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1552                 }
1553
1554                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890) {
1555                         iga2_fifo_max_depth = K8M890_IGA2_FIFO_MAX_DEPTH;
1556                         iga2_fifo_threshold = K8M890_IGA2_FIFO_THRESHOLD;
1557                         iga2_fifo_high_threshold =
1558                             K8M890_IGA2_FIFO_HIGH_THRESHOLD;
1559                         iga2_display_queue_expire_num =
1560                             K8M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1561                 }
1562
1563                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M890) {
1564                         iga2_fifo_max_depth = P4M890_IGA2_FIFO_MAX_DEPTH;
1565                         iga2_fifo_threshold = P4M890_IGA2_FIFO_THRESHOLD;
1566                         iga2_fifo_high_threshold =
1567                             P4M890_IGA2_FIFO_HIGH_THRESHOLD;
1568                         iga2_display_queue_expire_num =
1569                             P4M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1570                 }
1571
1572                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M900) {
1573                         iga2_fifo_max_depth = P4M900_IGA2_FIFO_MAX_DEPTH;
1574                         iga2_fifo_threshold = P4M900_IGA2_FIFO_THRESHOLD;
1575                         iga2_fifo_high_threshold =
1576                             P4M900_IGA2_FIFO_HIGH_THRESHOLD;
1577                         iga2_display_queue_expire_num =
1578                             P4M900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1579                 }
1580
1581                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX800) {
1582                         iga2_fifo_max_depth = VX800_IGA2_FIFO_MAX_DEPTH;
1583                         iga2_fifo_threshold = VX800_IGA2_FIFO_THRESHOLD;
1584                         iga2_fifo_high_threshold =
1585                             VX800_IGA2_FIFO_HIGH_THRESHOLD;
1586                         iga2_display_queue_expire_num =
1587                             VX800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1588                 }
1589
1590                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX855) {
1591                         iga2_fifo_max_depth = VX855_IGA2_FIFO_MAX_DEPTH;
1592                         iga2_fifo_threshold = VX855_IGA2_FIFO_THRESHOLD;
1593                         iga2_fifo_high_threshold =
1594                             VX855_IGA2_FIFO_HIGH_THRESHOLD;
1595                         iga2_display_queue_expire_num =
1596                             VX855_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1597                 }
1598
1599                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX900) {
1600                         iga2_fifo_max_depth = VX900_IGA2_FIFO_MAX_DEPTH;
1601                         iga2_fifo_threshold = VX900_IGA2_FIFO_THRESHOLD;
1602                         iga2_fifo_high_threshold =
1603                             VX900_IGA2_FIFO_HIGH_THRESHOLD;
1604                         iga2_display_queue_expire_num =
1605                             VX900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1606                 }
1607
1608                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1609                         /* Set Display FIFO Depath Select */
1610                         reg_value =
1611                             IGA2_FIFO_DEPTH_SELECT_FORMULA(iga2_fifo_max_depth)
1612                             - 1;
1613                         /* Patch LCD in IGA2 case */
1614                         viafb_load_reg_num =
1615                             display_fifo_depth_reg.
1616                             iga2_fifo_depth_select_reg.reg_num;
1617                         reg =
1618                             display_fifo_depth_reg.
1619                             iga2_fifo_depth_select_reg.reg;
1620                         viafb_load_reg(reg_value,
1621                                 viafb_load_reg_num, reg, VIACR);
1622                 } else {
1623
1624                         /* Set Display FIFO Depath Select */
1625                         reg_value =
1626                             IGA2_FIFO_DEPTH_SELECT_FORMULA(iga2_fifo_max_depth);
1627                         viafb_load_reg_num =
1628                             display_fifo_depth_reg.
1629                             iga2_fifo_depth_select_reg.reg_num;
1630                         reg =
1631                             display_fifo_depth_reg.
1632                             iga2_fifo_depth_select_reg.reg;
1633                         viafb_load_reg(reg_value,
1634                                 viafb_load_reg_num, reg, VIACR);
1635                 }
1636
1637                 /* Set Display FIFO Threshold Select */
1638                 reg_value = IGA2_FIFO_THRESHOLD_FORMULA(iga2_fifo_threshold);
1639                 viafb_load_reg_num =
1640                     fifo_threshold_select_reg.
1641                     iga2_fifo_threshold_select_reg.reg_num;
1642                 reg =
1643                     fifo_threshold_select_reg.
1644                     iga2_fifo_threshold_select_reg.reg;
1645                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1646
1647                 /* Set FIFO High Threshold Select */
1648                 reg_value =
1649                     IGA2_FIFO_HIGH_THRESHOLD_FORMULA(iga2_fifo_high_threshold);
1650                 viafb_load_reg_num =
1651                     fifo_high_threshold_select_reg.
1652                     iga2_fifo_high_threshold_select_reg.reg_num;
1653                 reg =
1654                     fifo_high_threshold_select_reg.
1655                     iga2_fifo_high_threshold_select_reg.reg;
1656                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1657
1658                 /* Set Display Queue Expire Num */
1659                 reg_value =
1660                     IGA2_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA
1661                     (iga2_display_queue_expire_num);
1662                 viafb_load_reg_num =
1663                     display_queue_expire_num_reg.
1664                     iga2_display_queue_expire_num_reg.reg_num;
1665                 reg =
1666                     display_queue_expire_num_reg.
1667                     iga2_display_queue_expire_num_reg.reg;
1668                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1669
1670         }
1671
1672 }
1673
1674 static u32 cle266_encode_pll(struct pll_config pll)
1675 {
1676         return (pll.multiplier << 8)
1677                 | (pll.rshift << 6)
1678                 | pll.divisor;
1679 }
1680
1681 static u32 k800_encode_pll(struct pll_config pll)
1682 {
1683         return ((pll.divisor - 2) << 16)
1684                 | (pll.rshift << 10)
1685                 | (pll.multiplier - 2);
1686 }
1687
1688 static u32 vx855_encode_pll(struct pll_config pll)
1689 {
1690         return (pll.divisor << 16)
1691                 | (pll.rshift << 10)
1692                 | pll.multiplier;
1693 }
1694
1695 u32 viafb_get_clk_value(int clk)
1696 {
1697         u32 value = 0;
1698         int i = 0;
1699
1700         while (i < NUM_TOTAL_PLL_TABLE && clk != pll_value[i].clk)
1701                 i++;
1702
1703         if (i == NUM_TOTAL_PLL_TABLE) {
1704                 printk(KERN_WARNING "viafb_get_clk_value: PLL lookup failed!");
1705         } else {
1706                 switch (viaparinfo->chip_info->gfx_chip_name) {
1707                 case UNICHROME_CLE266:
1708                 case UNICHROME_K400:
1709                         value = cle266_encode_pll(pll_value[i].cle266_pll);
1710                         break;
1711
1712                 case UNICHROME_K800:
1713                 case UNICHROME_PM800:
1714                 case UNICHROME_CN700:
1715                         value = k800_encode_pll(pll_value[i].k800_pll);
1716                         break;
1717
1718                 case UNICHROME_CX700:
1719                 case UNICHROME_CN750:
1720                 case UNICHROME_K8M890:
1721                 case UNICHROME_P4M890:
1722                 case UNICHROME_P4M900:
1723                 case UNICHROME_VX800:
1724                         value = k800_encode_pll(pll_value[i].cx700_pll);
1725                         break;
1726
1727                 case UNICHROME_VX855:
1728                 case UNICHROME_VX900:
1729                         value = vx855_encode_pll(pll_value[i].vx855_pll);
1730                         break;
1731                 }
1732         }
1733
1734         return value;
1735 }
1736
1737 /* Set VCLK*/
1738 void viafb_set_vclock(u32 clk, int set_iga)
1739 {
1740         /* H.W. Reset : ON */
1741         viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
1742
1743         if (set_iga == IGA1) {
1744                 /* Change D,N FOR VCLK */
1745                 switch (viaparinfo->chip_info->gfx_chip_name) {
1746                 case UNICHROME_CLE266:
1747                 case UNICHROME_K400:
1748                         via_write_reg(VIASR, SR46, (clk & 0x00FF));
1749                         via_write_reg(VIASR, SR47, (clk & 0xFF00) >> 8);
1750                         break;
1751
1752                 case UNICHROME_K800:
1753                 case UNICHROME_PM800:
1754                 case UNICHROME_CN700:
1755                 case UNICHROME_CX700:
1756                 case UNICHROME_CN750:
1757                 case UNICHROME_K8M890:
1758                 case UNICHROME_P4M890:
1759                 case UNICHROME_P4M900:
1760                 case UNICHROME_VX800:
1761                 case UNICHROME_VX855:
1762                 case UNICHROME_VX900:
1763                         via_write_reg(VIASR, SR44, (clk & 0x0000FF));
1764                         via_write_reg(VIASR, SR45, (clk & 0x00FF00) >> 8);
1765                         via_write_reg(VIASR, SR46, (clk & 0xFF0000) >> 16);
1766                         break;
1767                 }
1768         }
1769
1770         if (set_iga == IGA2) {
1771                 /* Change D,N FOR LCK */
1772                 switch (viaparinfo->chip_info->gfx_chip_name) {
1773                 case UNICHROME_CLE266:
1774                 case UNICHROME_K400:
1775                         via_write_reg(VIASR, SR44, (clk & 0x00FF));
1776                         via_write_reg(VIASR, SR45, (clk & 0xFF00) >> 8);
1777                         break;
1778
1779                 case UNICHROME_K800:
1780                 case UNICHROME_PM800:
1781                 case UNICHROME_CN700:
1782                 case UNICHROME_CX700:
1783                 case UNICHROME_CN750:
1784                 case UNICHROME_K8M890:
1785                 case UNICHROME_P4M890:
1786                 case UNICHROME_P4M900:
1787                 case UNICHROME_VX800:
1788                 case UNICHROME_VX855:
1789                 case UNICHROME_VX900:
1790                         via_write_reg(VIASR, SR4A, (clk & 0x0000FF));
1791                         via_write_reg(VIASR, SR4B, (clk & 0x00FF00) >> 8);
1792                         via_write_reg(VIASR, SR4C, (clk & 0xFF0000) >> 16);
1793                         break;
1794                 }
1795         }
1796
1797         /* H.W. Reset : OFF */
1798         viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
1799
1800         /* Reset PLL */
1801         if (set_iga == IGA1) {
1802                 viafb_write_reg_mask(SR40, VIASR, 0x02, BIT1);
1803                 viafb_write_reg_mask(SR40, VIASR, 0x00, BIT1);
1804         }
1805
1806         if (set_iga == IGA2) {
1807                 viafb_write_reg_mask(SR40, VIASR, 0x04, BIT2);
1808                 viafb_write_reg_mask(SR40, VIASR, 0x00, BIT2);
1809         }
1810
1811         /* Fire! */
1812         via_write_misc_reg_mask(0x0C, 0x0C); /* select external clock */
1813 }
1814
1815 void viafb_load_crtc_timing(struct display_timing device_timing,
1816         int set_iga)
1817 {
1818         int i;
1819         int viafb_load_reg_num = 0;
1820         int reg_value = 0;
1821         struct io_register *reg = NULL;
1822
1823         viafb_unlock_crt();
1824
1825         for (i = 0; i < 12; i++) {
1826                 if (set_iga == IGA1) {
1827                         switch (i) {
1828                         case H_TOTAL_INDEX:
1829                                 reg_value =
1830                                     IGA1_HOR_TOTAL_FORMULA(device_timing.
1831                                                            hor_total);
1832                                 viafb_load_reg_num =
1833                                         iga1_crtc_reg.hor_total.reg_num;
1834                                 reg = iga1_crtc_reg.hor_total.reg;
1835                                 break;
1836                         case H_ADDR_INDEX:
1837                                 reg_value =
1838                                     IGA1_HOR_ADDR_FORMULA(device_timing.
1839                                                           hor_addr);
1840                                 viafb_load_reg_num =
1841                                         iga1_crtc_reg.hor_addr.reg_num;
1842                                 reg = iga1_crtc_reg.hor_addr.reg;
1843                                 break;
1844                         case H_BLANK_START_INDEX:
1845                                 reg_value =
1846                                     IGA1_HOR_BLANK_START_FORMULA
1847                                     (device_timing.hor_blank_start);
1848                                 viafb_load_reg_num =
1849                                     iga1_crtc_reg.hor_blank_start.reg_num;
1850                                 reg = iga1_crtc_reg.hor_blank_start.reg;
1851                                 break;
1852                         case H_BLANK_END_INDEX:
1853                                 reg_value =
1854                                     IGA1_HOR_BLANK_END_FORMULA
1855                                     (device_timing.hor_blank_start,
1856                                      device_timing.hor_blank_end);
1857                                 viafb_load_reg_num =
1858                                     iga1_crtc_reg.hor_blank_end.reg_num;
1859                                 reg = iga1_crtc_reg.hor_blank_end.reg;
1860                                 break;
1861                         case H_SYNC_START_INDEX:
1862                                 reg_value =
1863                                     IGA1_HOR_SYNC_START_FORMULA
1864                                     (device_timing.hor_sync_start);
1865                                 viafb_load_reg_num =
1866                                     iga1_crtc_reg.hor_sync_start.reg_num;
1867                                 reg = iga1_crtc_reg.hor_sync_start.reg;
1868                                 break;
1869                         case H_SYNC_END_INDEX:
1870                                 reg_value =
1871                                     IGA1_HOR_SYNC_END_FORMULA
1872                                     (device_timing.hor_sync_start,
1873                                      device_timing.hor_sync_end);
1874                                 viafb_load_reg_num =
1875                                     iga1_crtc_reg.hor_sync_end.reg_num;
1876                                 reg = iga1_crtc_reg.hor_sync_end.reg;
1877                                 break;
1878                         case V_TOTAL_INDEX:
1879                                 reg_value =
1880                                     IGA1_VER_TOTAL_FORMULA(device_timing.
1881                                                            ver_total);
1882                                 viafb_load_reg_num =
1883                                         iga1_crtc_reg.ver_total.reg_num;
1884                                 reg = iga1_crtc_reg.ver_total.reg;
1885                                 break;
1886                         case V_ADDR_INDEX:
1887                                 reg_value =
1888                                     IGA1_VER_ADDR_FORMULA(device_timing.
1889                                                           ver_addr);
1890                                 viafb_load_reg_num =
1891                                         iga1_crtc_reg.ver_addr.reg_num;
1892                                 reg = iga1_crtc_reg.ver_addr.reg;
1893                                 break;
1894                         case V_BLANK_START_INDEX:
1895                                 reg_value =
1896                                     IGA1_VER_BLANK_START_FORMULA
1897                                     (device_timing.ver_blank_start);
1898                                 viafb_load_reg_num =
1899                                     iga1_crtc_reg.ver_blank_start.reg_num;
1900                                 reg = iga1_crtc_reg.ver_blank_start.reg;
1901                                 break;
1902                         case V_BLANK_END_INDEX:
1903                                 reg_value =
1904                                     IGA1_VER_BLANK_END_FORMULA
1905                                     (device_timing.ver_blank_start,
1906                                      device_timing.ver_blank_end);
1907                                 viafb_load_reg_num =
1908                                     iga1_crtc_reg.ver_blank_end.reg_num;
1909                                 reg = iga1_crtc_reg.ver_blank_end.reg;
1910                                 break;
1911                         case V_SYNC_START_INDEX:
1912                                 reg_value =
1913                                     IGA1_VER_SYNC_START_FORMULA
1914                                     (device_timing.ver_sync_start);
1915                                 viafb_load_reg_num =
1916                                     iga1_crtc_reg.ver_sync_start.reg_num;
1917                                 reg = iga1_crtc_reg.ver_sync_start.reg;
1918                                 break;
1919                         case V_SYNC_END_INDEX:
1920                                 reg_value =
1921                                     IGA1_VER_SYNC_END_FORMULA
1922                                     (device_timing.ver_sync_start,
1923                                      device_timing.ver_sync_end);
1924                                 viafb_load_reg_num =
1925                                     iga1_crtc_reg.ver_sync_end.reg_num;
1926                                 reg = iga1_crtc_reg.ver_sync_end.reg;
1927                                 break;
1928
1929                         }
1930                 }
1931
1932                 if (set_iga == IGA2) {
1933                         switch (i) {
1934                         case H_TOTAL_INDEX:
1935                                 reg_value =
1936                                     IGA2_HOR_TOTAL_FORMULA(device_timing.
1937                                                            hor_total);
1938                                 viafb_load_reg_num =
1939                                         iga2_crtc_reg.hor_total.reg_num;
1940                                 reg = iga2_crtc_reg.hor_total.reg;
1941                                 break;
1942                         case H_ADDR_INDEX:
1943                                 reg_value =
1944                                     IGA2_HOR_ADDR_FORMULA(device_timing.
1945                                                           hor_addr);
1946                                 viafb_load_reg_num =
1947                                         iga2_crtc_reg.hor_addr.reg_num;
1948                                 reg = iga2_crtc_reg.hor_addr.reg;
1949                                 break;
1950                         case H_BLANK_START_INDEX:
1951                                 reg_value =
1952                                     IGA2_HOR_BLANK_START_FORMULA
1953                                     (device_timing.hor_blank_start);
1954                                 viafb_load_reg_num =
1955                                     iga2_crtc_reg.hor_blank_start.reg_num;
1956                                 reg = iga2_crtc_reg.hor_blank_start.reg;
1957                                 break;
1958                         case H_BLANK_END_INDEX:
1959                                 reg_value =
1960                                     IGA2_HOR_BLANK_END_FORMULA
1961                                     (device_timing.hor_blank_start,
1962                                      device_timing.hor_blank_end);
1963                                 viafb_load_reg_num =
1964                                     iga2_crtc_reg.hor_blank_end.reg_num;
1965                                 reg = iga2_crtc_reg.hor_blank_end.reg;
1966                                 break;
1967                         case H_SYNC_START_INDEX:
1968                                 reg_value =
1969                                     IGA2_HOR_SYNC_START_FORMULA
1970                                     (device_timing.hor_sync_start);
1971                                 if (UNICHROME_CN700 <=
1972                                         viaparinfo->chip_info->gfx_chip_name)
1973                                         viafb_load_reg_num =
1974                                             iga2_crtc_reg.hor_sync_start.
1975                                             reg_num;
1976                                 else
1977                                         viafb_load_reg_num = 3;
1978                                 reg = iga2_crtc_reg.hor_sync_start.reg;
1979                                 break;
1980                         case H_SYNC_END_INDEX:
1981                                 reg_value =
1982                                     IGA2_HOR_SYNC_END_FORMULA
1983                                     (device_timing.hor_sync_start,
1984                                      device_timing.hor_sync_end);
1985                                 viafb_load_reg_num =
1986                                     iga2_crtc_reg.hor_sync_end.reg_num;
1987                                 reg = iga2_crtc_reg.hor_sync_end.reg;
1988                                 break;
1989                         case V_TOTAL_INDEX:
1990                                 reg_value =
1991                                     IGA2_VER_TOTAL_FORMULA(device_timing.
1992                                                            ver_total);
1993                                 viafb_load_reg_num =
1994                                         iga2_crtc_reg.ver_total.reg_num;
1995                                 reg = iga2_crtc_reg.ver_total.reg;
1996                                 break;
1997                         case V_ADDR_INDEX:
1998                                 reg_value =
1999                                     IGA2_VER_ADDR_FORMULA(device_timing.
2000                                                           ver_addr);
2001                                 viafb_load_reg_num =
2002                                         iga2_crtc_reg.ver_addr.reg_num;
2003                                 reg = iga2_crtc_reg.ver_addr.reg;
2004                                 break;
2005                         case V_BLANK_START_INDEX:
2006                                 reg_value =
2007                                     IGA2_VER_BLANK_START_FORMULA
2008                                     (device_timing.ver_blank_start);
2009                                 viafb_load_reg_num =
2010                                     iga2_crtc_reg.ver_blank_start.reg_num;
2011                                 reg = iga2_crtc_reg.ver_blank_start.reg;
2012                                 break;
2013                         case V_BLANK_END_INDEX:
2014                                 reg_value =
2015                                     IGA2_VER_BLANK_END_FORMULA
2016                                     (device_timing.ver_blank_start,
2017                                      device_timing.ver_blank_end);
2018                                 viafb_load_reg_num =
2019                                     iga2_crtc_reg.ver_blank_end.reg_num;
2020                                 reg = iga2_crtc_reg.ver_blank_end.reg;
2021                                 break;
2022                         case V_SYNC_START_INDEX:
2023                                 reg_value =
2024                                     IGA2_VER_SYNC_START_FORMULA
2025                                     (device_timing.ver_sync_start);
2026                                 viafb_load_reg_num =
2027                                     iga2_crtc_reg.ver_sync_start.reg_num;
2028                                 reg = iga2_crtc_reg.ver_sync_start.reg;
2029                                 break;
2030                         case V_SYNC_END_INDEX:
2031                                 reg_value =
2032                                     IGA2_VER_SYNC_END_FORMULA
2033                                     (device_timing.ver_sync_start,
2034                                      device_timing.ver_sync_end);
2035                                 viafb_load_reg_num =
2036                                     iga2_crtc_reg.ver_sync_end.reg_num;
2037                                 reg = iga2_crtc_reg.ver_sync_end.reg;
2038                                 break;
2039
2040                         }
2041                 }
2042                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
2043         }
2044
2045         viafb_lock_crt();
2046 }
2047
2048 void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
2049         struct VideoModeTable *video_mode, int bpp_byte, int set_iga)
2050 {
2051         struct display_timing crt_reg;
2052         int i;
2053         int index = 0;
2054         int h_addr, v_addr;
2055         u32 pll_D_N;
2056
2057         for (i = 0; i < video_mode->mode_array; i++) {
2058                 index = i;
2059
2060                 if (crt_table[i].refresh_rate == viaparinfo->
2061                         crt_setting_info->refresh_rate)
2062                         break;
2063         }
2064
2065         crt_reg = crt_table[index].crtc;
2066
2067         /* Mode 640x480 has border, but LCD/DFP didn't have border. */
2068         /* So we would delete border. */
2069         if ((viafb_LCD_ON | viafb_DVI_ON)
2070             && video_mode->crtc[0].crtc.hor_addr == 640
2071             && video_mode->crtc[0].crtc.ver_addr == 480
2072             && viaparinfo->crt_setting_info->refresh_rate == 60) {
2073                 /* The border is 8 pixels. */
2074                 crt_reg.hor_blank_start = crt_reg.hor_blank_start - 8;
2075
2076                 /* Blanking time should add left and right borders. */
2077                 crt_reg.hor_blank_end = crt_reg.hor_blank_end + 16;
2078         }
2079
2080         h_addr = crt_reg.hor_addr;
2081         v_addr = crt_reg.ver_addr;
2082         if (set_iga == IGA1) {
2083                 viafb_unlock_crt();
2084                 viafb_write_reg(CR09, VIACR, 0x00);     /*initial CR09=0 */
2085                 viafb_write_reg_mask(CR11, VIACR, 0x00, BIT4 + BIT5 + BIT6);
2086                 viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
2087         }
2088
2089         switch (set_iga) {
2090         case IGA1:
2091                 viafb_load_crtc_timing(crt_reg, IGA1);
2092                 break;
2093         case IGA2:
2094                 viafb_load_crtc_timing(crt_reg, IGA2);
2095                 break;
2096         }
2097
2098         load_fix_bit_crtc_reg();
2099         viafb_lock_crt();
2100         viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
2101         viafb_load_fetch_count_reg(h_addr, bpp_byte, set_iga);
2102
2103         /* load FIFO */
2104         if ((viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266)
2105             && (viaparinfo->chip_info->gfx_chip_name != UNICHROME_K400))
2106                 viafb_load_FIFO_reg(set_iga, h_addr, v_addr);
2107
2108         pll_D_N = viafb_get_clk_value(crt_table[index].clk);
2109         DEBUG_MSG(KERN_INFO "PLL=%x", pll_D_N);
2110         viafb_set_vclock(pll_D_N, set_iga);
2111
2112 }
2113
2114 void __devinit viafb_init_chip_info(int chip_type)
2115 {
2116         init_gfx_chip_info(chip_type);
2117         init_tmds_chip_info();
2118         init_lvds_chip_info();
2119
2120         viaparinfo->crt_setting_info->iga_path = IGA1;
2121         viaparinfo->crt_setting_info->refresh_rate = viafb_refresh;
2122
2123         /*Set IGA path for each device */
2124         viafb_set_iga_path();
2125
2126         viaparinfo->lvds_setting_info->display_method = viafb_lcd_dsp_method;
2127         viaparinfo->lvds_setting_info->lcd_mode = viafb_lcd_mode;
2128         viaparinfo->lvds_setting_info2->display_method =
2129                 viaparinfo->lvds_setting_info->display_method;
2130         viaparinfo->lvds_setting_info2->lcd_mode =
2131                 viaparinfo->lvds_setting_info->lcd_mode;
2132 }
2133
2134 void viafb_update_device_setting(int hres, int vres,
2135         int bpp, int vmode_refresh, int flag)
2136 {
2137         if (flag == 0) {
2138                 viaparinfo->crt_setting_info->refresh_rate =
2139                         vmode_refresh;
2140
2141                 viaparinfo->tmds_setting_info->h_active = hres;
2142                 viaparinfo->tmds_setting_info->v_active = vres;
2143
2144                 viaparinfo->lvds_setting_info->h_active = hres;
2145                 viaparinfo->lvds_setting_info->v_active = vres;
2146                 viaparinfo->lvds_setting_info->bpp = bpp;
2147                 viaparinfo->lvds_setting_info2->h_active = hres;
2148                 viaparinfo->lvds_setting_info2->v_active = vres;
2149                 viaparinfo->lvds_setting_info2->bpp = bpp;
2150         } else {
2151
2152                 if (viaparinfo->tmds_setting_info->iga_path == IGA2) {
2153                         viaparinfo->tmds_setting_info->h_active = hres;
2154                         viaparinfo->tmds_setting_info->v_active = vres;
2155                 }
2156
2157                 if (viaparinfo->lvds_setting_info->iga_path == IGA2) {
2158                         viaparinfo->lvds_setting_info->h_active = hres;
2159                         viaparinfo->lvds_setting_info->v_active = vres;
2160                         viaparinfo->lvds_setting_info->bpp = bpp;
2161                 }
2162                 if (IGA2 == viaparinfo->lvds_setting_info2->iga_path) {
2163                         viaparinfo->lvds_setting_info2->h_active = hres;
2164                         viaparinfo->lvds_setting_info2->v_active = vres;
2165                         viaparinfo->lvds_setting_info2->bpp = bpp;
2166                 }
2167         }
2168 }
2169
2170 static void __devinit init_gfx_chip_info(int chip_type)
2171 {
2172         u8 tmp;
2173
2174         viaparinfo->chip_info->gfx_chip_name = chip_type;
2175
2176         /* Check revision of CLE266 Chip */
2177         if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
2178                 /* CR4F only define in CLE266.CX chip */
2179                 tmp = viafb_read_reg(VIACR, CR4F);
2180                 viafb_write_reg(CR4F, VIACR, 0x55);
2181                 if (viafb_read_reg(VIACR, CR4F) != 0x55)
2182                         viaparinfo->chip_info->gfx_chip_revision =
2183                         CLE266_REVISION_AX;
2184                 else
2185                         viaparinfo->chip_info->gfx_chip_revision =
2186                         CLE266_REVISION_CX;
2187                 /* restore orignal CR4F value */
2188                 viafb_write_reg(CR4F, VIACR, tmp);
2189         }
2190
2191         if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
2192                 tmp = viafb_read_reg(VIASR, SR43);
2193                 DEBUG_MSG(KERN_INFO "SR43:%X\n", tmp);
2194                 if (tmp & 0x02) {
2195                         viaparinfo->chip_info->gfx_chip_revision =
2196                                 CX700_REVISION_700M2;
2197                 } else if (tmp & 0x40) {
2198                         viaparinfo->chip_info->gfx_chip_revision =
2199                                 CX700_REVISION_700M;
2200                 } else {
2201                         viaparinfo->chip_info->gfx_chip_revision =
2202                                 CX700_REVISION_700;
2203                 }
2204         }
2205
2206         /* Determine which 2D engine we have */
2207         switch (viaparinfo->chip_info->gfx_chip_name) {
2208         case UNICHROME_VX800:
2209         case UNICHROME_VX855:
2210         case UNICHROME_VX900:
2211                 viaparinfo->chip_info->twod_engine = VIA_2D_ENG_M1;
2212                 break;
2213         case UNICHROME_K8M890:
2214         case UNICHROME_P4M900:
2215                 viaparinfo->chip_info->twod_engine = VIA_2D_ENG_H5;
2216                 break;
2217         default:
2218                 viaparinfo->chip_info->twod_engine = VIA_2D_ENG_H2;
2219                 break;
2220         }
2221 }
2222
2223 static void __devinit init_tmds_chip_info(void)
2224 {
2225         viafb_tmds_trasmitter_identify();
2226
2227         if (INTERFACE_NONE == viaparinfo->chip_info->tmds_chip_info.
2228                 output_interface) {
2229                 switch (viaparinfo->chip_info->gfx_chip_name) {
2230                 case UNICHROME_CX700:
2231                         {
2232                                 /* we should check support by hardware layout.*/
2233                                 if ((viafb_display_hardware_layout ==
2234                                      HW_LAYOUT_DVI_ONLY)
2235                                     || (viafb_display_hardware_layout ==
2236                                         HW_LAYOUT_LCD_DVI)) {
2237                                         viaparinfo->chip_info->tmds_chip_info.
2238                                             output_interface = INTERFACE_TMDS;
2239                                 } else {
2240                                         viaparinfo->chip_info->tmds_chip_info.
2241                                                 output_interface =
2242                                                 INTERFACE_NONE;
2243                                 }
2244                                 break;
2245                         }
2246                 case UNICHROME_K8M890:
2247                 case UNICHROME_P4M900:
2248                 case UNICHROME_P4M890:
2249                         /* TMDS on PCIE, we set DFPLOW as default. */
2250                         viaparinfo->chip_info->tmds_chip_info.output_interface =
2251                             INTERFACE_DFP_LOW;
2252                         break;
2253                 default:
2254                         {
2255                                 /* set DVP1 default for DVI */
2256                                 viaparinfo->chip_info->tmds_chip_info
2257                                 .output_interface = INTERFACE_DVP1;
2258                         }
2259                 }
2260         }
2261
2262         DEBUG_MSG(KERN_INFO "TMDS Chip = %d\n",
2263                   viaparinfo->chip_info->tmds_chip_info.tmds_chip_name);
2264         viafb_init_dvi_size(&viaparinfo->shared->chip_info.tmds_chip_info,
2265                 &viaparinfo->shared->tmds_setting_info);
2266 }
2267
2268 static void __devinit init_lvds_chip_info(void)
2269 {
2270         viafb_lvds_trasmitter_identify();
2271         viafb_init_lcd_size();
2272         viafb_init_lvds_output_interface(&viaparinfo->chip_info->lvds_chip_info,
2273                                    viaparinfo->lvds_setting_info);
2274         if (viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name) {
2275                 viafb_init_lvds_output_interface(&viaparinfo->chip_info->
2276                         lvds_chip_info2, viaparinfo->lvds_setting_info2);
2277         }
2278         /*If CX700,two singel LCD, we need to reassign
2279            LCD interface to different LVDS port */
2280         if ((UNICHROME_CX700 == viaparinfo->chip_info->gfx_chip_name)
2281             && (HW_LAYOUT_LCD1_LCD2 == viafb_display_hardware_layout)) {
2282                 if ((INTEGRATED_LVDS == viaparinfo->chip_info->lvds_chip_info.
2283                         lvds_chip_name) && (INTEGRATED_LVDS ==
2284                         viaparinfo->chip_info->
2285                         lvds_chip_info2.lvds_chip_name)) {
2286                         viaparinfo->chip_info->lvds_chip_info.output_interface =
2287                                 INTERFACE_LVDS0;
2288                         viaparinfo->chip_info->lvds_chip_info2.
2289                                 output_interface =
2290                             INTERFACE_LVDS1;
2291                 }
2292         }
2293
2294         DEBUG_MSG(KERN_INFO "LVDS Chip = %d\n",
2295                   viaparinfo->chip_info->lvds_chip_info.lvds_chip_name);
2296         DEBUG_MSG(KERN_INFO "LVDS1 output_interface = %d\n",
2297                   viaparinfo->chip_info->lvds_chip_info.output_interface);
2298         DEBUG_MSG(KERN_INFO "LVDS2 output_interface = %d\n",
2299                   viaparinfo->chip_info->lvds_chip_info.output_interface);
2300 }
2301
2302 void __devinit viafb_init_dac(int set_iga)
2303 {
2304         int i;
2305         u8 tmp;
2306
2307         if (set_iga == IGA1) {
2308                 /* access Primary Display's LUT */
2309                 viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0);
2310                 /* turn off LCK */
2311                 viafb_write_reg_mask(SR1B, VIASR, 0x00, BIT7 + BIT6);
2312                 for (i = 0; i < 256; i++) {
2313                         write_dac_reg(i, palLUT_table[i].red,
2314                                       palLUT_table[i].green,
2315                                       palLUT_table[i].blue);
2316                 }
2317                 /* turn on LCK */
2318                 viafb_write_reg_mask(SR1B, VIASR, 0xC0, BIT7 + BIT6);
2319         } else {
2320                 tmp = viafb_read_reg(VIACR, CR6A);
2321                 /* access Secondary Display's LUT */
2322                 viafb_write_reg_mask(CR6A, VIACR, 0x40, BIT6);
2323                 viafb_write_reg_mask(SR1A, VIASR, 0x01, BIT0);
2324                 for (i = 0; i < 256; i++) {
2325                         write_dac_reg(i, palLUT_table[i].red,
2326                                       palLUT_table[i].green,
2327                                       palLUT_table[i].blue);
2328                 }
2329                 /* set IGA1 DAC for default */
2330                 viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0);
2331                 viafb_write_reg(CR6A, VIACR, tmp);
2332         }
2333 }
2334
2335 static void device_screen_off(void)
2336 {
2337         /* turn off CRT screen (IGA1) */
2338         viafb_write_reg_mask(SR01, VIASR, 0x20, BIT5);
2339 }
2340
2341 static void device_screen_on(void)
2342 {
2343         /* turn on CRT screen (IGA1) */
2344         viafb_write_reg_mask(SR01, VIASR, 0x00, BIT5);
2345 }
2346
2347 static void set_display_channel(void)
2348 {
2349         /*If viafb_LCD2_ON, on cx700, internal lvds's information
2350         is keeped on lvds_setting_info2 */
2351         if (viafb_LCD2_ON &&
2352                 viaparinfo->lvds_setting_info2->device_lcd_dualedge) {
2353                 /* For dual channel LCD: */
2354                 /* Set to Dual LVDS channel. */
2355                 viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);
2356         } else if (viafb_LCD_ON && viafb_DVI_ON) {
2357                 /* For LCD+DFP: */
2358                 /* Set to LVDS1 + TMDS channel. */
2359                 viafb_write_reg_mask(CRD2, VIACR, 0x10, BIT4 + BIT5);
2360         } else if (viafb_DVI_ON) {
2361                 /* Set to single TMDS channel. */
2362                 viafb_write_reg_mask(CRD2, VIACR, 0x30, BIT4 + BIT5);
2363         } else if (viafb_LCD_ON) {
2364                 if (viaparinfo->lvds_setting_info->device_lcd_dualedge) {
2365                         /* For dual channel LCD: */
2366                         /* Set to Dual LVDS channel. */
2367                         viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);
2368                 } else {
2369                         /* Set to LVDS0 + LVDS1 channel. */
2370                         viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT4 + BIT5);
2371                 }
2372         }
2373 }
2374
2375 static u8 get_sync(struct fb_info *info)
2376 {
2377         u8 polarity = 0;
2378
2379         if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT))
2380                 polarity |= VIA_HSYNC_NEGATIVE;
2381         if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT))
2382                 polarity |= VIA_VSYNC_NEGATIVE;
2383         return polarity;
2384 }
2385
2386 int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp,
2387         struct VideoModeTable *vmode_tbl1, int video_bpp1)
2388 {
2389         int i, j;
2390         int port;
2391         u32 devices = viaparinfo->shared->iga1_devices
2392                 | viaparinfo->shared->iga2_devices;
2393         u8 value, index, mask;
2394         struct crt_mode_table *crt_timing;
2395         struct crt_mode_table *crt_timing1 = NULL;
2396
2397         device_screen_off();
2398         crt_timing = vmode_tbl->crtc;
2399
2400         if (viafb_SAMM_ON == 1) {
2401                 crt_timing1 = vmode_tbl1->crtc;
2402         }
2403
2404         inb(VIAStatus);
2405         outb(0x00, VIAAR);
2406
2407         /* Write Common Setting for Video Mode */
2408         switch (viaparinfo->chip_info->gfx_chip_name) {
2409         case UNICHROME_CLE266:
2410                 viafb_write_regx(CLE266_ModeXregs, NUM_TOTAL_CLE266_ModeXregs);
2411                 break;
2412
2413         case UNICHROME_K400:
2414                 viafb_write_regx(KM400_ModeXregs, NUM_TOTAL_KM400_ModeXregs);
2415                 break;
2416
2417         case UNICHROME_K800:
2418         case UNICHROME_PM800:
2419                 viafb_write_regx(CN400_ModeXregs, NUM_TOTAL_CN400_ModeXregs);
2420                 break;
2421
2422         case UNICHROME_CN700:
2423         case UNICHROME_K8M890:
2424         case UNICHROME_P4M890:
2425         case UNICHROME_P4M900:
2426                 viafb_write_regx(CN700_ModeXregs, NUM_TOTAL_CN700_ModeXregs);
2427                 break;
2428
2429         case UNICHROME_CX700:
2430         case UNICHROME_VX800:
2431                 viafb_write_regx(CX700_ModeXregs, NUM_TOTAL_CX700_ModeXregs);
2432                 break;
2433
2434         case UNICHROME_VX855:
2435         case UNICHROME_VX900:
2436                 viafb_write_regx(VX855_ModeXregs, NUM_TOTAL_VX855_ModeXregs);
2437                 break;
2438         }
2439
2440         viafb_write_regx(scaling_parameters, ARRAY_SIZE(scaling_parameters));
2441         device_off();
2442         via_set_state(devices, VIA_STATE_OFF);
2443
2444         /* Fill VPIT Parameters */
2445         /* Write Misc Register */
2446         outb(VPIT.Misc, VIA_MISC_REG_WRITE);
2447
2448         /* Write Sequencer */
2449         for (i = 1; i <= StdSR; i++)
2450                 via_write_reg(VIASR, i, VPIT.SR[i - 1]);
2451
2452         viafb_write_reg_mask(0x15, VIASR, 0xA2, 0xA2);
2453
2454         /* Write CRTC */
2455         viafb_fill_crtc_timing(crt_timing, vmode_tbl, video_bpp / 8, IGA1);
2456
2457         /* Write Graphic Controller */
2458         for (i = 0; i < StdGR; i++)
2459                 via_write_reg(VIAGR, i, VPIT.GR[i]);
2460
2461         /* Write Attribute Controller */
2462         for (i = 0; i < StdAR; i++) {
2463                 inb(VIAStatus);
2464                 outb(i, VIAAR);
2465                 outb(VPIT.AR[i], VIAAR);
2466         }
2467
2468         inb(VIAStatus);
2469         outb(0x20, VIAAR);
2470
2471         /* Update Patch Register */
2472
2473         if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266
2474             || viaparinfo->chip_info->gfx_chip_name == UNICHROME_K400)
2475             && vmode_tbl->crtc[0].crtc.hor_addr == 1024
2476             && vmode_tbl->crtc[0].crtc.ver_addr == 768) {
2477                 for (j = 0; j < res_patch_table[0].table_length; j++) {
2478                         index = res_patch_table[0].io_reg_table[j].index;
2479                         port = res_patch_table[0].io_reg_table[j].port;
2480                         value = res_patch_table[0].io_reg_table[j].value;
2481                         mask = res_patch_table[0].io_reg_table[j].mask;
2482                         viafb_write_reg_mask(index, port, value, mask);
2483                 }
2484         }
2485
2486         via_set_primary_pitch(viafbinfo->fix.line_length);
2487         via_set_secondary_pitch(viafb_dual_fb ? viafbinfo1->fix.line_length
2488                 : viafbinfo->fix.line_length);
2489         via_set_primary_color_depth(viaparinfo->depth);
2490         via_set_secondary_color_depth(viafb_dual_fb ? viaparinfo1->depth
2491                 : viaparinfo->depth);
2492         via_set_source(viaparinfo->shared->iga1_devices, IGA1);
2493         via_set_source(viaparinfo->shared->iga2_devices, IGA2);
2494         if (viaparinfo->shared->iga2_devices)
2495                 enable_second_display_channel();
2496         else
2497                 disable_second_display_channel();
2498
2499         /* Update Refresh Rate Setting */
2500
2501         /* Clear On Screen */
2502
2503         /* CRT set mode */
2504         if (viafb_CRT_ON) {
2505                 if (viafb_SAMM_ON && (viaparinfo->crt_setting_info->iga_path ==
2506                         IGA2)) {
2507                         viafb_fill_crtc_timing(crt_timing1, vmode_tbl1,
2508                                 video_bpp1 / 8,
2509                                 viaparinfo->crt_setting_info->iga_path);
2510                 } else {
2511                         viafb_fill_crtc_timing(crt_timing, vmode_tbl,
2512                                 video_bpp / 8,
2513                                 viaparinfo->crt_setting_info->iga_path);
2514                 }
2515
2516                 /* Patch if set_hres is not 8 alignment (1366) to viafb_setmode
2517                 to 8 alignment (1368),there is several pixels (2 pixels)
2518                 on right side of screen. */
2519                 if (vmode_tbl->crtc[0].crtc.hor_addr % 8) {
2520                         viafb_unlock_crt();
2521                         viafb_write_reg(CR02, VIACR,
2522                                 viafb_read_reg(VIACR, CR02) - 1);
2523                         viafb_lock_crt();
2524                 }
2525         }
2526
2527         if (viafb_DVI_ON) {
2528                 if (viafb_SAMM_ON &&
2529                         (viaparinfo->tmds_setting_info->iga_path == IGA2)) {
2530                         viafb_dvi_set_mode(viafb_get_mode
2531                                      (viaparinfo->tmds_setting_info->h_active,
2532                                       viaparinfo->tmds_setting_info->
2533                                       v_active),
2534                                      video_bpp1, viaparinfo->
2535                                      tmds_setting_info->iga_path);
2536                 } else {
2537                         viafb_dvi_set_mode(viafb_get_mode
2538                                      (viaparinfo->tmds_setting_info->h_active,
2539                                       viaparinfo->
2540                                       tmds_setting_info->v_active),
2541                                      video_bpp, viaparinfo->
2542                                      tmds_setting_info->iga_path);
2543                 }
2544         }
2545
2546         if (viafb_LCD_ON) {
2547                 if (viafb_SAMM_ON &&
2548                         (viaparinfo->lvds_setting_info->iga_path == IGA2)) {
2549                         viaparinfo->lvds_setting_info->bpp = video_bpp1;
2550                         viafb_lcd_set_mode(crt_timing1, viaparinfo->
2551                                 lvds_setting_info,
2552                                      &viaparinfo->chip_info->lvds_chip_info);
2553                 } else {
2554                         /* IGA1 doesn't have LCD scaling, so set it center. */
2555                         if (viaparinfo->lvds_setting_info->iga_path == IGA1) {
2556                                 viaparinfo->lvds_setting_info->display_method =
2557                                     LCD_CENTERING;
2558                         }
2559                         viaparinfo->lvds_setting_info->bpp = video_bpp;
2560                         viafb_lcd_set_mode(crt_timing, viaparinfo->
2561                                 lvds_setting_info,
2562                                      &viaparinfo->chip_info->lvds_chip_info);
2563                 }
2564         }
2565         if (viafb_LCD2_ON) {
2566                 if (viafb_SAMM_ON &&
2567                         (viaparinfo->lvds_setting_info2->iga_path == IGA2)) {
2568                         viaparinfo->lvds_setting_info2->bpp = video_bpp1;
2569                         viafb_lcd_set_mode(crt_timing1, viaparinfo->
2570                                 lvds_setting_info2,
2571                                      &viaparinfo->chip_info->lvds_chip_info2);
2572                 } else {
2573                         /* IGA1 doesn't have LCD scaling, so set it center. */
2574                         if (viaparinfo->lvds_setting_info2->iga_path == IGA1) {
2575                                 viaparinfo->lvds_setting_info2->display_method =
2576                                     LCD_CENTERING;
2577                         }
2578                         viaparinfo->lvds_setting_info2->bpp = video_bpp;
2579                         viafb_lcd_set_mode(crt_timing, viaparinfo->
2580                                 lvds_setting_info2,
2581                                      &viaparinfo->chip_info->lvds_chip_info2);
2582                 }
2583         }
2584
2585         if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700)
2586             && (viafb_LCD_ON || viafb_DVI_ON))
2587                 set_display_channel();
2588
2589         /* If set mode normally, save resolution information for hot-plug . */
2590         if (!viafb_hotplug) {
2591                 viafb_hotplug_Xres = vmode_tbl->crtc[0].crtc.hor_addr;
2592                 viafb_hotplug_Yres = vmode_tbl->crtc[0].crtc.ver_addr;
2593                 viafb_hotplug_bpp = video_bpp;
2594                 viafb_hotplug_refresh = viafb_refresh;
2595
2596                 if (viafb_DVI_ON)
2597                         viafb_DeviceStatus = DVI_Device;
2598                 else
2599                         viafb_DeviceStatus = CRT_Device;
2600         }
2601         device_on();
2602         if (!viafb_dual_fb)
2603                 via_set_sync_polarity(devices, get_sync(viafbinfo));
2604         else {
2605                 via_set_sync_polarity(viaparinfo->shared->iga1_devices,
2606                         get_sync(viafbinfo));
2607                 via_set_sync_polarity(viaparinfo->shared->iga2_devices,
2608                         get_sync(viafbinfo1));
2609         }
2610
2611         via_set_state(devices, VIA_STATE_ON);
2612         device_screen_on();
2613         return 1;
2614 }
2615
2616 int viafb_get_pixclock(int hres, int vres, int vmode_refresh)
2617 {
2618         int i;
2619
2620         for (i = 0; i < NUM_TOTAL_RES_MAP_REFRESH; i++) {
2621                 if ((hres == res_map_refresh_tbl[i].hres)
2622                     && (vres == res_map_refresh_tbl[i].vres)
2623                     && (vmode_refresh == res_map_refresh_tbl[i].vmode_refresh))
2624                         return res_map_refresh_tbl[i].pixclock;
2625         }
2626         return RES_640X480_60HZ_PIXCLOCK;
2627
2628 }
2629
2630 int viafb_get_refresh(int hres, int vres, u32 long_refresh)
2631 {
2632 #define REFRESH_TOLERANCE 3
2633         int i, nearest = -1, diff = REFRESH_TOLERANCE;
2634         for (i = 0; i < NUM_TOTAL_RES_MAP_REFRESH; i++) {
2635                 if ((hres == res_map_refresh_tbl[i].hres)
2636                     && (vres == res_map_refresh_tbl[i].vres)
2637                     && (diff > (abs(long_refresh -
2638                     res_map_refresh_tbl[i].vmode_refresh)))) {
2639                         diff = abs(long_refresh - res_map_refresh_tbl[i].
2640                                 vmode_refresh);
2641                         nearest = i;
2642                 }
2643         }
2644 #undef REFRESH_TOLERANCE
2645         if (nearest > 0)
2646                 return res_map_refresh_tbl[nearest].vmode_refresh;
2647         return 60;
2648 }
2649
2650 static void device_off(void)
2651 {
2652         viafb_dvi_disable();
2653         viafb_lcd_disable();
2654 }
2655
2656 static void device_on(void)
2657 {
2658         if (viafb_DVI_ON == 1)
2659                 viafb_dvi_enable();
2660         if (viafb_LCD_ON == 1)
2661                 viafb_lcd_enable();
2662 }
2663
2664 static void enable_second_display_channel(void)
2665 {
2666         /* to enable second display channel. */
2667         viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6);
2668         viafb_write_reg_mask(CR6A, VIACR, BIT7, BIT7);
2669         viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6);
2670 }
2671
2672 static void disable_second_display_channel(void)
2673 {
2674         /* to disable second display channel. */
2675         viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6);
2676         viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT7);
2677         viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6);
2678 }
2679
2680 void viafb_set_dpa_gfx(int output_interface, struct GFX_DPA_SETTING\
2681                                         *p_gfx_dpa_setting)
2682 {
2683         switch (output_interface) {
2684         case INTERFACE_DVP0:
2685                 {
2686                         /* DVP0 Clock Polarity and Adjust: */
2687                         viafb_write_reg_mask(CR96, VIACR,
2688                                        p_gfx_dpa_setting->DVP0, 0x0F);
2689
2690                         /* DVP0 Clock and Data Pads Driving: */
2691                         viafb_write_reg_mask(SR1E, VIASR,
2692                                        p_gfx_dpa_setting->DVP0ClockDri_S, BIT2);
2693                         viafb_write_reg_mask(SR2A, VIASR,
2694                                        p_gfx_dpa_setting->DVP0ClockDri_S1,
2695                                        BIT4);
2696                         viafb_write_reg_mask(SR1B, VIASR,
2697                                        p_gfx_dpa_setting->DVP0DataDri_S, BIT1);
2698                         viafb_write_reg_mask(SR2A, VIASR,
2699                                        p_gfx_dpa_setting->DVP0DataDri_S1, BIT5);
2700                         break;
2701                 }
2702
2703         case INTERFACE_DVP1:
2704                 {
2705                         /* DVP1 Clock Polarity and Adjust: */
2706                         viafb_write_reg_mask(CR9B, VIACR,
2707                                        p_gfx_dpa_setting->DVP1, 0x0F);
2708
2709                         /* DVP1 Clock and Data Pads Driving: */
2710                         viafb_write_reg_mask(SR65, VIASR,
2711                                        p_gfx_dpa_setting->DVP1Driving, 0x0F);
2712                         break;
2713                 }
2714
2715         case INTERFACE_DFP_HIGH:
2716                 {
2717                         viafb_write_reg_mask(CR97, VIACR,
2718                                        p_gfx_dpa_setting->DFPHigh, 0x0F);
2719                         break;
2720                 }
2721
2722         case INTERFACE_DFP_LOW:
2723                 {
2724                         viafb_write_reg_mask(CR99, VIACR,
2725                                        p_gfx_dpa_setting->DFPLow, 0x0F);
2726                         break;
2727                 }
2728
2729         case INTERFACE_DFP:
2730                 {
2731                         viafb_write_reg_mask(CR97, VIACR,
2732                                        p_gfx_dpa_setting->DFPHigh, 0x0F);
2733                         viafb_write_reg_mask(CR99, VIACR,
2734                                        p_gfx_dpa_setting->DFPLow, 0x0F);
2735                         break;
2736                 }
2737         }
2738 }
2739
2740 /*According var's xres, yres fill var's other timing information*/
2741 void viafb_fill_var_timing_info(struct fb_var_screeninfo *var, int refresh,
2742         struct VideoModeTable *vmode_tbl)
2743 {
2744         struct crt_mode_table *crt_timing = NULL;
2745         struct display_timing crt_reg;
2746         int i = 0, index = 0;
2747         crt_timing = vmode_tbl->crtc;
2748         for (i = 0; i < vmode_tbl->mode_array; i++) {
2749                 index = i;
2750                 if (crt_timing[i].refresh_rate == refresh)
2751                         break;
2752         }
2753
2754         crt_reg = crt_timing[index].crtc;
2755         var->pixclock = viafb_get_pixclock(var->xres, var->yres, refresh);
2756         var->left_margin =
2757             crt_reg.hor_total - (crt_reg.hor_sync_start + crt_reg.hor_sync_end);
2758         var->right_margin = crt_reg.hor_sync_start - crt_reg.hor_addr;
2759         var->hsync_len = crt_reg.hor_sync_end;
2760         var->upper_margin =
2761             crt_reg.ver_total - (crt_reg.ver_sync_start + crt_reg.ver_sync_end);
2762         var->lower_margin = crt_reg.ver_sync_start - crt_reg.ver_addr;
2763         var->vsync_len = crt_reg.ver_sync_end;
2764         var->sync = 0;
2765         if (crt_timing[index].h_sync_polarity == POSITIVE)
2766                 var->sync |= FB_SYNC_HOR_HIGH_ACT;
2767         if (crt_timing[index].v_sync_polarity == POSITIVE)
2768                 var->sync |= FB_SYNC_VERT_HIGH_ACT;
2769 }