drivers/video/via/hw.c

   1 /*
   2  * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
   3  * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
   4
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public
   7  * License as published by the Free Software Foundation;
   8  * either version 2, or (at your option) any later version.
   9
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
  12  * the implied warranty of MERCHANTABILITY or FITNESS FOR
  13  * A PARTICULAR PURPOSE.See the GNU General Public License
  14  * for more details.
  15
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc.,
  19  * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  20  */
  21
  22 #include <linux/via-core.h>
  23 #include "global.h"
  24
  25 static struct pll_map pll_value[] = {
  26         {25175000,
  27                 {99, 7, 3},
  28                 {85, 3, 4},     /* ignoring bit difference: 0x00008000 */
  29                 {141, 5, 4},
  30                 {141, 5, 4} },
  31         {29581000,
  32                 {33, 4, 2},
  33                 {66, 2, 4},     /* ignoring bit difference: 0x00808000 */
  34                 {166, 5, 4},    /* ignoring bit difference: 0x00008000 */
  35                 {165, 5, 4} },
  36         {26880000,
  37                 {15, 4, 1},
  38                 {30, 2, 3},     /* ignoring bit difference: 0x00808000 */
  39                 {150, 5, 4},
  40                 {150, 5, 4} },
  41         {31500000,
  42                 {53, 3, 3},     /* ignoring bit difference: 0x00008000 */
  43                 {141, 4, 4},    /* ignoring bit difference: 0x00008000 */
  44                 {176, 5, 4},
  45                 {176, 5, 4} },
  46         {31728000,
  47                 {31, 7, 1},
  48                 {177, 5, 4},    /* ignoring bit difference: 0x00008000 */
  49                 {177, 5, 4},
  50                 {142, 4, 4} },
  51         {32688000,
  52                 {73, 4, 3},
  53                 {146, 4, 4},    /* ignoring bit difference: 0x00008000 */
  54                 {183, 5, 4},
  55                 {146, 4, 4} },
  56         {36000000,
  57                 {101, 5, 3},    /* ignoring bit difference: 0x00008000 */
  58                 {161, 4, 4},    /* ignoring bit difference: 0x00008000 */
  59                 {202, 5, 4},
  60                 {161, 4, 4} },
  61         {40000000,
  62                 {89, 4, 3},
  63                 {89, 4, 3},     /* ignoring bit difference: 0x00008000 */
  64                 {112, 5, 3},
  65                 {112, 5, 3} },
  66         {41291000,
  67                 {23, 4, 1},
  68                 {69, 3, 3},     /* ignoring bit difference: 0x00008000 */
  69                 {115, 5, 3},
  70                 {115, 5, 3} },
  71         {43163000,
  72                 {121, 5, 3},
  73                 {121, 5, 3},    /* ignoring bit difference: 0x00008000 */
  74                 {121, 5, 3},
  75                 {121, 5, 3} },
  76         {45250000,
  77                 {127, 5, 3},
  78                 {127, 5, 3},    /* ignoring bit difference: 0x00808000 */
  79                 {127, 5, 3},
  80                 {127, 5, 3} },
  81         {46000000,
  82                 {90, 7, 2},
  83                 {103, 4, 3},    /* ignoring bit difference: 0x00008000 */
  84                 {129, 5, 3},
  85                 {103, 4, 3} },
  86         {46996000,
  87                 {105, 4, 3},    /* ignoring bit difference: 0x00008000 */
  88                 {131, 5, 3},    /* ignoring bit difference: 0x00808000 */
  89                 {131, 5, 3},    /* ignoring bit difference: 0x00808000 */
  90                 {105, 4, 3} },
  91         {48000000,
  92                 {67, 20, 0},
  93                 {134, 5, 3},    /* ignoring bit difference: 0x00808000 */
  94                 {134, 5, 3},
  95                 {134, 5, 3} },
  96         {48875000,
  97                 {99, 29, 0},
  98                 {82, 3, 3},     /* ignoring bit difference: 0x00808000 */
  99                 {82, 3, 3},     /* ignoring bit difference: 0x00808000 */
 100                 {137, 5, 3} },
 101         {49500000,
 102                 {83, 6, 2},
 103                 {83, 3, 3},     /* ignoring bit difference: 0x00008000 */
 104                 {138, 5, 3},
 105                 {83, 3, 3} },
 106         {52406000,
 107                 {117, 4, 3},
 108                 {117, 4, 3},    /* ignoring bit difference: 0x00008000 */
 109                 {117, 4, 3},
 110                 {88, 3, 3} },
 111         {52977000,
 112                 {37, 5, 1},
 113                 {148, 5, 3},    /* ignoring bit difference: 0x00808000 */
 114                 {148, 5, 3},
 115                 {148, 5, 3} },
 116         {56250000,
 117                 {55, 7, 1},     /* ignoring bit difference: 0x00008000 */
 118                 {126, 4, 3},    /* ignoring bit difference: 0x00008000 */
 119                 {157, 5, 3},
 120                 {157, 5, 3} },
 121         {57275000,
 122                 {0, 0, 0},
 123                 {2, 2, 0},
 124                 {2, 2, 0},
 125                 {157, 5, 3} },  /* ignoring bit difference: 0x00808000 */
 126         {60466000,
 127                 {76, 9, 1},
 128                 {169, 5, 3},    /* ignoring bit difference: 0x00808000 */
 129                 {169, 5, 3},    /* FIXED: old = {72, 2, 3} */
 130                 {169, 5, 3} },
 131         {61500000,
 132                 {86, 20, 0},
 133                 {172, 5, 3},    /* ignoring bit difference: 0x00808000 */
 134                 {172, 5, 3},
 135                 {172, 5, 3} },
 136         {65000000,
 137                 {109, 6, 2},    /* ignoring bit difference: 0x00008000 */
 138                 {109, 3, 3},    /* ignoring bit difference: 0x00008000 */
 139                 {109, 3, 3},
 140                 {109, 3, 3} },
 141         {65178000,
 142                 {91, 5, 2},
 143                 {182, 5, 3},    /* ignoring bit difference: 0x00808000 */
 144                 {109, 3, 3},
 145                 {182, 5, 3} },
 146         {66750000,
 147                 {75, 4, 2},
 148                 {150, 4, 3},    /* ignoring bit difference: 0x00808000 */
 149                 {150, 4, 3},
 150                 {112, 3, 3} },
 151         {68179000,
 152                 {19, 4, 0},
 153                 {114, 3, 3},    /* ignoring bit difference: 0x00008000 */
 154                 {190, 5, 3},
 155                 {191, 5, 3} },
 156         {69924000,
 157                 {83, 17, 0},
 158                 {195, 5, 3},    /* ignoring bit difference: 0x00808000 */
 159                 {195, 5, 3},
 160                 {195, 5, 3} },
 161         {70159000,
 162                 {98, 20, 0},
 163                 {196, 5, 3},    /* ignoring bit difference: 0x00808000 */
 164                 {196, 5, 3},
 165                 {195, 5, 3} },
 166         {72000000,
 167                 {121, 24, 0},
 168                 {161, 4, 3},    /* ignoring bit difference: 0x00808000 */
 169                 {161, 4, 3},
 170                 {161, 4, 3} },
 171         {78750000,
 172                 {33, 3, 1},
 173                 {66, 3, 2},     /* ignoring bit difference: 0x00008000 */
 174                 {110, 5, 2},
 175                 {110, 5, 2} },
 176         {80136000,
 177                 {28, 5, 0},
 178                 {68, 3, 2},     /* ignoring bit difference: 0x00008000 */
 179                 {112, 5, 2},
 180                 {112, 5, 2} },
 181         {83375000,
 182                 {93, 2, 3},
 183                 {93, 4, 2},     /* ignoring bit difference: 0x00800000 */
 184                 {93, 4, 2},     /* ignoring bit difference: 0x00800000 */
 185                 {117, 5, 2} },
 186         {83950000,
 187                 {41, 7, 0},
 188                 {117, 5, 2},    /* ignoring bit difference: 0x00008000 */
 189                 {117, 5, 2},
 190                 {117, 5, 2} },
 191         {84750000,
 192                 {118, 5, 2},
 193                 {118, 5, 2},    /* ignoring bit difference: 0x00808000 */
 194                 {118, 5, 2},
 195                 {118, 5, 2} },
 196         {85860000,
 197                 {84, 7, 1},
 198                 {120, 5, 2},    /* ignoring bit difference: 0x00808000 */
 199                 {120, 5, 2},
 200                 {118, 5, 2} },
 201         {88750000,
 202                 {31, 5, 0},
 203                 {124, 5, 2},    /* ignoring bit difference: 0x00808000 */
 204                 {174, 7, 2},    /* ignoring bit difference: 0x00808000 */
 205                 {124, 5, 2} },
 206         {94500000,
 207                 {33, 5, 0},
 208                 {132, 5, 2},    /* ignoring bit difference: 0x00008000 */
 209                 {132, 5, 2},
 210                 {132, 5, 2} },
 211         {97750000,
 212                 {82, 6, 1},
 213                 {137, 5, 2},    /* ignoring bit difference: 0x00808000 */
 214                 {137, 5, 2},
 215                 {137, 5, 2} },
 216         {101000000,
 217                 {127, 9, 1},
 218                 {141, 5, 2},    /* ignoring bit difference: 0x00808000 */
 219                 {141, 5, 2},
 220                 {141, 5, 2} },
 221         {106500000,
 222                 {119, 4, 2},
 223                 {119, 4, 2},    /* ignoring bit difference: 0x00808000 */
 224                 {119, 4, 2},
 225                 {149, 5, 2} },
 226         {108000000,
 227                 {121, 4, 2},
 228                 {121, 4, 2},    /* ignoring bit difference: 0x00808000 */
 229                 {151, 5, 2},
 230                 {151, 5, 2} },
 231         {113309000,
 232                 {95, 12, 0},
 233                 {95, 3, 2},     /* ignoring bit difference: 0x00808000 */
 234                 {95, 3, 2},
 235                 {159, 5, 2} },
 236         {118840000,
 237                 {83, 5, 1},
 238                 {166, 5, 2},    /* ignoring bit difference: 0x00808000 */
 239                 {166, 5, 2},
 240                 {166, 5, 2} },
 241         {119000000,
 242                 {108, 13, 0},
 243                 {133, 4, 2},    /* ignoring bit difference: 0x00808000 */
 244                 {133, 4, 2},
 245                 {167, 5, 2} },
 246         {121750000,
 247                 {85, 5, 1},
 248                 {170, 5, 2},    /* ignoring bit difference: 0x00808000 */
 249                 {68, 2, 2},
 250                 {0, 0, 0} },
 251         {125104000,
 252                 {53, 6, 0},     /* ignoring bit difference: 0x00008000 */
 253                 {106, 3, 2},    /* ignoring bit difference: 0x00008000 */
 254                 {175, 5, 2},
 255                 {0, 0, 0} },
 256         {135000000,
 257                 {94, 5, 1},
 258                 {28, 3, 0},     /* ignoring bit difference: 0x00804000 */
 259                 {151, 4, 2},
 260                 {189, 5, 2} },
 261         {136700000,
 262                 {115, 12, 0},
 263                 {191, 5, 2},    /* ignoring bit difference: 0x00808000 */
 264                 {191, 5, 2},
 265                 {191, 5, 2} },
 266         {138400000,
 267                 {87, 9, 0},
 268                 {116, 3, 2},    /* ignoring bit difference: 0x00808000 */
 269                 {116, 3, 2},
 270                 {194, 5, 2} },
 271         {146760000,
 272                 {103, 5, 1},
 273                 {206, 5, 2},    /* ignoring bit difference: 0x00808000 */
 274                 {206, 5, 2},
 275                 {206, 5, 2} },
 276         {153920000,
 277                 {86, 8, 0},
 278                 {86, 4, 1},     /* ignoring bit difference: 0x00808000 */
 279                 {86, 4, 1},
 280                 {86, 4, 1} },   /* FIXED: old = {84, 2, 1} */
 281         {156000000,
 282                 {109, 5, 1},
 283                 {109, 5, 1},    /* ignoring bit difference: 0x00808000 */
 284                 {109, 5, 1},
 285                 {108, 5, 1} },
 286         {157500000,
 287                 {55, 5, 0},     /* ignoring bit difference: 0x00008000 */
 288                 {22, 2, 0},     /* ignoring bit difference: 0x00802000 */
 289                 {110, 5, 1},
 290                 {110, 5, 1} },
 291         {162000000,
 292                 {113, 5, 1},
 293                 {113, 5, 1},    /* ignoring bit difference: 0x00808000 */
 294                 {113, 5, 1},
 295                 {113, 5, 1} },
 296         {187000000,
 297                 {118, 9, 0},
 298                 {131, 5, 1},    /* ignoring bit difference: 0x00808000 */
 299                 {131, 5, 1},
 300                 {131, 5, 1} },
 301         {193295000,
 302                 {108, 8, 0},
 303                 {81, 3, 1},     /* ignoring bit difference: 0x00808000 */
 304                 {135, 5, 1},
 305                 {135, 5, 1} },
 306         {202500000,
 307                 {99, 7, 0},
 308                 {85, 3, 1},     /* ignoring bit difference: 0x00808000 */
 309                 {142, 5, 1},
 310                 {142, 5, 1} },
 311         {204000000,
 312                 {100, 7, 0},
 313                 {143, 5, 1},    /* ignoring bit difference: 0x00808000 */
 314                 {143, 5, 1},
 315                 {143, 5, 1} },
 316         {218500000,
 317                 {92, 6, 0},
 318                 {153, 5, 1},    /* ignoring bit difference: 0x00808000 */
 319                 {153, 5, 1},
 320                 {153, 5, 1} },
 321         {234000000,
 322                 {98, 6, 0},
 323                 {98, 3, 1},     /* ignoring bit difference: 0x00008000 */
 324                 {98, 3, 1},
 325                 {164, 5, 1} },
 326         {267250000,
 327                 {112, 6, 0},
 328                 {112, 3, 1},    /* ignoring bit difference: 0x00808000 */
 329                 {187, 5, 1},
 330                 {187, 5, 1} },
 331         {297500000,
 332                 {102, 5, 0},    /* ignoring bit difference: 0x00008000 */
 333                 {166, 4, 1},    /* ignoring bit difference: 0x00008000 */
 334                 {208, 5, 1},
 335                 {208, 5, 1} },
 336         {74481000,
 337                 {26, 5, 0},
 338                 {125, 3, 3},    /* ignoring bit difference: 0x00808000 */
 339                 {208, 5, 3},
 340                 {209, 5, 3} },
 341         {172798000,
 342                 {121, 5, 1},
 343                 {121, 5, 1},    /* ignoring bit difference: 0x00808000 */
 344                 {121, 5, 1},
 345                 {121, 5, 1} },
 346         {122614000,
 347                 {60, 7, 0},
 348                 {137, 4, 2},    /* ignoring bit difference: 0x00808000 */
 349                 {137, 4, 2},
 350                 {172, 5, 2} },
 351         {74270000,
 352                 {83, 8, 1},
 353                 {208, 5, 3},
 354                 {208, 5, 3},
 355                 {0, 0, 0} },
 356         {148500000,
 357                 {83, 8, 0},
 358                 {208, 5, 2},
 359                 {166, 4, 2},
 360                 {208, 5, 2} }
 361 };
 362
 363 static struct fifo_depth_select display_fifo_depth_reg = {
 364         /* IGA1 FIFO Depth_Select */
 365         {IGA1_FIFO_DEPTH_SELECT_REG_NUM, {{SR17, 0, 7} } },
 366         /* IGA2 FIFO Depth_Select */
 367         {IGA2_FIFO_DEPTH_SELECT_REG_NUM,
 368          {{CR68, 4, 7}, {CR94, 7, 7}, {CR95, 7, 7} } }
 369 };
 370
 371 static struct fifo_threshold_select fifo_threshold_select_reg = {
 372         /* IGA1 FIFO Threshold Select */
 373         {IGA1_FIFO_THRESHOLD_REG_NUM, {{SR16, 0, 5}, {SR16, 7, 7} } },
 374         /* IGA2 FIFO Threshold Select */
 375         {IGA2_FIFO_THRESHOLD_REG_NUM, {{CR68, 0, 3}, {CR95, 4, 6} } }
 376 };
 377
 378 static struct fifo_high_threshold_select fifo_high_threshold_select_reg = {
 379         /* IGA1 FIFO High Threshold Select */
 380         {IGA1_FIFO_HIGH_THRESHOLD_REG_NUM, {{SR18, 0, 5}, {SR18, 7, 7} } },
 381         /* IGA2 FIFO High Threshold Select */
 382         {IGA2_FIFO_HIGH_THRESHOLD_REG_NUM, {{CR92, 0, 3}, {CR95, 0, 2} } }
 383 };
 384
 385 static struct display_queue_expire_num display_queue_expire_num_reg = {
 386         /* IGA1 Display Queue Expire Num */
 387         {IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{SR22, 0, 4} } },
 388         /* IGA2 Display Queue Expire Num */
 389         {IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{CR94, 0, 6} } }
 390 };
 391
 392 /* Definition Fetch Count Registers*/
 393 static struct fetch_count fetch_count_reg = {
 394         /* IGA1 Fetch Count Register */
 395         {IGA1_FETCH_COUNT_REG_NUM, {{SR1C, 0, 7}, {SR1D, 0, 1} } },
 396         /* IGA2 Fetch Count Register */
 397         {IGA2_FETCH_COUNT_REG_NUM, {{CR65, 0, 7}, {CR67, 2, 3} } }
 398 };
 399
 400 static struct iga1_crtc_timing iga1_crtc_reg = {
 401         /* IGA1 Horizontal Total */
 402         {IGA1_HOR_TOTAL_REG_NUM, {{CR00, 0, 7}, {CR36, 3, 3} } },
 403         /* IGA1 Horizontal Addressable Video */
 404         {IGA1_HOR_ADDR_REG_NUM, {{CR01, 0, 7} } },
 405         /* IGA1 Horizontal Blank Start */
 406         {IGA1_HOR_BLANK_START_REG_NUM, {{CR02, 0, 7} } },
 407         /* IGA1 Horizontal Blank End */
 408         {IGA1_HOR_BLANK_END_REG_NUM,
 409          {{CR03, 0, 4}, {CR05, 7, 7}, {CR33, 5, 5} } },
 410         /* IGA1 Horizontal Sync Start */
 411         {IGA1_HOR_SYNC_START_REG_NUM, {{CR04, 0, 7}, {CR33, 4, 4} } },
 412         /* IGA1 Horizontal Sync End */
 413         {IGA1_HOR_SYNC_END_REG_NUM, {{CR05, 0, 4} } },
 414         /* IGA1 Vertical Total */
 415         {IGA1_VER_TOTAL_REG_NUM,
 416          {{CR06, 0, 7}, {CR07, 0, 0}, {CR07, 5, 5}, {CR35, 0, 0} } },
 417         /* IGA1 Vertical Addressable Video */
 418         {IGA1_VER_ADDR_REG_NUM,
 419          {{CR12, 0, 7}, {CR07, 1, 1}, {CR07, 6, 6}, {CR35, 2, 2} } },
 420         /* IGA1 Vertical Blank Start */
 421         {IGA1_VER_BLANK_START_REG_NUM,
 422          {{CR15, 0, 7}, {CR07, 3, 3}, {CR09, 5, 5}, {CR35, 3, 3} } },
 423         /* IGA1 Vertical Blank End */
 424         {IGA1_VER_BLANK_END_REG_NUM, {{CR16, 0, 7} } },
 425         /* IGA1 Vertical Sync Start */
 426         {IGA1_VER_SYNC_START_REG_NUM,
 427          {{CR10, 0, 7}, {CR07, 2, 2}, {CR07, 7, 7}, {CR35, 1, 1} } },
 428         /* IGA1 Vertical Sync End */
 429         {IGA1_VER_SYNC_END_REG_NUM, {{CR11, 0, 3} } }
 430 };
 431
 432 static struct iga2_crtc_timing iga2_crtc_reg = {
 433         /* IGA2 Horizontal Total */
 434         {IGA2_HOR_TOTAL_REG_NUM, {{CR50, 0, 7}, {CR55, 0, 3} } },
 435         /* IGA2 Horizontal Addressable Video */
 436         {IGA2_HOR_ADDR_REG_NUM, {{CR51, 0, 7}, {CR55, 4, 6} } },
 437         /* IGA2 Horizontal Blank Start */
 438         {IGA2_HOR_BLANK_START_REG_NUM, {{CR52, 0, 7}, {CR54, 0, 2} } },
 439         /* IGA2 Horizontal Blank End */
 440         {IGA2_HOR_BLANK_END_REG_NUM,
 441          {{CR53, 0, 7}, {CR54, 3, 5}, {CR5D, 6, 6} } },
 442         /* IGA2 Horizontal Sync Start */
 443         {IGA2_HOR_SYNC_START_REG_NUM,
 444          {{CR56, 0, 7}, {CR54, 6, 7}, {CR5C, 7, 7}, {CR5D, 7, 7} } },
 445         /* IGA2 Horizontal Sync End */
 446         {IGA2_HOR_SYNC_END_REG_NUM, {{CR57, 0, 7}, {CR5C, 6, 6} } },
 447         /* IGA2 Vertical Total */
 448         {IGA2_VER_TOTAL_REG_NUM, {{CR58, 0, 7}, {CR5D, 0, 2} } },
 449         /* IGA2 Vertical Addressable Video */
 450         {IGA2_VER_ADDR_REG_NUM, {{CR59, 0, 7}, {CR5D, 3, 5} } },
 451         /* IGA2 Vertical Blank Start */
 452         {IGA2_VER_BLANK_START_REG_NUM, {{CR5A, 0, 7}, {CR5C, 0, 2} } },
 453         /* IGA2 Vertical Blank End */
 454         {IGA2_VER_BLANK_END_REG_NUM, {{CR5B, 0, 7}, {CR5C, 3, 5} } },
 455         /* IGA2 Vertical Sync Start */
 456         {IGA2_VER_SYNC_START_REG_NUM, {{CR5E, 0, 7}, {CR5F, 5, 7} } },
 457         /* IGA2 Vertical Sync End */
 458         {IGA2_VER_SYNC_END_REG_NUM, {{CR5F, 0, 4} } }
 459 };
 460
 461 static struct rgbLUT palLUT_table[] = {
 462         /* {R,G,B} */
 463         /* Index 0x00~0x03 */
 464         {0x00, 0x00, 0x00}, {0x00, 0x00, 0x2A}, {0x00, 0x2A, 0x00}, {0x00,
 465                                                                      0x2A,
 466                                                                      0x2A},
 467         /* Index 0x04~0x07 */
 468         {0x2A, 0x00, 0x00}, {0x2A, 0x00, 0x2A}, {0x2A, 0x15, 0x00}, {0x2A,
 469                                                                      0x2A,
 470                                                                      0x2A},
 471         /* Index 0x08~0x0B */
 472         {0x15, 0x15, 0x15}, {0x15, 0x15, 0x3F}, {0x15, 0x3F, 0x15}, {0x15,
 473                                                                      0x3F,
 474                                                                      0x3F},
 475         /* Index 0x0C~0x0F */
 476         {0x3F, 0x15, 0x15}, {0x3F, 0x15, 0x3F}, {0x3F, 0x3F, 0x15}, {0x3F,
 477                                                                      0x3F,
 478                                                                      0x3F},
 479         /* Index 0x10~0x13 */
 480         {0x00, 0x00, 0x00}, {0x05, 0x05, 0x05}, {0x08, 0x08, 0x08}, {0x0B,
 481                                                                      0x0B,
 482                                                                      0x0B},
 483         /* Index 0x14~0x17 */
 484         {0x0E, 0x0E, 0x0E}, {0x11, 0x11, 0x11}, {0x14, 0x14, 0x14}, {0x18,
 485                                                                      0x18,
 486                                                                      0x18},
 487         /* Index 0x18~0x1B */
 488         {0x1C, 0x1C, 0x1C}, {0x20, 0x20, 0x20}, {0x24, 0x24, 0x24}, {0x28,
 489                                                                      0x28,
 490                                                                      0x28},
 491         /* Index 0x1C~0x1F */
 492         {0x2D, 0x2D, 0x2D}, {0x32, 0x32, 0x32}, {0x38, 0x38, 0x38}, {0x3F,
 493                                                                      0x3F,
 494                                                                      0x3F},
 495         /* Index 0x20~0x23 */
 496         {0x00, 0x00, 0x3F}, {0x10, 0x00, 0x3F}, {0x1F, 0x00, 0x3F}, {0x2F,
 497                                                                      0x00,
 498                                                                      0x3F},
 499         /* Index 0x24~0x27 */
 500         {0x3F, 0x00, 0x3F}, {0x3F, 0x00, 0x2F}, {0x3F, 0x00, 0x1F}, {0x3F,
 501                                                                      0x00,
 502                                                                      0x10},
 503         /* Index 0x28~0x2B */
 504         {0x3F, 0x00, 0x00}, {0x3F, 0x10, 0x00}, {0x3F, 0x1F, 0x00}, {0x3F,
 505                                                                      0x2F,
 506                                                                      0x00},
 507         /* Index 0x2C~0x2F */
 508         {0x3F, 0x3F, 0x00}, {0x2F, 0x3F, 0x00}, {0x1F, 0x3F, 0x00}, {0x10,
 509                                                                      0x3F,
 510                                                                      0x00},
 511         /* Index 0x30~0x33 */
 512         {0x00, 0x3F, 0x00}, {0x00, 0x3F, 0x10}, {0x00, 0x3F, 0x1F}, {0x00,
 513                                                                      0x3F,
 514                                                                      0x2F},
 515         /* Index 0x34~0x37 */
 516         {0x00, 0x3F, 0x3F}, {0x00, 0x2F, 0x3F}, {0x00, 0x1F, 0x3F}, {0x00,
 517                                                                      0x10,
 518                                                                      0x3F},
 519         /* Index 0x38~0x3B */
 520         {0x1F, 0x1F, 0x3F}, {0x27, 0x1F, 0x3F}, {0x2F, 0x1F, 0x3F}, {0x37,
 521                                                                      0x1F,
 522                                                                      0x3F},
 523         /* Index 0x3C~0x3F */
 524         {0x3F, 0x1F, 0x3F}, {0x3F, 0x1F, 0x37}, {0x3F, 0x1F, 0x2F}, {0x3F,
 525                                                                      0x1F,
 526                                                                      0x27},
 527         /* Index 0x40~0x43 */
 528         {0x3F, 0x1F, 0x1F}, {0x3F, 0x27, 0x1F}, {0x3F, 0x2F, 0x1F}, {0x3F,
 529                                                                      0x3F,
 530                                                                      0x1F},
 531         /* Index 0x44~0x47 */
 532         {0x3F, 0x3F, 0x1F}, {0x37, 0x3F, 0x1F}, {0x2F, 0x3F, 0x1F}, {0x27,
 533                                                                      0x3F,
 534                                                                      0x1F},
 535         /* Index 0x48~0x4B */
 536         {0x1F, 0x3F, 0x1F}, {0x1F, 0x3F, 0x27}, {0x1F, 0x3F, 0x2F}, {0x1F,
 537                                                                      0x3F,
 538                                                                      0x37},
 539         /* Index 0x4C~0x4F */
 540         {0x1F, 0x3F, 0x3F}, {0x1F, 0x37, 0x3F}, {0x1F, 0x2F, 0x3F}, {0x1F,
 541                                                                      0x27,
 542                                                                      0x3F},
 543         /* Index 0x50~0x53 */
 544         {0x2D, 0x2D, 0x3F}, {0x31, 0x2D, 0x3F}, {0x36, 0x2D, 0x3F}, {0x3A,
 545                                                                      0x2D,
 546                                                                      0x3F},
 547         /* Index 0x54~0x57 */
 548         {0x3F, 0x2D, 0x3F}, {0x3F, 0x2D, 0x3A}, {0x3F, 0x2D, 0x36}, {0x3F,
 549                                                                      0x2D,
 550                                                                      0x31},
 551         /* Index 0x58~0x5B */
 552         {0x3F, 0x2D, 0x2D}, {0x3F, 0x31, 0x2D}, {0x3F, 0x36, 0x2D}, {0x3F,
 553                                                                      0x3A,
 554                                                                      0x2D},
 555         /* Index 0x5C~0x5F */
 556         {0x3F, 0x3F, 0x2D}, {0x3A, 0x3F, 0x2D}, {0x36, 0x3F, 0x2D}, {0x31,
 557                                                                      0x3F,
 558                                                                      0x2D},
 559         /* Index 0x60~0x63 */
 560         {0x2D, 0x3F, 0x2D}, {0x2D, 0x3F, 0x31}, {0x2D, 0x3F, 0x36}, {0x2D,
 561                                                                      0x3F,
 562                                                                      0x3A},
 563         /* Index 0x64~0x67 */
 564         {0x2D, 0x3F, 0x3F}, {0x2D, 0x3A, 0x3F}, {0x2D, 0x36, 0x3F}, {0x2D,
 565                                                                      0x31,
 566                                                                      0x3F},
 567         /* Index 0x68~0x6B */
 568         {0x00, 0x00, 0x1C}, {0x07, 0x00, 0x1C}, {0x0E, 0x00, 0x1C}, {0x15,
 569                                                                      0x00,
 570                                                                      0x1C},
 571         /* Index 0x6C~0x6F */
 572         {0x1C, 0x00, 0x1C}, {0x1C, 0x00, 0x15}, {0x1C, 0x00, 0x0E}, {0x1C,
 573                                                                      0x00,
 574                                                                      0x07},
 575         /* Index 0x70~0x73 */
 576         {0x1C, 0x00, 0x00}, {0x1C, 0x07, 0x00}, {0x1C, 0x0E, 0x00}, {0x1C,
 577                                                                      0x15,
 578                                                                      0x00},
 579         /* Index 0x74~0x77 */
 580         {0x1C, 0x1C, 0x00}, {0x15, 0x1C, 0x00}, {0x0E, 0x1C, 0x00}, {0x07,
 581                                                                      0x1C,
 582                                                                      0x00},
 583         /* Index 0x78~0x7B */
 584         {0x00, 0x1C, 0x00}, {0x00, 0x1C, 0x07}, {0x00, 0x1C, 0x0E}, {0x00,
 585                                                                      0x1C,
 586                                                                      0x15},
 587         /* Index 0x7C~0x7F */
 588         {0x00, 0x1C, 0x1C}, {0x00, 0x15, 0x1C}, {0x00, 0x0E, 0x1C}, {0x00,
 589                                                                      0x07,
 590                                                                      0x1C},
 591         /* Index 0x80~0x83 */
 592         {0x0E, 0x0E, 0x1C}, {0x11, 0x0E, 0x1C}, {0x15, 0x0E, 0x1C}, {0x18,
 593                                                                      0x0E,
 594                                                                      0x1C},
 595         /* Index 0x84~0x87 */
 596         {0x1C, 0x0E, 0x1C}, {0x1C, 0x0E, 0x18}, {0x1C, 0x0E, 0x15}, {0x1C,
 597                                                                      0x0E,
 598                                                                      0x11},
 599         /* Index 0x88~0x8B */
 600         {0x1C, 0x0E, 0x0E}, {0x1C, 0x11, 0x0E}, {0x1C, 0x15, 0x0E}, {0x1C,
 601                                                                      0x18,
 602                                                                      0x0E},
 603         /* Index 0x8C~0x8F */
 604         {0x1C, 0x1C, 0x0E}, {0x18, 0x1C, 0x0E}, {0x15, 0x1C, 0x0E}, {0x11,
 605                                                                      0x1C,
 606                                                                      0x0E},
 607         /* Index 0x90~0x93 */
 608         {0x0E, 0x1C, 0x0E}, {0x0E, 0x1C, 0x11}, {0x0E, 0x1C, 0x15}, {0x0E,
 609                                                                      0x1C,
 610                                                                      0x18},
 611         /* Index 0x94~0x97 */
 612         {0x0E, 0x1C, 0x1C}, {0x0E, 0x18, 0x1C}, {0x0E, 0x15, 0x1C}, {0x0E,
 613                                                                      0x11,
 614                                                                      0x1C},
 615         /* Index 0x98~0x9B */
 616         {0x14, 0x14, 0x1C}, {0x16, 0x14, 0x1C}, {0x18, 0x14, 0x1C}, {0x1A,
 617                                                                      0x14,
 618                                                                      0x1C},
 619         /* Index 0x9C~0x9F */
 620         {0x1C, 0x14, 0x1C}, {0x1C, 0x14, 0x1A}, {0x1C, 0x14, 0x18}, {0x1C,
 621                                                                      0x14,
 622                                                                      0x16},
 623         /* Index 0xA0~0xA3 */
 624         {0x1C, 0x14, 0x14}, {0x1C, 0x16, 0x14}, {0x1C, 0x18, 0x14}, {0x1C,
 625                                                                      0x1A,
 626                                                                      0x14},
 627         /* Index 0xA4~0xA7 */
 628         {0x1C, 0x1C, 0x14}, {0x1A, 0x1C, 0x14}, {0x18, 0x1C, 0x14}, {0x16,
 629                                                                      0x1C,
 630                                                                      0x14},
 631         /* Index 0xA8~0xAB */
 632         {0x14, 0x1C, 0x14}, {0x14, 0x1C, 0x16}, {0x14, 0x1C, 0x18}, {0x14,
 633                                                                      0x1C,
 634                                                                      0x1A},
 635         /* Index 0xAC~0xAF */
 636         {0x14, 0x1C, 0x1C}, {0x14, 0x1A, 0x1C}, {0x14, 0x18, 0x1C}, {0x14,
 637                                                                      0x16,
 638                                                                      0x1C},
 639         /* Index 0xB0~0xB3 */
 640         {0x00, 0x00, 0x10}, {0x04, 0x00, 0x10}, {0x08, 0x00, 0x10}, {0x0C,
 641                                                                      0x00,
 642                                                                      0x10},
 643         /* Index 0xB4~0xB7 */
 644         {0x10, 0x00, 0x10}, {0x10, 0x00, 0x0C}, {0x10, 0x00, 0x08}, {0x10,
 645                                                                      0x00,
 646                                                                      0x04},
 647         /* Index 0xB8~0xBB */
 648         {0x10, 0x00, 0x00}, {0x10, 0x04, 0x00}, {0x10, 0x08, 0x00}, {0x10,
 649                                                                      0x0C,
 650                                                                      0x00},
 651         /* Index 0xBC~0xBF */
 652         {0x10, 0x10, 0x00}, {0x0C, 0x10, 0x00}, {0x08, 0x10, 0x00}, {0x04,
 653                                                                      0x10,
 654                                                                      0x00},
 655         /* Index 0xC0~0xC3 */
 656         {0x00, 0x10, 0x00}, {0x00, 0x10, 0x04}, {0x00, 0x10, 0x08}, {0x00,
 657                                                                      0x10,
 658                                                                      0x0C},
 659         /* Index 0xC4~0xC7 */
 660         {0x00, 0x10, 0x10}, {0x00, 0x0C, 0x10}, {0x00, 0x08, 0x10}, {0x00,
 661                                                                      0x04,
 662                                                                      0x10},
 663         /* Index 0xC8~0xCB */
 664         {0x08, 0x08, 0x10}, {0x0A, 0x08, 0x10}, {0x0C, 0x08, 0x10}, {0x0E,
 665                                                                      0x08,
 666                                                                      0x10},
 667         /* Index 0xCC~0xCF */
 668         {0x10, 0x08, 0x10}, {0x10, 0x08, 0x0E}, {0x10, 0x08, 0x0C}, {0x10,
 669                                                                      0x08,
 670                                                                      0x0A},
 671         /* Index 0xD0~0xD3 */
 672         {0x10, 0x08, 0x08}, {0x10, 0x0A, 0x08}, {0x10, 0x0C, 0x08}, {0x10,
 673                                                                      0x0E,
 674                                                                      0x08},
 675         /* Index 0xD4~0xD7 */
 676         {0x10, 0x10, 0x08}, {0x0E, 0x10, 0x08}, {0x0C, 0x10, 0x08}, {0x0A,
 677                                                                      0x10,
 678                                                                      0x08},
 679         /* Index 0xD8~0xDB */
 680         {0x08, 0x10, 0x08}, {0x08, 0x10, 0x0A}, {0x08, 0x10, 0x0C}, {0x08,
 681                                                                      0x10,
 682                                                                      0x0E},
 683         /* Index 0xDC~0xDF */
 684         {0x08, 0x10, 0x10}, {0x08, 0x0E, 0x10}, {0x08, 0x0C, 0x10}, {0x08,
 685                                                                      0x0A,
 686                                                                      0x10},
 687         /* Index 0xE0~0xE3 */
 688         {0x0B, 0x0B, 0x10}, {0x0C, 0x0B, 0x10}, {0x0D, 0x0B, 0x10}, {0x0F,
 689                                                                      0x0B,
 690                                                                      0x10},
 691         /* Index 0xE4~0xE7 */
 692         {0x10, 0x0B, 0x10}, {0x10, 0x0B, 0x0F}, {0x10, 0x0B, 0x0D}, {0x10,
 693                                                                      0x0B,
 694                                                                      0x0C},
 695         /* Index 0xE8~0xEB */
 696         {0x10, 0x0B, 0x0B}, {0x10, 0x0C, 0x0B}, {0x10, 0x0D, 0x0B}, {0x10,
 697                                                                      0x0F,
 698                                                                      0x0B},
 699         /* Index 0xEC~0xEF */
 700         {0x10, 0x10, 0x0B}, {0x0F, 0x10, 0x0B}, {0x0D, 0x10, 0x0B}, {0x0C,
 701                                                                      0x10,
 702                                                                      0x0B},
 703         /* Index 0xF0~0xF3 */
 704         {0x0B, 0x10, 0x0B}, {0x0B, 0x10, 0x0C}, {0x0B, 0x10, 0x0D}, {0x0B,
 705                                                                      0x10,
 706                                                                      0x0F},
 707         /* Index 0xF4~0xF7 */
 708         {0x0B, 0x10, 0x10}, {0x0B, 0x0F, 0x10}, {0x0B, 0x0D, 0x10}, {0x0B,
 709                                                                      0x0C,
 710                                                                      0x10},
 711         /* Index 0xF8~0xFB */
 712         {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00,
 713                                                                      0x00,
 714                                                                      0x00},
 715         /* Index 0xFC~0xFF */
 716         {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00,
 717                                                                      0x00,
 718                                                                      0x00}
 719 };
 720
 721 static void set_crt_output_path(int set_iga);
 722 static void dvi_patch_skew_dvp0(void);
 723 static void dvi_patch_skew_dvp_low(void);
 724 static void set_dvi_output_path(int set_iga, int output_interface);
 725 static void set_lcd_output_path(int set_iga, int output_interface);
 726 static void load_fix_bit_crtc_reg(void);
 727 static void __devinit init_gfx_chip_info(int chip_type);
 728 static void __devinit init_tmds_chip_info(void);
 729 static void __devinit init_lvds_chip_info(void);
 730 static void device_screen_off(void);
 731 static void device_screen_on(void);
 732 static void set_display_channel(void);
 733 static void device_off(void);
 734 static void device_on(void);
 735 static void enable_second_display_channel(void);
 736
 737 void viafb_lock_crt(void)
 738 {
 739         viafb_write_reg_mask(CR11, VIACR, BIT7, BIT7);
 740 }
 741
 742 void viafb_unlock_crt(void)
 743 {
 744         viafb_write_reg_mask(CR11, VIACR, 0, BIT7);
 745         viafb_write_reg_mask(CR47, VIACR, 0, BIT0);
 746 }
 747
 748 void write_dac_reg(u8 index, u8 r, u8 g, u8 b)
 749 {
 750         outb(index, LUT_INDEX_WRITE);
 751         outb(r, LUT_DATA);
 752         outb(g, LUT_DATA);
 753         outb(b, LUT_DATA);
 754 }
 755
 756 static u32 get_dvi_devices(int output_interface)
 757 {
 758         switch (output_interface) {
 759         case INTERFACE_DVP0:
 760                 return VIA_96 | VIA_6C;
 761
 762         case INTERFACE_DVP1:
 763                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
 764                         return VIA_93;
 765                 else
 766                         return VIA_DVP1;
 767
 768         case INTERFACE_DFP_HIGH:
 769                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
 770                         return 0;
 771                 else
 772                         return VIA_LVDS2 | VIA_96;
 773
 774         case INTERFACE_DFP_LOW:
 775                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
 776                         return 0;
 777                 else
 778                         return VIA_DVP1 | VIA_LVDS1;
 779
 780         case INTERFACE_TMDS:
 781                 return VIA_LVDS1;
 782         }
 783
 784         return 0;
 785 }
 786
 787 static u32 get_lcd_devices(int output_interface)
 788 {
 789         switch (output_interface) {
 790         case INTERFACE_DVP0:
 791                 return VIA_96;
 792
 793         case INTERFACE_DVP1:
 794                 return VIA_DVP1;
 795
 796         case INTERFACE_DFP_HIGH:
 797                 return VIA_LVDS2 | VIA_96;
 798
 799         case INTERFACE_DFP_LOW:
 800                 return VIA_LVDS1 | VIA_DVP1;
 801
 802         case INTERFACE_DFP:
 803                 return VIA_LVDS1 | VIA_LVDS2;
 804
 805         case INTERFACE_LVDS0:
 806         case INTERFACE_LVDS0LVDS1:
 807                 return VIA_LVDS1;
 808
 809         case INTERFACE_LVDS1:
 810                 return VIA_LVDS2;
 811         }
 812
 813         return 0;
 814 }
 815
 816 /*Set IGA path for each device*/
 817 void viafb_set_iga_path(void)
 818 {
 819
 820         if (viafb_SAMM_ON == 1) {
 821                 if (viafb_CRT_ON) {
 822                         if (viafb_primary_dev == CRT_Device)
 823                                 viaparinfo->crt_setting_info->iga_path = IGA1;
 824                         else
 825                                 viaparinfo->crt_setting_info->iga_path = IGA2;
 826                 }
 827
 828                 if (viafb_DVI_ON) {
 829                         if (viafb_primary_dev == DVI_Device)
 830                                 viaparinfo->tmds_setting_info->iga_path = IGA1;
 831                         else
 832                                 viaparinfo->tmds_setting_info->iga_path = IGA2;
 833                 }
 834
 835                 if (viafb_LCD_ON) {
 836                         if (viafb_primary_dev == LCD_Device) {
 837                                 if (viafb_dual_fb &&
 838                                         (viaparinfo->chip_info->gfx_chip_name ==
 839                                         UNICHROME_CLE266)) {
 840                                         viaparinfo->
 841                                         lvds_setting_info->iga_path = IGA2;
 842                                         viaparinfo->
 843                                         crt_setting_info->iga_path = IGA1;
 844                                         viaparinfo->
 845                                         tmds_setting_info->iga_path = IGA1;
 846                                 } else
 847                                         viaparinfo->
 848                                         lvds_setting_info->iga_path = IGA1;
 849                         } else {
 850                                 viaparinfo->lvds_setting_info->iga_path = IGA2;
 851                         }
 852                 }
 853                 if (viafb_LCD2_ON) {
 854                         if (LCD2_Device == viafb_primary_dev)
 855                                 viaparinfo->lvds_setting_info2->iga_path = IGA1;
 856                         else
 857                                 viaparinfo->lvds_setting_info2->iga_path = IGA2;
 858                 }
 859         } else {
 860                 viafb_SAMM_ON = 0;
 861
 862                 if (viafb_CRT_ON && viafb_LCD_ON) {
 863                         viaparinfo->crt_setting_info->iga_path = IGA1;
 864                         viaparinfo->lvds_setting_info->iga_path = IGA2;
 865                 } else if (viafb_CRT_ON && viafb_DVI_ON) {
 866                         viaparinfo->crt_setting_info->iga_path = IGA1;
 867                         viaparinfo->tmds_setting_info->iga_path = IGA2;
 868                 } else if (viafb_LCD_ON && viafb_DVI_ON) {
 869                         viaparinfo->tmds_setting_info->iga_path = IGA1;
 870                         viaparinfo->lvds_setting_info->iga_path = IGA2;
 871                 } else if (viafb_LCD_ON && viafb_LCD2_ON) {
 872                         viaparinfo->lvds_setting_info->iga_path = IGA2;
 873                         viaparinfo->lvds_setting_info2->iga_path = IGA2;
 874                 } else if (viafb_CRT_ON) {
 875                         viaparinfo->crt_setting_info->iga_path = IGA1;
 876                 } else if (viafb_LCD_ON) {
 877                         viaparinfo->lvds_setting_info->iga_path = IGA2;
 878                 } else if (viafb_DVI_ON) {
 879                         viaparinfo->tmds_setting_info->iga_path = IGA1;
 880                 }
 881         }
 882
 883         viaparinfo->shared->iga1_devices = 0;
 884         viaparinfo->shared->iga2_devices = 0;
 885         if (viafb_CRT_ON) {
 886                 if (viaparinfo->crt_setting_info->iga_path == IGA1)
 887                         viaparinfo->shared->iga1_devices |= VIA_CRT;
 888                 else
 889                         viaparinfo->shared->iga2_devices |= VIA_CRT;
 890         }
 891
 892         if (viafb_DVI_ON) {
 893                 if (viaparinfo->tmds_setting_info->iga_path == IGA1)
 894                         viaparinfo->shared->iga1_devices |= get_dvi_devices(
 895                                 viaparinfo->chip_info->
 896                                 tmds_chip_info.output_interface);
 897                 else
 898                         viaparinfo->shared->iga2_devices |= get_dvi_devices(
 899                                 viaparinfo->chip_info->
 900                                 tmds_chip_info.output_interface);
 901         }
 902
 903         if (viafb_LCD_ON) {
 904                 if (viaparinfo->lvds_setting_info->iga_path == IGA1)
 905                         viaparinfo->shared->iga1_devices |= get_lcd_devices(
 906                                 viaparinfo->chip_info->
 907                                 lvds_chip_info.output_interface);
 908                 else
 909                         viaparinfo->shared->iga2_devices |= get_lcd_devices(
 910                                 viaparinfo->chip_info->
 911                                 lvds_chip_info.output_interface);
 912         }
 913
 914         if (viafb_LCD2_ON) {
 915                 if (viaparinfo->lvds_setting_info2->iga_path == IGA1)
 916                         viaparinfo->shared->iga1_devices |= get_lcd_devices(
 917                                 viaparinfo->chip_info->
 918                                 lvds_chip_info2.output_interface);
 919                 else
 920                         viaparinfo->shared->iga2_devices |= get_lcd_devices(
 921                                 viaparinfo->chip_info->
 922                                 lvds_chip_info2.output_interface);
 923         }
 924 }
 925
 926 static void set_color_register(u8 index, u8 red, u8 green, u8 blue)
 927 {
 928         outb(0xFF, 0x3C6); /* bit mask of palette */
 929         outb(index, 0x3C8);
 930         outb(red, 0x3C9);
 931         outb(green, 0x3C9);
 932         outb(blue, 0x3C9);
 933 }
 934
 935 void viafb_set_primary_color_register(u8 index, u8 red, u8 green, u8 blue)
 936 {
 937         viafb_write_reg_mask(0x1A, VIASR, 0x00, 0x01);
 938         set_color_register(index, red, green, blue);
 939 }
 940
 941 void viafb_set_secondary_color_register(u8 index, u8 red, u8 green, u8 blue)
 942 {
 943         viafb_write_reg_mask(0x1A, VIASR, 0x01, 0x01);
 944         set_color_register(index, red, green, blue);
 945 }
 946
 947 void viafb_set_output_path(int device, int set_iga, int output_interface)
 948 {
 949         switch (device) {
 950         case DEVICE_CRT:
 951                 set_crt_output_path(set_iga);
 952                 break;
 953         case DEVICE_DVI:
 954                 set_dvi_output_path(set_iga, output_interface);
 955                 break;
 956         case DEVICE_LCD:
 957                 set_lcd_output_path(set_iga, output_interface);
 958                 break;
 959         }
 960
 961         if (set_iga == IGA2)
 962                 enable_second_display_channel();
 963 }
 964
 965 static void set_source_common(u8 index, u8 offset, u8 iga)
 966 {
 967         u8 value, mask = 1 << offset;
 968
 969         switch (iga) {
 970         case IGA1:
 971                 value = 0x00;
 972                 break;
 973         case IGA2:
 974                 value = mask;
 975                 break;
 976         default:
 977                 printk(KERN_WARNING "viafb: Unsupported source: %d\n", iga);
 978                 return;
 979         }
 980
 981         via_write_reg_mask(VIACR, index, value, mask);
 982 }
 983
 984 static void set_crt_source(u8 iga)
 985 {
 986         u8 value;
 987
 988         switch (iga) {
 989         case IGA1:
 990                 value = 0x00;
 991                 break;
 992         case IGA2:
 993                 value = 0x40;
 994                 break;
 995         default:
 996                 printk(KERN_WARNING "viafb: Unsupported source: %d\n", iga);
 997                 return;
 998         }
 999
1000         via_write_reg_mask(VIASR, 0x16, value, 0x40);
1001 }
1002
1003 static inline void set_6C_source(u8 iga)
1004 {
1005         set_source_common(0x6C, 7, iga);
1006 }
1007
1008 static inline void set_93_source(u8 iga)
1009 {
1010         set_source_common(0x93, 7, iga);
1011 }
1012
1013 static inline void set_96_source(u8 iga)
1014 {
1015         set_source_common(0x96, 4, iga);
1016 }
1017
1018 static inline void set_dvp1_source(u8 iga)
1019 {
1020         set_source_common(0x9B, 4, iga);
1021 }
1022
1023 static inline void set_lvds1_source(u8 iga)
1024 {
1025         set_source_common(0x99, 4, iga);
1026 }
1027
1028 static inline void set_lvds2_source(u8 iga)
1029 {
1030         set_source_common(0x97, 4, iga);
1031 }
1032
1033 static void set_crt_output_path(int set_iga)
1034 {
1035         viafb_write_reg_mask(CR36, VIACR, 0x00, BIT4 + BIT5);
1036         set_crt_source(set_iga);
1037 }
1038
1039 static void dvi_patch_skew_dvp0(void)
1040 {
1041         /* Reset data driving first: */
1042         viafb_write_reg_mask(SR1B, VIASR, 0, BIT1);
1043         viafb_write_reg_mask(SR2A, VIASR, 0, BIT4);
1044
1045         switch (viaparinfo->chip_info->gfx_chip_name) {
1046         case UNICHROME_P4M890:
1047                 {
1048                         if ((viaparinfo->tmds_setting_info->h_active == 1600) &&
1049                                 (viaparinfo->tmds_setting_info->v_active ==
1050                                 1200))
1051                                 viafb_write_reg_mask(CR96, VIACR, 0x03,
1052                                                BIT0 + BIT1 + BIT2);
1053                         else
1054                                 viafb_write_reg_mask(CR96, VIACR, 0x07,
1055                                                BIT0 + BIT1 + BIT2);
1056                         break;
1057                 }
1058
1059         case UNICHROME_P4M900:
1060                 {
1061                         viafb_write_reg_mask(CR96, VIACR, 0x07,
1062                                        BIT0 + BIT1 + BIT2 + BIT3);
1063                         viafb_write_reg_mask(SR1B, VIASR, 0x02, BIT1);
1064                         viafb_write_reg_mask(SR2A, VIASR, 0x10, BIT4);
1065                         break;
1066                 }
1067
1068         default:
1069                 {
1070                         break;
1071                 }
1072         }
1073 }
1074
1075 static void dvi_patch_skew_dvp_low(void)
1076 {
1077         switch (viaparinfo->chip_info->gfx_chip_name) {
1078         case UNICHROME_K8M890:
1079                 {
1080                         viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1);
1081                         break;
1082                 }
1083
1084         case UNICHROME_P4M900:
1085                 {
1086                         viafb_write_reg_mask(CR99, VIACR, 0x08,
1087                                        BIT0 + BIT1 + BIT2 + BIT3);
1088                         break;
1089                 }
1090
1091         case UNICHROME_P4M890:
1092                 {
1093                         viafb_write_reg_mask(CR99, VIACR, 0x0F,
1094                                        BIT0 + BIT1 + BIT2 + BIT3);
1095                         break;
1096                 }
1097
1098         default:
1099                 {
1100                         break;
1101                 }
1102         }
1103 }
1104
1105 static void set_dvi_output_path(int set_iga, int output_interface)
1106 {
1107         switch (output_interface) {
1108         case INTERFACE_DVP0:
1109                 set_96_source(set_iga);
1110                 set_6C_source(set_iga);
1111                 viafb_write_reg_mask(CR6B, VIACR, 0x01, BIT0);
1112                 viafb_write_reg_mask(CR6C, VIACR, 0x21, BIT0 + BIT5);
1113                 viafb_write_reg_mask(SR1E, VIASR, 0xC0, BIT7 + BIT6);
1114                 dvi_patch_skew_dvp0();
1115                 break;
1116
1117         case INTERFACE_DVP1:
1118                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
1119                         set_93_source(set_iga);
1120                         viafb_write_reg_mask(CR93, VIACR, 0x21, BIT0 + BIT5);
1121                 } else {
1122                         set_dvp1_source(set_iga);
1123                 }
1124
1125                 viafb_write_reg_mask(SR1E, VIASR, 0x30, BIT4 + BIT5);
1126                 break;
1127         case INTERFACE_DFP_HIGH:
1128                 if (viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266) {
1129                         via_write_reg_mask(VIACR, CR97, 0x03, 0x03);
1130                         set_lvds2_source(set_iga);
1131                         set_96_source(set_iga);
1132                 }
1133
1134                 viafb_write_reg_mask(SR2A, VIASR, 0x0C, BIT2 + BIT3);
1135                 break;
1136
1137         case INTERFACE_DFP_LOW:
1138                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
1139                         break;
1140                 set_dvp1_source(set_iga);
1141                 set_lvds1_source(set_iga);
1142                 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1);
1143                 dvi_patch_skew_dvp_low();
1144                 break;
1145
1146         case INTERFACE_TMDS:
1147                 set_lvds1_source(set_iga);
1148                 break;
1149         }
1150
1151         if (set_iga == IGA2) {
1152                 /* Disable LCD Scaling */
1153                 viafb_write_reg_mask(CR79, VIACR, 0x00, BIT0);
1154         }
1155 }
1156
1157 static void set_lcd_output_path(int set_iga, int output_interface)
1158 {
1159         DEBUG_MSG(KERN_INFO
1160                   "set_lcd_output_path, iga:%d,out_interface:%d\n",
1161                   set_iga, output_interface);
1162
1163         viafb_write_reg_mask(CR6B, VIACR, 0x00, BIT3);
1164         viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
1165         switch (output_interface) {
1166         case INTERFACE_DVP0:
1167                 set_96_source(set_iga);
1168                 if (set_iga == IGA2)
1169                         viafb_write_reg(CR91, VIACR, 0x00);
1170                 break;
1171
1172         case INTERFACE_DVP1:
1173                 set_dvp1_source(set_iga);
1174                 if (set_iga == IGA2)
1175                         viafb_write_reg(CR91, VIACR, 0x00);
1176                 break;
1177
1178         case INTERFACE_DFP_HIGH:
1179                 set_lvds2_source(set_iga);
1180                 set_96_source(set_iga);
1181                 if (set_iga == IGA2)
1182                         viafb_write_reg(CR91, VIACR, 0x00);
1183                 break;
1184
1185         case INTERFACE_DFP_LOW:
1186                 set_lvds1_source(set_iga);
1187                 set_dvp1_source(set_iga);
1188                 if (set_iga == IGA2)
1189                         viafb_write_reg(CR91, VIACR, 0x00);
1190                 break;
1191
1192         case INTERFACE_DFP:
1193                 if ((UNICHROME_K8M890 == viaparinfo->chip_info->gfx_chip_name)
1194                     || (UNICHROME_P4M890 ==
1195                     viaparinfo->chip_info->gfx_chip_name))
1196                         viafb_write_reg_mask(CR97, VIACR, 0x84,
1197                                        BIT7 + BIT2 + BIT1 + BIT0);
1198
1199                 set_lvds1_source(set_iga);
1200                 set_lvds2_source(set_iga);
1201                 if (set_iga == IGA2)
1202                         viafb_write_reg(CR91, VIACR, 0x00);
1203                 break;
1204
1205         case INTERFACE_LVDS0:
1206         case INTERFACE_LVDS0LVDS1:
1207                 set_lvds1_source(set_iga);
1208                 break;
1209
1210         case INTERFACE_LVDS1:
1211                 set_lvds2_source(set_iga);
1212                 break;
1213         }
1214 }
1215
1216 static void load_fix_bit_crtc_reg(void)
1217 {
1218         /* always set to 1 */
1219         viafb_write_reg_mask(CR03, VIACR, 0x80, BIT7);
1220         /* line compare should set all bits = 1 (extend modes) */
1221         viafb_write_reg(CR18, VIACR, 0xff);
1222         /* line compare should set all bits = 1 (extend modes) */
1223         viafb_write_reg_mask(CR07, VIACR, 0x10, BIT4);
1224         /* line compare should set all bits = 1 (extend modes) */
1225         viafb_write_reg_mask(CR09, VIACR, 0x40, BIT6);
1226         /* line compare should set all bits = 1 (extend modes) */
1227         viafb_write_reg_mask(CR35, VIACR, 0x10, BIT4);
1228         /* line compare should set all bits = 1 (extend modes) */
1229         viafb_write_reg_mask(CR33, VIACR, 0x06, BIT0 + BIT1 + BIT2);
1230         /*viafb_write_reg_mask(CR32, VIACR, 0x01, BIT0); */
1231         /* extend mode always set to e3h */
1232         viafb_write_reg(CR17, VIACR, 0xe3);
1233         /* extend mode always set to 0h */
1234         viafb_write_reg(CR08, VIACR, 0x00);
1235         /* extend mode always set to 0h */
1236         viafb_write_reg(CR14, VIACR, 0x00);
1237
1238         /* If K8M800, enable Prefetch Mode. */
1239         if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800)
1240                 || (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890))
1241                 viafb_write_reg_mask(CR33, VIACR, 0x08, BIT3);
1242         if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
1243             && (viaparinfo->chip_info->gfx_chip_revision == CLE266_REVISION_AX))
1244                 viafb_write_reg_mask(SR1A, VIASR, 0x02, BIT1);
1245
1246 }
1247
1248 void viafb_load_reg(int timing_value, int viafb_load_reg_num,
1249         struct io_register *reg,
1250               int io_type)
1251 {
1252         int reg_mask;
1253         int bit_num = 0;
1254         int data;
1255         int i, j;
1256         int shift_next_reg;
1257         int start_index, end_index, cr_index;
1258         u16 get_bit;
1259
1260         for (i = 0; i < viafb_load_reg_num; i++) {
1261                 reg_mask = 0;
1262                 data = 0;
1263                 start_index = reg[i].start_bit;
1264                 end_index = reg[i].end_bit;
1265                 cr_index = reg[i].io_addr;
1266
1267                 shift_next_reg = bit_num;
1268                 for (j = start_index; j <= end_index; j++) {
1269                         /*if (bit_num==8) timing_value = timing_value >>8; */
1270                         reg_mask = reg_mask | (BIT0 << j);
1271                         get_bit = (timing_value & (BIT0 << bit_num));
1272                         data =
1273                             data | ((get_bit >> shift_next_reg) << start_index);
1274                         bit_num++;
1275                 }
1276                 if (io_type == VIACR)
1277                         viafb_write_reg_mask(cr_index, VIACR, data, reg_mask);
1278                 else
1279                         viafb_write_reg_mask(cr_index, VIASR, data, reg_mask);
1280         }
1281
1282 }
1283
1284 /* Write Registers */
1285 void viafb_write_regx(struct io_reg RegTable[], int ItemNum)
1286 {
1287         int i;
1288
1289         /*DEBUG_MSG(KERN_INFO "Table Size : %x!!\n",ItemNum ); */
1290
1291         for (i = 0; i < ItemNum; i++)
1292                 via_write_reg_mask(RegTable[i].port, RegTable[i].index,
1293                         RegTable[i].value, RegTable[i].mask);
1294 }
1295
1296 void viafb_load_fetch_count_reg(int h_addr, int bpp_byte, int set_iga)
1297 {
1298         int reg_value;
1299         int viafb_load_reg_num;
1300         struct io_register *reg = NULL;
1301
1302         switch (set_iga) {
1303         case IGA1:
1304                 reg_value = IGA1_FETCH_COUNT_FORMULA(h_addr, bpp_byte);
1305                 viafb_load_reg_num = fetch_count_reg.
1306                         iga1_fetch_count_reg.reg_num;
1307                 reg = fetch_count_reg.iga1_fetch_count_reg.reg;
1308                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1309                 break;
1310         case IGA2:
1311                 reg_value = IGA2_FETCH_COUNT_FORMULA(h_addr, bpp_byte);
1312                 viafb_load_reg_num = fetch_count_reg.
1313                         iga2_fetch_count_reg.reg_num;
1314                 reg = fetch_count_reg.iga2_fetch_count_reg.reg;
1315                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1316                 break;
1317         }
1318
1319 }
1320
1321 void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active)
1322 {
1323         int reg_value;
1324         int viafb_load_reg_num;
1325         struct io_register *reg = NULL;
1326         int iga1_fifo_max_depth = 0, iga1_fifo_threshold =
1327             0, iga1_fifo_high_threshold = 0, iga1_display_queue_expire_num = 0;
1328         int iga2_fifo_max_depth = 0, iga2_fifo_threshold =
1329             0, iga2_fifo_high_threshold = 0, iga2_display_queue_expire_num = 0;
1330
1331         if (set_iga == IGA1) {
1332                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1333                         iga1_fifo_max_depth = K800_IGA1_FIFO_MAX_DEPTH;
1334                         iga1_fifo_threshold = K800_IGA1_FIFO_THRESHOLD;
1335                         iga1_fifo_high_threshold =
1336                             K800_IGA1_FIFO_HIGH_THRESHOLD;
1337                         /* If resolution > 1280x1024, expire length = 64, else
1338                            expire length = 128 */
1339                         if ((hor_active > 1280) && (ver_active > 1024))
1340                                 iga1_display_queue_expire_num = 16;
1341                         else
1342                                 iga1_display_queue_expire_num =
1343                                     K800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1344
1345                 }
1346
1347                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_PM800) {
1348                         iga1_fifo_max_depth = P880_IGA1_FIFO_MAX_DEPTH;
1349                         iga1_fifo_threshold = P880_IGA1_FIFO_THRESHOLD;
1350                         iga1_fifo_high_threshold =
1351                             P880_IGA1_FIFO_HIGH_THRESHOLD;
1352                         iga1_display_queue_expire_num =
1353                             P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1354
1355                         /* If resolution > 1280x1024, expire length = 64, else
1356                            expire length = 128 */
1357                         if ((hor_active > 1280) && (ver_active > 1024))
1358                                 iga1_display_queue_expire_num = 16;
1359                         else
1360                                 iga1_display_queue_expire_num =
1361                                     P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1362                 }
1363
1364                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CN700) {
1365                         iga1_fifo_max_depth = CN700_IGA1_FIFO_MAX_DEPTH;
1366                         iga1_fifo_threshold = CN700_IGA1_FIFO_THRESHOLD;
1367                         iga1_fifo_high_threshold =
1368                             CN700_IGA1_FIFO_HIGH_THRESHOLD;
1369
1370                         /* If resolution > 1280x1024, expire length = 64,
1371                            else expire length = 128 */
1372                         if ((hor_active > 1280) && (ver_active > 1024))
1373                                 iga1_display_queue_expire_num = 16;
1374                         else
1375                                 iga1_display_queue_expire_num =
1376                                     CN700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1377                 }
1378
1379                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
1380                         iga1_fifo_max_depth = CX700_IGA1_FIFO_MAX_DEPTH;
1381                         iga1_fifo_threshold = CX700_IGA1_FIFO_THRESHOLD;
1382                         iga1_fifo_high_threshold =
1383                             CX700_IGA1_FIFO_HIGH_THRESHOLD;
1384                         iga1_display_queue_expire_num =
1385                             CX700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1386                 }
1387
1388                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890) {
1389                         iga1_fifo_max_depth = K8M890_IGA1_FIFO_MAX_DEPTH;
1390                         iga1_fifo_threshold = K8M890_IGA1_FIFO_THRESHOLD;
1391                         iga1_fifo_high_threshold =
1392                             K8M890_IGA1_FIFO_HIGH_THRESHOLD;
1393                         iga1_display_queue_expire_num =
1394                             K8M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1395                 }
1396
1397                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M890) {
1398                         iga1_fifo_max_depth = P4M890_IGA1_FIFO_MAX_DEPTH;
1399                         iga1_fifo_threshold = P4M890_IGA1_FIFO_THRESHOLD;
1400                         iga1_fifo_high_threshold =
1401                             P4M890_IGA1_FIFO_HIGH_THRESHOLD;
1402                         iga1_display_queue_expire_num =
1403                             P4M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1404                 }
1405
1406                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M900) {
1407                         iga1_fifo_max_depth = P4M900_IGA1_FIFO_MAX_DEPTH;
1408                         iga1_fifo_threshold = P4M900_IGA1_FIFO_THRESHOLD;
1409                         iga1_fifo_high_threshold =
1410                             P4M900_IGA1_FIFO_HIGH_THRESHOLD;
1411                         iga1_display_queue_expire_num =
1412                             P4M900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1413                 }
1414
1415                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX800) {
1416                         iga1_fifo_max_depth = VX800_IGA1_FIFO_MAX_DEPTH;
1417                         iga1_fifo_threshold = VX800_IGA1_FIFO_THRESHOLD;
1418                         iga1_fifo_high_threshold =
1419                             VX800_IGA1_FIFO_HIGH_THRESHOLD;
1420                         iga1_display_queue_expire_num =
1421                             VX800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1422                 }
1423
1424                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX855) {
1425                         iga1_fifo_max_depth = VX855_IGA1_FIFO_MAX_DEPTH;
1426                         iga1_fifo_threshold = VX855_IGA1_FIFO_THRESHOLD;
1427                         iga1_fifo_high_threshold =
1428                             VX855_IGA1_FIFO_HIGH_THRESHOLD;
1429                         iga1_display_queue_expire_num =
1430                             VX855_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1431                 }
1432
1433                 /* Set Display FIFO Depath Select */
1434                 reg_value = IGA1_FIFO_DEPTH_SELECT_FORMULA(iga1_fifo_max_depth);
1435                 viafb_load_reg_num =
1436                     display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg_num;
1437                 reg = display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg;
1438                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1439
1440                 /* Set Display FIFO Threshold Select */
1441                 reg_value = IGA1_FIFO_THRESHOLD_FORMULA(iga1_fifo_threshold);
1442                 viafb_load_reg_num =
1443                     fifo_threshold_select_reg.
1444                     iga1_fifo_threshold_select_reg.reg_num;
1445                 reg =
1446                     fifo_threshold_select_reg.
1447                     iga1_fifo_threshold_select_reg.reg;
1448                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1449
1450                 /* Set FIFO High Threshold Select */
1451                 reg_value =
1452                     IGA1_FIFO_HIGH_THRESHOLD_FORMULA(iga1_fifo_high_threshold);
1453                 viafb_load_reg_num =
1454                     fifo_high_threshold_select_reg.
1455                     iga1_fifo_high_threshold_select_reg.reg_num;
1456                 reg =
1457                     fifo_high_threshold_select_reg.
1458                     iga1_fifo_high_threshold_select_reg.reg;
1459                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1460
1461                 /* Set Display Queue Expire Num */
1462                 reg_value =
1463                     IGA1_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA
1464                     (iga1_display_queue_expire_num);
1465                 viafb_load_reg_num =
1466                     display_queue_expire_num_reg.
1467                     iga1_display_queue_expire_num_reg.reg_num;
1468                 reg =
1469                     display_queue_expire_num_reg.
1470                     iga1_display_queue_expire_num_reg.reg;
1471                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1472
1473         } else {
1474                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1475                         iga2_fifo_max_depth = K800_IGA2_FIFO_MAX_DEPTH;
1476                         iga2_fifo_threshold = K800_IGA2_FIFO_THRESHOLD;
1477                         iga2_fifo_high_threshold =
1478                             K800_IGA2_FIFO_HIGH_THRESHOLD;
1479
1480                         /* If resolution > 1280x1024, expire length = 64,
1481                            else  expire length = 128 */
1482                         if ((hor_active > 1280) && (ver_active > 1024))
1483                                 iga2_display_queue_expire_num = 16;
1484                         else
1485                                 iga2_display_queue_expire_num =
1486                                     K800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1487                 }
1488
1489                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_PM800) {
1490                         iga2_fifo_max_depth = P880_IGA2_FIFO_MAX_DEPTH;
1491                         iga2_fifo_threshold = P880_IGA2_FIFO_THRESHOLD;
1492                         iga2_fifo_high_threshold =
1493                             P880_IGA2_FIFO_HIGH_THRESHOLD;
1494
1495                         /* If resolution > 1280x1024, expire length = 64,
1496                            else  expire length = 128 */
1497                         if ((hor_active > 1280) && (ver_active > 1024))
1498                                 iga2_display_queue_expire_num = 16;
1499                         else
1500                                 iga2_display_queue_expire_num =
1501                                     P880_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1502                 }
1503
1504                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CN700) {
1505                         iga2_fifo_max_depth = CN700_IGA2_FIFO_MAX_DEPTH;
1506                         iga2_fifo_threshold = CN700_IGA2_FIFO_THRESHOLD;
1507                         iga2_fifo_high_threshold =
1508                             CN700_IGA2_FIFO_HIGH_THRESHOLD;
1509
1510                         /* If resolution > 1280x1024, expire length = 64,
1511                            else expire length = 128 */
1512                         if ((hor_active > 1280) && (ver_active > 1024))
1513                                 iga2_display_queue_expire_num = 16;
1514                         else
1515                                 iga2_display_queue_expire_num =
1516                                     CN700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1517                 }
1518
1519                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
1520                         iga2_fifo_max_depth = CX700_IGA2_FIFO_MAX_DEPTH;
1521                         iga2_fifo_threshold = CX700_IGA2_FIFO_THRESHOLD;
1522                         iga2_fifo_high_threshold =
1523                             CX700_IGA2_FIFO_HIGH_THRESHOLD;
1524                         iga2_display_queue_expire_num =
1525                             CX700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1526                 }
1527
1528                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890) {
1529                         iga2_fifo_max_depth = K8M890_IGA2_FIFO_MAX_DEPTH;
1530                         iga2_fifo_threshold = K8M890_IGA2_FIFO_THRESHOLD;
1531                         iga2_fifo_high_threshold =
1532                             K8M890_IGA2_FIFO_HIGH_THRESHOLD;
1533                         iga2_display_queue_expire_num =
1534                             K8M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1535                 }
1536
1537                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M890) {
1538                         iga2_fifo_max_depth = P4M890_IGA2_FIFO_MAX_DEPTH;
1539                         iga2_fifo_threshold = P4M890_IGA2_FIFO_THRESHOLD;
1540                         iga2_fifo_high_threshold =
1541                             P4M890_IGA2_FIFO_HIGH_THRESHOLD;
1542                         iga2_display_queue_expire_num =
1543                             P4M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1544                 }
1545
1546                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M900) {
1547                         iga2_fifo_max_depth = P4M900_IGA2_FIFO_MAX_DEPTH;
1548                         iga2_fifo_threshold = P4M900_IGA2_FIFO_THRESHOLD;
1549                         iga2_fifo_high_threshold =
1550                             P4M900_IGA2_FIFO_HIGH_THRESHOLD;
1551                         iga2_display_queue_expire_num =
1552                             P4M900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1553                 }
1554
1555                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX800) {
1556                         iga2_fifo_max_depth = VX800_IGA2_FIFO_MAX_DEPTH;
1557                         iga2_fifo_threshold = VX800_IGA2_FIFO_THRESHOLD;
1558                         iga2_fifo_high_threshold =
1559                             VX800_IGA2_FIFO_HIGH_THRESHOLD;
1560                         iga2_display_queue_expire_num =
1561                             VX800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1562                 }
1563
1564                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX855) {
1565                         iga2_fifo_max_depth = VX855_IGA2_FIFO_MAX_DEPTH;
1566                         iga2_fifo_threshold = VX855_IGA2_FIFO_THRESHOLD;
1567                         iga2_fifo_high_threshold =
1568                             VX855_IGA2_FIFO_HIGH_THRESHOLD;
1569                         iga2_display_queue_expire_num =
1570                             VX855_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1571                 }
1572
1573                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1574                         /* Set Display FIFO Depath Select */
1575                         reg_value =
1576                             IGA2_FIFO_DEPTH_SELECT_FORMULA(iga2_fifo_max_depth)
1577                             - 1;
1578                         /* Patch LCD in IGA2 case */
1579                         viafb_load_reg_num =
1580                             display_fifo_depth_reg.
1581                             iga2_fifo_depth_select_reg.reg_num;
1582                         reg =
1583                             display_fifo_depth_reg.
1584                             iga2_fifo_depth_select_reg.reg;
1585                         viafb_load_reg(reg_value,
1586                                 viafb_load_reg_num, reg, VIACR);
1587                 } else {
1588
1589                         /* Set Display FIFO Depath Select */
1590                         reg_value =
1591                             IGA2_FIFO_DEPTH_SELECT_FORMULA(iga2_fifo_max_depth);
1592                         viafb_load_reg_num =
1593                             display_fifo_depth_reg.
1594                             iga2_fifo_depth_select_reg.reg_num;
1595                         reg =
1596                             display_fifo_depth_reg.
1597                             iga2_fifo_depth_select_reg.reg;
1598                         viafb_load_reg(reg_value,
1599                                 viafb_load_reg_num, reg, VIACR);
1600                 }
1601
1602                 /* Set Display FIFO Threshold Select */
1603                 reg_value = IGA2_FIFO_THRESHOLD_FORMULA(iga2_fifo_threshold);
1604                 viafb_load_reg_num =
1605                     fifo_threshold_select_reg.
1606                     iga2_fifo_threshold_select_reg.reg_num;
1607                 reg =
1608                     fifo_threshold_select_reg.
1609                     iga2_fifo_threshold_select_reg.reg;
1610                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1611
1612                 /* Set FIFO High Threshold Select */
1613                 reg_value =
1614                     IGA2_FIFO_HIGH_THRESHOLD_FORMULA(iga2_fifo_high_threshold);
1615                 viafb_load_reg_num =
1616                     fifo_high_threshold_select_reg.
1617                     iga2_fifo_high_threshold_select_reg.reg_num;
1618                 reg =
1619                     fifo_high_threshold_select_reg.
1620                     iga2_fifo_high_threshold_select_reg.reg;
1621                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1622
1623                 /* Set Display Queue Expire Num */
1624                 reg_value =
1625                     IGA2_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA
1626                     (iga2_display_queue_expire_num);
1627                 viafb_load_reg_num =
1628                     display_queue_expire_num_reg.
1629                     iga2_display_queue_expire_num_reg.reg_num;
1630                 reg =
1631                     display_queue_expire_num_reg.
1632                     iga2_display_queue_expire_num_reg.reg;
1633                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1634
1635         }
1636
1637 }
1638
1639 static u32 cle266_encode_pll(struct pll_config pll)
1640 {
1641         return (pll.multiplier << 8)
1642                 | (pll.rshift << 6)
1643                 | pll.divisor;
1644 }
1645
1646 static u32 k800_encode_pll(struct pll_config pll)
1647 {
1648         return ((pll.divisor - 2) << 16)
1649                 | (pll.rshift << 10)
1650                 | (pll.multiplier - 2);
1651 }
1652
1653 static u32 vx855_encode_pll(struct pll_config pll)
1654 {
1655         return (pll.divisor << 16)
1656                 | (pll.rshift << 10)
1657                 | pll.multiplier;
1658 }
1659
1660 u32 viafb_get_clk_value(int clk)
1661 {
1662         u32 value = 0;
1663         int i = 0;
1664
1665         while (i < NUM_TOTAL_PLL_TABLE && clk != pll_value[i].clk)
1666                 i++;
1667
1668         if (i == NUM_TOTAL_PLL_TABLE) {
1669                 printk(KERN_WARNING "viafb_get_clk_value: PLL lookup failed!");
1670         } else {
1671                 switch (viaparinfo->chip_info->gfx_chip_name) {
1672                 case UNICHROME_CLE266:
1673                 case UNICHROME_K400:
1674                         value = cle266_encode_pll(pll_value[i].cle266_pll);
1675                         break;
1676
1677                 case UNICHROME_K800:
1678                 case UNICHROME_PM800:
1679                 case UNICHROME_CN700:
1680                         value = k800_encode_pll(pll_value[i].k800_pll);
1681                         break;
1682
1683                 case UNICHROME_CX700:
1684                 case UNICHROME_CN750:
1685                 case UNICHROME_K8M890:
1686                 case UNICHROME_P4M890:
1687                 case UNICHROME_P4M900:
1688                 case UNICHROME_VX800:
1689                         value = k800_encode_pll(pll_value[i].cx700_pll);
1690                         break;
1691
1692                 case UNICHROME_VX855:
1693                         value = vx855_encode_pll(pll_value[i].vx855_pll);
1694                         break;
1695                 }
1696         }
1697
1698         return value;
1699 }
1700
1701 /* Set VCLK*/
1702 void viafb_set_vclock(u32 clk, int set_iga)
1703 {
1704         /* H.W. Reset : ON */
1705         viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
1706
1707         if (set_iga == IGA1) {
1708                 /* Change D,N FOR VCLK */
1709                 switch (viaparinfo->chip_info->gfx_chip_name) {
1710                 case UNICHROME_CLE266:
1711                 case UNICHROME_K400:
1712                         via_write_reg(VIASR, SR46, (clk & 0x00FF));
1713                         via_write_reg(VIASR, SR47, (clk & 0xFF00) >> 8);
1714                         break;
1715
1716                 case UNICHROME_K800:
1717                 case UNICHROME_PM800:
1718                 case UNICHROME_CN700:
1719                 case UNICHROME_CX700:
1720                 case UNICHROME_CN750:
1721                 case UNICHROME_K8M890:
1722                 case UNICHROME_P4M890:
1723                 case UNICHROME_P4M900:
1724                 case UNICHROME_VX800:
1725                 case UNICHROME_VX855:
1726                         via_write_reg(VIASR, SR44, (clk & 0x0000FF));
1727                         via_write_reg(VIASR, SR45, (clk & 0x00FF00) >> 8);
1728                         via_write_reg(VIASR, SR46, (clk & 0xFF0000) >> 16);
1729                         break;
1730                 }
1731         }
1732
1733         if (set_iga == IGA2) {
1734                 /* Change D,N FOR LCK */
1735                 switch (viaparinfo->chip_info->gfx_chip_name) {
1736                 case UNICHROME_CLE266:
1737                 case UNICHROME_K400:
1738                         via_write_reg(VIASR, SR44, (clk & 0x00FF));
1739                         via_write_reg(VIASR, SR45, (clk & 0xFF00) >> 8);
1740                         break;
1741
1742                 case UNICHROME_K800:
1743                 case UNICHROME_PM800:
1744                 case UNICHROME_CN700:
1745                 case UNICHROME_CX700:
1746                 case UNICHROME_CN750:
1747                 case UNICHROME_K8M890:
1748                 case UNICHROME_P4M890:
1749                 case UNICHROME_P4M900:
1750                 case UNICHROME_VX800:
1751                 case UNICHROME_VX855:
1752                         via_write_reg(VIASR, SR4A, (clk & 0x0000FF));
1753                         via_write_reg(VIASR, SR4B, (clk & 0x00FF00) >> 8);
1754                         via_write_reg(VIASR, SR4C, (clk & 0xFF0000) >> 16);
1755                         break;
1756                 }
1757         }
1758
1759         /* H.W. Reset : OFF */
1760         viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
1761
1762         /* Reset PLL */
1763         if (set_iga == IGA1) {
1764                 viafb_write_reg_mask(SR40, VIASR, 0x02, BIT1);
1765                 viafb_write_reg_mask(SR40, VIASR, 0x00, BIT1);
1766         }
1767
1768         if (set_iga == IGA2) {
1769                 viafb_write_reg_mask(SR40, VIASR, 0x04, BIT2);
1770                 viafb_write_reg_mask(SR40, VIASR, 0x00, BIT2);
1771         }
1772
1773         /* Fire! */
1774         via_write_misc_reg_mask(0x0C, 0x0C); /* select external clock */
1775 }
1776
1777 void viafb_load_crtc_timing(struct display_timing device_timing,
1778         int set_iga)
1779 {
1780         int i;
1781         int viafb_load_reg_num = 0;
1782         int reg_value = 0;
1783         struct io_register *reg = NULL;
1784
1785         viafb_unlock_crt();
1786
1787         for (i = 0; i < 12; i++) {
1788                 if (set_iga == IGA1) {
1789                         switch (i) {
1790                         case H_TOTAL_INDEX:
1791                                 reg_value =
1792                                     IGA1_HOR_TOTAL_FORMULA(device_timing.
1793                                                            hor_total);
1794                                 viafb_load_reg_num =
1795                                         iga1_crtc_reg.hor_total.reg_num;
1796                                 reg = iga1_crtc_reg.hor_total.reg;
1797                                 break;
1798                         case H_ADDR_INDEX:
1799                                 reg_value =
1800                                     IGA1_HOR_ADDR_FORMULA(device_timing.
1801                                                           hor_addr);
1802                                 viafb_load_reg_num =
1803                                         iga1_crtc_reg.hor_addr.reg_num;
1804                                 reg = iga1_crtc_reg.hor_addr.reg;
1805                                 break;
1806                         case H_BLANK_START_INDEX:
1807                                 reg_value =
1808                                     IGA1_HOR_BLANK_START_FORMULA
1809                                     (device_timing.hor_blank_start);
1810                                 viafb_load_reg_num =
1811                                     iga1_crtc_reg.hor_blank_start.reg_num;
1812                                 reg = iga1_crtc_reg.hor_blank_start.reg;
1813                                 break;
1814                         case H_BLANK_END_INDEX:
1815                                 reg_value =
1816                                     IGA1_HOR_BLANK_END_FORMULA
1817                                     (device_timing.hor_blank_start,
1818                                      device_timing.hor_blank_end);
1819                                 viafb_load_reg_num =
1820                                     iga1_crtc_reg.hor_blank_end.reg_num;
1821                                 reg = iga1_crtc_reg.hor_blank_end.reg;
1822                                 break;
1823                         case H_SYNC_START_INDEX:
1824                                 reg_value =
1825                                     IGA1_HOR_SYNC_START_FORMULA
1826                                     (device_timing.hor_sync_start);
1827                                 viafb_load_reg_num =
1828                                     iga1_crtc_reg.hor_sync_start.reg_num;
1829                                 reg = iga1_crtc_reg.hor_sync_start.reg;
1830                                 break;
1831                         case H_SYNC_END_INDEX:
1832                                 reg_value =
1833                                     IGA1_HOR_SYNC_END_FORMULA
1834                                     (device_timing.hor_sync_start,
1835                                      device_timing.hor_sync_end);
1836                                 viafb_load_reg_num =
1837                                     iga1_crtc_reg.hor_sync_end.reg_num;
1838                                 reg = iga1_crtc_reg.hor_sync_end.reg;
1839                                 break;
1840                         case V_TOTAL_INDEX:
1841                                 reg_value =
1842                                     IGA1_VER_TOTAL_FORMULA(device_timing.
1843                                                            ver_total);
1844                                 viafb_load_reg_num =
1845                                         iga1_crtc_reg.ver_total.reg_num;
1846                                 reg = iga1_crtc_reg.ver_total.reg;
1847                                 break;
1848                         case V_ADDR_INDEX:
1849                                 reg_value =
1850                                     IGA1_VER_ADDR_FORMULA(device_timing.
1851                                                           ver_addr);
1852                                 viafb_load_reg_num =
1853                                         iga1_crtc_reg.ver_addr.reg_num;
1854                                 reg = iga1_crtc_reg.ver_addr.reg;
1855                                 break;
1856                         case V_BLANK_START_INDEX:
1857                                 reg_value =
1858                                     IGA1_VER_BLANK_START_FORMULA
1859                                     (device_timing.ver_blank_start);
1860                                 viafb_load_reg_num =
1861                                     iga1_crtc_reg.ver_blank_start.reg_num;
1862                                 reg = iga1_crtc_reg.ver_blank_start.reg;
1863                                 break;
1864                         case V_BLANK_END_INDEX:
1865                                 reg_value =
1866                                     IGA1_VER_BLANK_END_FORMULA
1867                                     (device_timing.ver_blank_start,
1868                                      device_timing.ver_blank_end);
1869                                 viafb_load_reg_num =
1870                                     iga1_crtc_reg.ver_blank_end.reg_num;
1871                                 reg = iga1_crtc_reg.ver_blank_end.reg;
1872                                 break;
1873                         case V_SYNC_START_INDEX:
1874                                 reg_value =
1875                                     IGA1_VER_SYNC_START_FORMULA
1876                                     (device_timing.ver_sync_start);
1877                                 viafb_load_reg_num =
1878                                     iga1_crtc_reg.ver_sync_start.reg_num;
1879                                 reg = iga1_crtc_reg.ver_sync_start.reg;
1880                                 break;
1881                         case V_SYNC_END_INDEX:
1882                                 reg_value =
1883                                     IGA1_VER_SYNC_END_FORMULA
1884                                     (device_timing.ver_sync_start,
1885                                      device_timing.ver_sync_end);
1886                                 viafb_load_reg_num =
1887                                     iga1_crtc_reg.ver_sync_end.reg_num;
1888                                 reg = iga1_crtc_reg.ver_sync_end.reg;
1889                                 break;
1890
1891                         }
1892                 }
1893
1894                 if (set_iga == IGA2) {
1895                         switch (i) {
1896                         case H_TOTAL_INDEX:
1897                                 reg_value =
1898                                     IGA2_HOR_TOTAL_FORMULA(device_timing.
1899                                                            hor_total);
1900                                 viafb_load_reg_num =
1901                                         iga2_crtc_reg.hor_total.reg_num;
1902                                 reg = iga2_crtc_reg.hor_total.reg;
1903                                 break;
1904                         case H_ADDR_INDEX:
1905                                 reg_value =
1906                                     IGA2_HOR_ADDR_FORMULA(device_timing.
1907                                                           hor_addr);
1908                                 viafb_load_reg_num =
1909                                         iga2_crtc_reg.hor_addr.reg_num;
1910                                 reg = iga2_crtc_reg.hor_addr.reg;
1911                                 break;
1912                         case H_BLANK_START_INDEX:
1913                                 reg_value =
1914                                     IGA2_HOR_BLANK_START_FORMULA
1915                                     (device_timing.hor_blank_start);
1916                                 viafb_load_reg_num =
1917                                     iga2_crtc_reg.hor_blank_start.reg_num;
1918                                 reg = iga2_crtc_reg.hor_blank_start.reg;
1919                                 break;
1920                         case H_BLANK_END_INDEX:
1921                                 reg_value =
1922                                     IGA2_HOR_BLANK_END_FORMULA
1923                                     (device_timing.hor_blank_start,
1924                                      device_timing.hor_blank_end);
1925                                 viafb_load_reg_num =
1926                                     iga2_crtc_reg.hor_blank_end.reg_num;
1927                                 reg = iga2_crtc_reg.hor_blank_end.reg;
1928                                 break;
1929                         case H_SYNC_START_INDEX:
1930                                 reg_value =
1931                                     IGA2_HOR_SYNC_START_FORMULA
1932                                     (device_timing.hor_sync_start);
1933                                 if (UNICHROME_CN700 <=
1934                                         viaparinfo->chip_info->gfx_chip_name)
1935                                         viafb_load_reg_num =
1936                                             iga2_crtc_reg.hor_sync_start.
1937                                             reg_num;
1938                                 else
1939                                         viafb_load_reg_num = 3;
1940                                 reg = iga2_crtc_reg.hor_sync_start.reg;
1941                                 break;
1942                         case H_SYNC_END_INDEX:
1943                                 reg_value =
1944                                     IGA2_HOR_SYNC_END_FORMULA
1945                                     (device_timing.hor_sync_start,
1946                                      device_timing.hor_sync_end);
1947                                 viafb_load_reg_num =
1948                                     iga2_crtc_reg.hor_sync_end.reg_num;
1949                                 reg = iga2_crtc_reg.hor_sync_end.reg;
1950                                 break;
1951                         case V_TOTAL_INDEX:
1952                                 reg_value =
1953                                     IGA2_VER_TOTAL_FORMULA(device_timing.
1954                                                            ver_total);
1955                                 viafb_load_reg_num =
1956                                         iga2_crtc_reg.ver_total.reg_num;
1957                                 reg = iga2_crtc_reg.ver_total.reg;
1958                                 break;
1959                         case V_ADDR_INDEX:
1960                                 reg_value =
1961                                     IGA2_VER_ADDR_FORMULA(device_timing.
1962                                                           ver_addr);
1963                                 viafb_load_reg_num =
1964                                         iga2_crtc_reg.ver_addr.reg_num;
1965                                 reg = iga2_crtc_reg.ver_addr.reg;
1966                                 break;
1967                         case V_BLANK_START_INDEX:
1968                                 reg_value =
1969                                     IGA2_VER_BLANK_START_FORMULA
1970                                     (device_timing.ver_blank_start);
1971                                 viafb_load_reg_num =
1972                                     iga2_crtc_reg.ver_blank_start.reg_num;
1973                                 reg = iga2_crtc_reg.ver_blank_start.reg;
1974                                 break;
1975                         case V_BLANK_END_INDEX:
1976                                 reg_value =
1977                                     IGA2_VER_BLANK_END_FORMULA
1978                                     (device_timing.ver_blank_start,
1979                                      device_timing.ver_blank_end);
1980                                 viafb_load_reg_num =
1981                                     iga2_crtc_reg.ver_blank_end.reg_num;
1982                                 reg = iga2_crtc_reg.ver_blank_end.reg;
1983                                 break;
1984                         case V_SYNC_START_INDEX:
1985                                 reg_value =
1986                                     IGA2_VER_SYNC_START_FORMULA
1987                                     (device_timing.ver_sync_start);
1988                                 viafb_load_reg_num =
1989                                     iga2_crtc_reg.ver_sync_start.reg_num;
1990                                 reg = iga2_crtc_reg.ver_sync_start.reg;
1991                                 break;
1992                         case V_SYNC_END_INDEX:
1993                                 reg_value =
1994                                     IGA2_VER_SYNC_END_FORMULA
1995                                     (device_timing.ver_sync_start,
1996                                      device_timing.ver_sync_end);
1997                                 viafb_load_reg_num =
1998                                     iga2_crtc_reg.ver_sync_end.reg_num;
1999                                 reg = iga2_crtc_reg.ver_sync_end.reg;
2000                                 break;
2001
2002                         }
2003                 }
2004                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
2005         }
2006
2007         viafb_lock_crt();
2008 }
2009
2010 void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
2011         struct VideoModeTable *video_mode, int bpp_byte, int set_iga)
2012 {
2013         struct display_timing crt_reg;
2014         int i;
2015         int index = 0;
2016         int h_addr, v_addr;
2017         u32 pll_D_N;
2018         u8 polarity = 0;
2019
2020         for (i = 0; i < video_mode->mode_array; i++) {
2021                 index = i;
2022
2023                 if (crt_table[i].refresh_rate == viaparinfo->
2024                         crt_setting_info->refresh_rate)
2025                         break;
2026         }
2027
2028         crt_reg = crt_table[index].crtc;
2029
2030         /* Mode 640x480 has border, but LCD/DFP didn't have border. */
2031         /* So we would delete border. */
2032         if ((viafb_LCD_ON | viafb_DVI_ON)
2033             && video_mode->crtc[0].crtc.hor_addr == 640
2034             && video_mode->crtc[0].crtc.ver_addr == 480
2035             && viaparinfo->crt_setting_info->refresh_rate == 60) {
2036                 /* The border is 8 pixels. */
2037                 crt_reg.hor_blank_start = crt_reg.hor_blank_start - 8;
2038
2039                 /* Blanking time should add left and right borders. */
2040                 crt_reg.hor_blank_end = crt_reg.hor_blank_end + 16;
2041         }
2042
2043         h_addr = crt_reg.hor_addr;
2044         v_addr = crt_reg.ver_addr;
2045
2046         /* update polarity for CRT timing */
2047         if (crt_table[index].h_sync_polarity == NEGATIVE)
2048                 polarity |= BIT6;
2049         if (crt_table[index].v_sync_polarity == NEGATIVE)
2050                 polarity |= BIT7;
2051         via_write_misc_reg_mask(polarity, BIT6 | BIT7);
2052
2053         if (set_iga == IGA1) {
2054                 viafb_unlock_crt();
2055                 viafb_write_reg(CR09, VIACR, 0x00);     /*initial CR09=0 */
2056                 viafb_write_reg_mask(CR11, VIACR, 0x00, BIT4 + BIT5 + BIT6);
2057                 viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
2058         }
2059
2060         switch (set_iga) {
2061         case IGA1:
2062                 viafb_load_crtc_timing(crt_reg, IGA1);
2063                 break;
2064         case IGA2:
2065                 viafb_load_crtc_timing(crt_reg, IGA2);
2066                 break;
2067         }
2068
2069         load_fix_bit_crtc_reg();
2070         viafb_lock_crt();
2071         viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
2072         viafb_load_fetch_count_reg(h_addr, bpp_byte, set_iga);
2073
2074         /* load FIFO */
2075         if ((viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266)
2076             && (viaparinfo->chip_info->gfx_chip_name != UNICHROME_K400))
2077                 viafb_load_FIFO_reg(set_iga, h_addr, v_addr);
2078
2079         pll_D_N = viafb_get_clk_value(crt_table[index].clk);
2080         DEBUG_MSG(KERN_INFO "PLL=%x", pll_D_N);
2081         viafb_set_vclock(pll_D_N, set_iga);
2082
2083 }
2084
2085 void __devinit viafb_init_chip_info(int chip_type)
2086 {
2087         init_gfx_chip_info(chip_type);
2088         init_tmds_chip_info();
2089         init_lvds_chip_info();
2090
2091         viaparinfo->crt_setting_info->iga_path = IGA1;
2092         viaparinfo->crt_setting_info->refresh_rate = viafb_refresh;
2093
2094         /*Set IGA path for each device */
2095         viafb_set_iga_path();
2096
2097         viaparinfo->lvds_setting_info->display_method = viafb_lcd_dsp_method;
2098         viaparinfo->lvds_setting_info->lcd_mode = viafb_lcd_mode;
2099         viaparinfo->lvds_setting_info2->display_method =
2100                 viaparinfo->lvds_setting_info->display_method;
2101         viaparinfo->lvds_setting_info2->lcd_mode =
2102                 viaparinfo->lvds_setting_info->lcd_mode;
2103 }
2104
2105 void viafb_update_device_setting(int hres, int vres,
2106         int bpp, int vmode_refresh, int flag)
2107 {
2108         if (flag == 0) {
2109                 viaparinfo->crt_setting_info->h_active = hres;
2110                 viaparinfo->crt_setting_info->v_active = vres;
2111                 viaparinfo->crt_setting_info->bpp = bpp;
2112                 viaparinfo->crt_setting_info->refresh_rate =
2113                         vmode_refresh;
2114
2115                 viaparinfo->tmds_setting_info->h_active = hres;
2116                 viaparinfo->tmds_setting_info->v_active = vres;
2117
2118                 viaparinfo->lvds_setting_info->h_active = hres;
2119                 viaparinfo->lvds_setting_info->v_active = vres;
2120                 viaparinfo->lvds_setting_info->bpp = bpp;
2121                 viaparinfo->lvds_setting_info->refresh_rate =
2122                         vmode_refresh;
2123                 viaparinfo->lvds_setting_info2->h_active = hres;
2124                 viaparinfo->lvds_setting_info2->v_active = vres;
2125                 viaparinfo->lvds_setting_info2->bpp = bpp;
2126                 viaparinfo->lvds_setting_info2->refresh_rate =
2127                         vmode_refresh;
2128         } else {
2129
2130                 if (viaparinfo->tmds_setting_info->iga_path == IGA2) {
2131                         viaparinfo->tmds_setting_info->h_active = hres;
2132                         viaparinfo->tmds_setting_info->v_active = vres;
2133                 }
2134
2135                 if (viaparinfo->lvds_setting_info->iga_path == IGA2) {
2136                         viaparinfo->lvds_setting_info->h_active = hres;
2137                         viaparinfo->lvds_setting_info->v_active = vres;
2138                         viaparinfo->lvds_setting_info->bpp = bpp;
2139                         viaparinfo->lvds_setting_info->refresh_rate =
2140                                 vmode_refresh;
2141                 }
2142                 if (IGA2 == viaparinfo->lvds_setting_info2->iga_path) {
2143                         viaparinfo->lvds_setting_info2->h_active = hres;
2144                         viaparinfo->lvds_setting_info2->v_active = vres;
2145                         viaparinfo->lvds_setting_info2->bpp = bpp;
2146                         viaparinfo->lvds_setting_info2->refresh_rate =
2147                                 vmode_refresh;
2148                 }
2149         }
2150 }
2151
2152 static void __devinit init_gfx_chip_info(int chip_type)
2153 {
2154         u8 tmp;
2155
2156         viaparinfo->chip_info->gfx_chip_name = chip_type;
2157
2158         /* Check revision of CLE266 Chip */
2159         if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
2160                 /* CR4F only define in CLE266.CX chip */
2161                 tmp = viafb_read_reg(VIACR, CR4F);
2162                 viafb_write_reg(CR4F, VIACR, 0x55);
2163                 if (viafb_read_reg(VIACR, CR4F) != 0x55)
2164                         viaparinfo->chip_info->gfx_chip_revision =
2165                         CLE266_REVISION_AX;
2166                 else
2167                         viaparinfo->chip_info->gfx_chip_revision =
2168                         CLE266_REVISION_CX;
2169                 /* restore orignal CR4F value */
2170                 viafb_write_reg(CR4F, VIACR, tmp);
2171         }
2172
2173         if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
2174                 tmp = viafb_read_reg(VIASR, SR43);
2175                 DEBUG_MSG(KERN_INFO "SR43:%X\n", tmp);
2176                 if (tmp & 0x02) {
2177                         viaparinfo->chip_info->gfx_chip_revision =
2178                                 CX700_REVISION_700M2;
2179                 } else if (tmp & 0x40) {
2180                         viaparinfo->chip_info->gfx_chip_revision =
2181                                 CX700_REVISION_700M;
2182                 } else {
2183                         viaparinfo->chip_info->gfx_chip_revision =
2184                                 CX700_REVISION_700;
2185                 }
2186         }
2187
2188         /* Determine which 2D engine we have */
2189         switch (viaparinfo->chip_info->gfx_chip_name) {
2190         case UNICHROME_VX800:
2191         case UNICHROME_VX855:
2192                 viaparinfo->chip_info->twod_engine = VIA_2D_ENG_M1;
2193                 break;
2194         case UNICHROME_K8M890:
2195         case UNICHROME_P4M900:
2196                 viaparinfo->chip_info->twod_engine = VIA_2D_ENG_H5;
2197                 break;
2198         default:
2199                 viaparinfo->chip_info->twod_engine = VIA_2D_ENG_H2;
2200                 break;
2201         }
2202 }
2203
2204 static void __devinit init_tmds_chip_info(void)
2205 {
2206         viafb_tmds_trasmitter_identify();
2207
2208         if (INTERFACE_NONE == viaparinfo->chip_info->tmds_chip_info.
2209                 output_interface) {
2210                 switch (viaparinfo->chip_info->gfx_chip_name) {
2211                 case UNICHROME_CX700:
2212                         {
2213                                 /* we should check support by hardware layout.*/
2214                                 if ((viafb_display_hardware_layout ==
2215                                      HW_LAYOUT_DVI_ONLY)
2216                                     || (viafb_display_hardware_layout ==
2217                                         HW_LAYOUT_LCD_DVI)) {
2218                                         viaparinfo->chip_info->tmds_chip_info.
2219                                             output_interface = INTERFACE_TMDS;
2220                                 } else {
2221                                         viaparinfo->chip_info->tmds_chip_info.
2222                                                 output_interface =
2223                                                 INTERFACE_NONE;
2224                                 }
2225                                 break;
2226                         }
2227                 case UNICHROME_K8M890:
2228                 case UNICHROME_P4M900:
2229                 case UNICHROME_P4M890:
2230                         /* TMDS on PCIE, we set DFPLOW as default. */
2231                         viaparinfo->chip_info->tmds_chip_info.output_interface =
2232                             INTERFACE_DFP_LOW;
2233                         break;
2234                 default:
2235                         {
2236                                 /* set DVP1 default for DVI */
2237                                 viaparinfo->chip_info->tmds_chip_info
2238                                 .output_interface = INTERFACE_DVP1;
2239                         }
2240                 }
2241         }
2242
2243         DEBUG_MSG(KERN_INFO "TMDS Chip = %d\n",
2244                   viaparinfo->chip_info->tmds_chip_info.tmds_chip_name);
2245         viafb_init_dvi_size(&viaparinfo->shared->chip_info.tmds_chip_info,
2246                 &viaparinfo->shared->tmds_setting_info);
2247 }
2248
2249 static void __devinit init_lvds_chip_info(void)
2250 {
2251         viafb_lvds_trasmitter_identify();
2252         viafb_init_lcd_size();
2253         viafb_init_lvds_output_interface(&viaparinfo->chip_info->lvds_chip_info,
2254                                    viaparinfo->lvds_setting_info);
2255         if (viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name) {
2256                 viafb_init_lvds_output_interface(&viaparinfo->chip_info->
2257                         lvds_chip_info2, viaparinfo->lvds_setting_info2);
2258         }
2259         /*If CX700,two singel LCD, we need to reassign
2260            LCD interface to different LVDS port */
2261         if ((UNICHROME_CX700 == viaparinfo->chip_info->gfx_chip_name)
2262             && (HW_LAYOUT_LCD1_LCD2 == viafb_display_hardware_layout)) {
2263                 if ((INTEGRATED_LVDS == viaparinfo->chip_info->lvds_chip_info.
2264                         lvds_chip_name) && (INTEGRATED_LVDS ==
2265                         viaparinfo->chip_info->
2266                         lvds_chip_info2.lvds_chip_name)) {
2267                         viaparinfo->chip_info->lvds_chip_info.output_interface =
2268                                 INTERFACE_LVDS0;
2269                         viaparinfo->chip_info->lvds_chip_info2.
2270                                 output_interface =
2271                             INTERFACE_LVDS1;
2272                 }
2273         }
2274
2275         DEBUG_MSG(KERN_INFO "LVDS Chip = %d\n",
2276                   viaparinfo->chip_info->lvds_chip_info.lvds_chip_name);
2277         DEBUG_MSG(KERN_INFO "LVDS1 output_interface = %d\n",
2278                   viaparinfo->chip_info->lvds_chip_info.output_interface);
2279         DEBUG_MSG(KERN_INFO "LVDS2 output_interface = %d\n",
2280                   viaparinfo->chip_info->lvds_chip_info.output_interface);
2281 }
2282
2283 void __devinit viafb_init_dac(int set_iga)
2284 {
2285         int i;
2286         u8 tmp;
2287
2288         if (set_iga == IGA1) {
2289                 /* access Primary Display's LUT */
2290                 viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0);
2291                 /* turn off LCK */
2292                 viafb_write_reg_mask(SR1B, VIASR, 0x00, BIT7 + BIT6);
2293                 for (i = 0; i < 256; i++) {
2294                         write_dac_reg(i, palLUT_table[i].red,
2295                                       palLUT_table[i].green,
2296                                       palLUT_table[i].blue);
2297                 }
2298                 /* turn on LCK */
2299                 viafb_write_reg_mask(SR1B, VIASR, 0xC0, BIT7 + BIT6);
2300         } else {
2301                 tmp = viafb_read_reg(VIACR, CR6A);
2302                 /* access Secondary Display's LUT */
2303                 viafb_write_reg_mask(CR6A, VIACR, 0x40, BIT6);
2304                 viafb_write_reg_mask(SR1A, VIASR, 0x01, BIT0);
2305                 for (i = 0; i < 256; i++) {
2306                         write_dac_reg(i, palLUT_table[i].red,
2307                                       palLUT_table[i].green,
2308                                       palLUT_table[i].blue);
2309                 }
2310                 /* set IGA1 DAC for default */
2311                 viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0);
2312                 viafb_write_reg(CR6A, VIACR, tmp);
2313         }
2314 }
2315
2316 static void device_screen_off(void)
2317 {
2318         /* turn off CRT screen (IGA1) */
2319         viafb_write_reg_mask(SR01, VIASR, 0x20, BIT5);
2320 }
2321
2322 static void device_screen_on(void)
2323 {
2324         /* turn on CRT screen (IGA1) */
2325         viafb_write_reg_mask(SR01, VIASR, 0x00, BIT5);
2326 }
2327
2328 static void set_display_channel(void)
2329 {
2330         /*If viafb_LCD2_ON, on cx700, internal lvds's information
2331         is keeped on lvds_setting_info2 */
2332         if (viafb_LCD2_ON &&
2333                 viaparinfo->lvds_setting_info2->device_lcd_dualedge) {
2334                 /* For dual channel LCD: */
2335                 /* Set to Dual LVDS channel. */
2336                 viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);
2337         } else if (viafb_LCD_ON && viafb_DVI_ON) {
2338                 /* For LCD+DFP: */
2339                 /* Set to LVDS1 + TMDS channel. */
2340                 viafb_write_reg_mask(CRD2, VIACR, 0x10, BIT4 + BIT5);
2341         } else if (viafb_DVI_ON) {
2342                 /* Set to single TMDS channel. */
2343                 viafb_write_reg_mask(CRD2, VIACR, 0x30, BIT4 + BIT5);
2344         } else if (viafb_LCD_ON) {
2345                 if (viaparinfo->lvds_setting_info->device_lcd_dualedge) {
2346                         /* For dual channel LCD: */
2347                         /* Set to Dual LVDS channel. */
2348                         viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);
2349                 } else {
2350                         /* Set to LVDS0 + LVDS1 channel. */
2351                         viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT4 + BIT5);
2352                 }
2353         }
2354 }
2355
2356 int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp,
2357         struct VideoModeTable *vmode_tbl1, int video_bpp1)
2358 {
2359         int i, j;
2360         int port;
2361         u8 value, index, mask;
2362         struct crt_mode_table *crt_timing;
2363         struct crt_mode_table *crt_timing1 = NULL;
2364
2365         device_screen_off();
2366         crt_timing = vmode_tbl->crtc;
2367
2368         if (viafb_SAMM_ON == 1) {
2369                 crt_timing1 = vmode_tbl1->crtc;
2370         }
2371
2372         inb(VIAStatus);
2373         outb(0x00, VIAAR);
2374
2375         /* Write Common Setting for Video Mode */
2376         switch (viaparinfo->chip_info->gfx_chip_name) {
2377         case UNICHROME_CLE266:
2378                 viafb_write_regx(CLE266_ModeXregs, NUM_TOTAL_CLE266_ModeXregs);
2379                 break;
2380
2381         case UNICHROME_K400:
2382                 viafb_write_regx(KM400_ModeXregs, NUM_TOTAL_KM400_ModeXregs);
2383                 break;
2384
2385         case UNICHROME_K800:
2386         case UNICHROME_PM800:
2387                 viafb_write_regx(CN400_ModeXregs, NUM_TOTAL_CN400_ModeXregs);
2388                 break;
2389
2390         case UNICHROME_CN700:
2391         case UNICHROME_K8M890:
2392         case UNICHROME_P4M890:
2393         case UNICHROME_P4M900:
2394                 viafb_write_regx(CN700_ModeXregs, NUM_TOTAL_CN700_ModeXregs);
2395                 break;
2396
2397         case UNICHROME_CX700:
2398         case UNICHROME_VX800:
2399                 viafb_write_regx(CX700_ModeXregs, NUM_TOTAL_CX700_ModeXregs);
2400                 break;
2401
2402         case UNICHROME_VX855:
2403                 viafb_write_regx(VX855_ModeXregs, NUM_TOTAL_VX855_ModeXregs);
2404                 break;
2405         }
2406
2407         device_off();
2408
2409         /* Fill VPIT Parameters */
2410         /* Write Misc Register */
2411         outb(VPIT.Misc, VIA_MISC_REG_WRITE);
2412
2413         /* Write Sequencer */
2414         for (i = 1; i <= StdSR; i++)
2415                 via_write_reg(VIASR, i, VPIT.SR[i - 1]);
2416
2417         viafb_write_reg_mask(0x15, VIASR, 0xA2, 0xA2);
2418
2419         /* Write CRTC */
2420         viafb_fill_crtc_timing(crt_timing, vmode_tbl, video_bpp / 8, IGA1);
2421
2422         /* Write Graphic Controller */
2423         for (i = 0; i < StdGR; i++)
2424                 via_write_reg(VIAGR, i, VPIT.GR[i]);
2425
2426         /* Write Attribute Controller */
2427         for (i = 0; i < StdAR; i++) {
2428                 inb(VIAStatus);
2429                 outb(i, VIAAR);
2430                 outb(VPIT.AR[i], VIAAR);
2431         }
2432
2433         inb(VIAStatus);
2434         outb(0x20, VIAAR);
2435
2436         /* Update Patch Register */
2437
2438         if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266
2439             || viaparinfo->chip_info->gfx_chip_name == UNICHROME_K400)
2440             && vmode_tbl->crtc[0].crtc.hor_addr == 1024
2441             && vmode_tbl->crtc[0].crtc.ver_addr == 768) {
2442                 for (j = 0; j < res_patch_table[0].table_length; j++) {
2443                         index = res_patch_table[0].io_reg_table[j].index;
2444                         port = res_patch_table[0].io_reg_table[j].port;
2445                         value = res_patch_table[0].io_reg_table[j].value;
2446                         mask = res_patch_table[0].io_reg_table[j].mask;
2447                         viafb_write_reg_mask(index, port, value, mask);
2448                 }
2449         }
2450
2451         via_set_primary_pitch(viafbinfo->fix.line_length);
2452         via_set_secondary_pitch(viafb_dual_fb ? viafbinfo1->fix.line_length
2453                 : viafbinfo->fix.line_length);
2454         via_set_primary_color_depth(viaparinfo->depth);
2455         via_set_secondary_color_depth(viafb_dual_fb ? viaparinfo1->depth
2456                 : viaparinfo->depth);
2457         /* Update Refresh Rate Setting */
2458
2459         /* Clear On Screen */
2460
2461         /* CRT set mode */
2462         if (viafb_CRT_ON) {
2463                 if (viafb_SAMM_ON && (viaparinfo->crt_setting_info->iga_path ==
2464                         IGA2)) {
2465                         viafb_fill_crtc_timing(crt_timing1, vmode_tbl1,
2466                                 video_bpp1 / 8,
2467                                 viaparinfo->crt_setting_info->iga_path);
2468                 } else {
2469                         viafb_fill_crtc_timing(crt_timing, vmode_tbl,
2470                                 video_bpp / 8,
2471                                 viaparinfo->crt_setting_info->iga_path);
2472                 }
2473
2474                 /* Patch if set_hres is not 8 alignment (1366) to viafb_setmode
2475                 to 8 alignment (1368),there is several pixels (2 pixels)
2476                 on right side of screen. */
2477                 if (vmode_tbl->crtc[0].crtc.hor_addr % 8) {
2478                         viafb_unlock_crt();
2479                         viafb_write_reg(CR02, VIACR,
2480                                 viafb_read_reg(VIACR, CR02) - 1);
2481                         viafb_lock_crt();
2482                 }
2483
2484                 viafb_set_output_path(DEVICE_CRT,
2485                         viaparinfo->crt_setting_info->iga_path, 0);
2486         }
2487
2488         if (viafb_DVI_ON) {
2489                 if (viafb_SAMM_ON &&
2490                         (viaparinfo->tmds_setting_info->iga_path == IGA2)) {
2491                         viafb_dvi_set_mode(viafb_get_mode
2492                                      (viaparinfo->tmds_setting_info->h_active,
2493                                       viaparinfo->tmds_setting_info->
2494                                       v_active),
2495                                      video_bpp1, viaparinfo->
2496                                      tmds_setting_info->iga_path);
2497                 } else {
2498                         viafb_dvi_set_mode(viafb_get_mode
2499                                      (viaparinfo->tmds_setting_info->h_active,
2500                                       viaparinfo->
2501                                       tmds_setting_info->v_active),
2502                                      video_bpp, viaparinfo->
2503                                      tmds_setting_info->iga_path);
2504                 }
2505
2506                 viafb_set_output_path(DEVICE_DVI,
2507                         viaparinfo->tmds_setting_info->iga_path,
2508                         viaparinfo->chip_info->tmds_chip_info.output_interface);
2509         }
2510
2511         if (viafb_LCD_ON) {
2512                 if (viafb_SAMM_ON &&
2513                         (viaparinfo->lvds_setting_info->iga_path == IGA2)) {
2514                         viaparinfo->lvds_setting_info->bpp = video_bpp1;
2515                         viafb_lcd_set_mode(crt_timing1, viaparinfo->
2516                                 lvds_setting_info,
2517                                      &viaparinfo->chip_info->lvds_chip_info);
2518                 } else {
2519                         /* IGA1 doesn't have LCD scaling, so set it center. */
2520                         if (viaparinfo->lvds_setting_info->iga_path == IGA1) {
2521                                 viaparinfo->lvds_setting_info->display_method =
2522                                     LCD_CENTERING;
2523                         }
2524                         viaparinfo->lvds_setting_info->bpp = video_bpp;
2525                         viafb_lcd_set_mode(crt_timing, viaparinfo->
2526                                 lvds_setting_info,
2527                                      &viaparinfo->chip_info->lvds_chip_info);
2528                 }
2529
2530                 viafb_set_output_path(DEVICE_LCD,
2531                         viaparinfo->lvds_setting_info->iga_path,
2532                         viaparinfo->chip_info->
2533                         lvds_chip_info.output_interface);
2534         }
2535         if (viafb_LCD2_ON) {
2536                 if (viafb_SAMM_ON &&
2537                         (viaparinfo->lvds_setting_info2->iga_path == IGA2)) {
2538                         viaparinfo->lvds_setting_info2->bpp = video_bpp1;
2539                         viafb_lcd_set_mode(crt_timing1, viaparinfo->
2540                                 lvds_setting_info2,
2541                                      &viaparinfo->chip_info->lvds_chip_info2);
2542                 } else {
2543                         /* IGA1 doesn't have LCD scaling, so set it center. */
2544                         if (viaparinfo->lvds_setting_info2->iga_path == IGA1) {
2545                                 viaparinfo->lvds_setting_info2->display_method =
2546                                     LCD_CENTERING;
2547                         }
2548                         viaparinfo->lvds_setting_info2->bpp = video_bpp;
2549                         viafb_lcd_set_mode(crt_timing, viaparinfo->
2550                                 lvds_setting_info2,
2551                                      &viaparinfo->chip_info->lvds_chip_info2);
2552                 }
2553
2554                 viafb_set_output_path(DEVICE_LCD,
2555                         viaparinfo->lvds_setting_info2->iga_path,
2556                         viaparinfo->chip_info->
2557                         lvds_chip_info2.output_interface);
2558         }
2559
2560         if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700)
2561             && (viafb_LCD_ON || viafb_DVI_ON))
2562                 set_display_channel();
2563
2564         /* If set mode normally, save resolution information for hot-plug . */
2565         if (!viafb_hotplug) {
2566                 viafb_hotplug_Xres = vmode_tbl->crtc[0].crtc.hor_addr;
2567                 viafb_hotplug_Yres = vmode_tbl->crtc[0].crtc.ver_addr;
2568                 viafb_hotplug_bpp = video_bpp;
2569                 viafb_hotplug_refresh = viafb_refresh;
2570
2571                 if (viafb_DVI_ON)
2572                         viafb_DeviceStatus = DVI_Device;
2573                 else
2574                         viafb_DeviceStatus = CRT_Device;
2575         }
2576         device_on();
2577         device_screen_on();
2578         return 1;
2579 }
2580
2581 int viafb_get_pixclock(int hres, int vres, int vmode_refresh)
2582 {
2583         int i;
2584
2585         for (i = 0; i < NUM_TOTAL_RES_MAP_REFRESH; i++) {
2586                 if ((hres == res_map_refresh_tbl[i].hres)
2587                     && (vres == res_map_refresh_tbl[i].vres)
2588                     && (vmode_refresh == res_map_refresh_tbl[i].vmode_refresh))
2589                         return res_map_refresh_tbl[i].pixclock;
2590         }
2591         return RES_640X480_60HZ_PIXCLOCK;
2592
2593 }
2594
2595 int viafb_get_refresh(int hres, int vres, u32 long_refresh)
2596 {
2597 #define REFRESH_TOLERANCE 3
2598         int i, nearest = -1, diff = REFRESH_TOLERANCE;
2599         for (i = 0; i < NUM_TOTAL_RES_MAP_REFRESH; i++) {
2600                 if ((hres == res_map_refresh_tbl[i].hres)
2601                     && (vres == res_map_refresh_tbl[i].vres)
2602                     && (diff > (abs(long_refresh -
2603                     res_map_refresh_tbl[i].vmode_refresh)))) {
2604                         diff = abs(long_refresh - res_map_refresh_tbl[i].
2605                                 vmode_refresh);
2606                         nearest = i;
2607                 }
2608         }
2609 #undef REFRESH_TOLERANCE
2610         if (nearest > 0)
2611                 return res_map_refresh_tbl[nearest].vmode_refresh;
2612         return 60;
2613 }
2614
2615 static void device_off(void)
2616 {
2617         viafb_crt_disable();
2618         viafb_dvi_disable();
2619         viafb_lcd_disable();
2620 }
2621
2622 static void device_on(void)
2623 {
2624         if (viafb_CRT_ON == 1)
2625                 viafb_crt_enable();
2626         if (viafb_DVI_ON == 1)
2627                 viafb_dvi_enable();
2628         if (viafb_LCD_ON == 1)
2629                 viafb_lcd_enable();
2630 }
2631
2632 void viafb_crt_disable(void)
2633 {
2634         viafb_write_reg_mask(CR36, VIACR, BIT5 + BIT4, BIT5 + BIT4);
2635 }
2636
2637 void viafb_crt_enable(void)
2638 {
2639         viafb_write_reg_mask(CR36, VIACR, 0x0, BIT5 + BIT4);
2640 }
2641
2642 static void enable_second_display_channel(void)
2643 {
2644         /* to enable second display channel. */
2645         viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6);
2646         viafb_write_reg_mask(CR6A, VIACR, BIT7, BIT7);
2647         viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6);
2648 }
2649
2650 void viafb_set_dpa_gfx(int output_interface, struct GFX_DPA_SETTING\
2651                                         *p_gfx_dpa_setting)
2652 {
2653         switch (output_interface) {
2654         case INTERFACE_DVP0:
2655                 {
2656                         /* DVP0 Clock Polarity and Adjust: */
2657                         viafb_write_reg_mask(CR96, VIACR,
2658                                        p_gfx_dpa_setting->DVP0, 0x0F);
2659
2660                         /* DVP0 Clock and Data Pads Driving: */
2661                         viafb_write_reg_mask(SR1E, VIASR,
2662                                        p_gfx_dpa_setting->DVP0ClockDri_S, BIT2);
2663                         viafb_write_reg_mask(SR2A, VIASR,
2664                                        p_gfx_dpa_setting->DVP0ClockDri_S1,
2665                                        BIT4);
2666                         viafb_write_reg_mask(SR1B, VIASR,
2667                                        p_gfx_dpa_setting->DVP0DataDri_S, BIT1);
2668                         viafb_write_reg_mask(SR2A, VIASR,
2669                                        p_gfx_dpa_setting->DVP0DataDri_S1, BIT5);
2670                         break;
2671                 }
2672
2673         case INTERFACE_DVP1:
2674                 {
2675                         /* DVP1 Clock Polarity and Adjust: */
2676                         viafb_write_reg_mask(CR9B, VIACR,
2677                                        p_gfx_dpa_setting->DVP1, 0x0F);
2678
2679                         /* DVP1 Clock and Data Pads Driving: */
2680                         viafb_write_reg_mask(SR65, VIASR,
2681                                        p_gfx_dpa_setting->DVP1Driving, 0x0F);
2682                         break;
2683                 }
2684
2685         case INTERFACE_DFP_HIGH:
2686                 {
2687                         viafb_write_reg_mask(CR97, VIACR,
2688                                        p_gfx_dpa_setting->DFPHigh, 0x0F);
2689                         break;
2690                 }
2691
2692         case INTERFACE_DFP_LOW:
2693                 {
2694                         viafb_write_reg_mask(CR99, VIACR,
2695                                        p_gfx_dpa_setting->DFPLow, 0x0F);
2696                         break;
2697                 }
2698
2699         case INTERFACE_DFP:
2700                 {
2701                         viafb_write_reg_mask(CR97, VIACR,
2702                                        p_gfx_dpa_setting->DFPHigh, 0x0F);
2703                         viafb_write_reg_mask(CR99, VIACR,
2704                                        p_gfx_dpa_setting->DFPLow, 0x0F);
2705                         break;
2706                 }
2707         }
2708 }
2709
2710 /*According var's xres, yres fill var's other timing information*/
2711 void viafb_fill_var_timing_info(struct fb_var_screeninfo *var, int refresh,
2712         struct VideoModeTable *vmode_tbl)
2713 {
2714         struct crt_mode_table *crt_timing = NULL;
2715         struct display_timing crt_reg;
2716         int i = 0, index = 0;
2717         crt_timing = vmode_tbl->crtc;
2718         for (i = 0; i < vmode_tbl->mode_array; i++) {
2719                 index = i;
2720                 if (crt_timing[i].refresh_rate == refresh)
2721                         break;
2722         }
2723
2724         crt_reg = crt_timing[index].crtc;
2725         var->pixclock = viafb_get_pixclock(var->xres, var->yres, refresh);
2726         var->left_margin =
2727             crt_reg.hor_total - (crt_reg.hor_sync_start + crt_reg.hor_sync_end);
2728         var->right_margin = crt_reg.hor_sync_start - crt_reg.hor_addr;
2729         var->hsync_len = crt_reg.hor_sync_end;
2730         var->upper_margin =
2731             crt_reg.ver_total - (crt_reg.ver_sync_start + crt_reg.ver_sync_end);
2732         var->lower_margin = crt_reg.ver_sync_start - crt_reg.ver_addr;
2733         var->vsync_len = crt_reg.ver_sync_end;
2734 }