drivers/video/via/hw.c

   1 /*
   2  * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
   3  * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
   4
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public
   7  * License as published by the Free Software Foundation;
   8  * either version 2, or (at your option) any later version.
   9
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
  12  * the implied warranty of MERCHANTABILITY or FITNESS FOR
  13  * A PARTICULAR PURPOSE.See the GNU General Public License
  14  * for more details.
  15
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc.,
  19  * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  20  */
  21
  22 #include <linux/via-core.h>
  23 #include "global.h"
  24
  25 static struct pll_map pll_value[] = {
  26         {25175000,
  27                 {99, 7, 3},
  28                 {85, 3, 4},     /* ignoring bit difference: 0x00008000 */
  29                 {141, 5, 4},
  30                 {141, 5, 4} },
  31         {29581000,
  32                 {33, 4, 2},
  33                 {66, 2, 4},     /* ignoring bit difference: 0x00808000 */
  34                 {166, 5, 4},    /* ignoring bit difference: 0x00008000 */
  35                 {165, 5, 4} },
  36         {26880000,
  37                 {15, 4, 1},
  38                 {30, 2, 3},     /* ignoring bit difference: 0x00808000 */
  39                 {150, 5, 4},
  40                 {150, 5, 4} },
  41         {31500000,
  42                 {53, 3, 3},     /* ignoring bit difference: 0x00008000 */
  43                 {141, 4, 4},    /* ignoring bit difference: 0x00008000 */
  44                 {176, 5, 4},
  45                 {176, 5, 4} },
  46         {31728000,
  47                 {31, 7, 1},
  48                 {177, 5, 4},    /* ignoring bit difference: 0x00008000 */
  49                 {177, 5, 4},
  50                 {142, 4, 4} },
  51         {32688000,
  52                 {73, 4, 3},
  53                 {146, 4, 4},    /* ignoring bit difference: 0x00008000 */
  54                 {183, 5, 4},
  55                 {146, 4, 4} },
  56         {36000000,
  57                 {101, 5, 3},    /* ignoring bit difference: 0x00008000 */
  58                 {161, 4, 4},    /* ignoring bit difference: 0x00008000 */
  59                 {202, 5, 4},
  60                 {161, 4, 4} },
  61         {40000000,
  62                 {89, 4, 3},
  63                 {89, 4, 3},     /* ignoring bit difference: 0x00008000 */
  64                 {112, 5, 3},
  65                 {112, 5, 3} },
  66         {41291000,
  67                 {23, 4, 1},
  68                 {69, 3, 3},     /* ignoring bit difference: 0x00008000 */
  69                 {115, 5, 3},
  70                 {115, 5, 3} },
  71         {43163000,
  72                 {121, 5, 3},
  73                 {121, 5, 3},    /* ignoring bit difference: 0x00008000 */
  74                 {121, 5, 3},
  75                 {121, 5, 3} },
  76         {45250000,
  77                 {127, 5, 3},
  78                 {127, 5, 3},    /* ignoring bit difference: 0x00808000 */
  79                 {127, 5, 3},
  80                 {127, 5, 3} },
  81         {46000000,
  82                 {90, 7, 2},
  83                 {103, 4, 3},    /* ignoring bit difference: 0x00008000 */
  84                 {129, 5, 3},
  85                 {103, 4, 3} },
  86         {46996000,
  87                 {105, 4, 3},    /* ignoring bit difference: 0x00008000 */
  88                 {131, 5, 3},    /* ignoring bit difference: 0x00808000 */
  89                 {131, 5, 3},    /* ignoring bit difference: 0x00808000 */
  90                 {105, 4, 3} },
  91         {48000000,
  92                 {67, 20, 0},
  93                 {134, 5, 3},    /* ignoring bit difference: 0x00808000 */
  94                 {134, 5, 3},
  95                 {134, 5, 3} },
  96         {48875000,
  97                 {99, 29, 0},
  98                 {82, 3, 3},     /* ignoring bit difference: 0x00808000 */
  99                 {82, 3, 3},     /* ignoring bit difference: 0x00808000 */
 100                 {137, 5, 3} },
 101         {49500000,
 102                 {83, 6, 2},
 103                 {83, 3, 3},     /* ignoring bit difference: 0x00008000 */
 104                 {138, 5, 3},
 105                 {83, 3, 3} },
 106         {52406000,
 107                 {117, 4, 3},
 108                 {117, 4, 3},    /* ignoring bit difference: 0x00008000 */
 109                 {117, 4, 3},
 110                 {88, 3, 3} },
 111         {52977000,
 112                 {37, 5, 1},
 113                 {148, 5, 3},    /* ignoring bit difference: 0x00808000 */
 114                 {148, 5, 3},
 115                 {148, 5, 3} },
 116         {56250000,
 117                 {55, 7, 1},     /* ignoring bit difference: 0x00008000 */
 118                 {126, 4, 3},    /* ignoring bit difference: 0x00008000 */
 119                 {157, 5, 3},
 120                 {157, 5, 3} },
 121         {57275000,
 122                 {0, 0, 0},
 123                 {2, 2, 0},
 124                 {2, 2, 0},
 125                 {157, 5, 3} },  /* ignoring bit difference: 0x00808000 */
 126         {60466000,
 127                 {76, 9, 1},
 128                 {169, 5, 3},    /* ignoring bit difference: 0x00808000 */
 129                 {169, 5, 3},    /* FIXED: old = {72, 2, 3} */
 130                 {169, 5, 3} },
 131         {61500000,
 132                 {86, 20, 0},
 133                 {172, 5, 3},    /* ignoring bit difference: 0x00808000 */
 134                 {172, 5, 3},
 135                 {172, 5, 3} },
 136         {65000000,
 137                 {109, 6, 2},    /* ignoring bit difference: 0x00008000 */
 138                 {109, 3, 3},    /* ignoring bit difference: 0x00008000 */
 139                 {109, 3, 3},
 140                 {109, 3, 3} },
 141         {65178000,
 142                 {91, 5, 2},
 143                 {182, 5, 3},    /* ignoring bit difference: 0x00808000 */
 144                 {109, 3, 3},
 145                 {182, 5, 3} },
 146         {66750000,
 147                 {75, 4, 2},
 148                 {150, 4, 3},    /* ignoring bit difference: 0x00808000 */
 149                 {150, 4, 3},
 150                 {112, 3, 3} },
 151         {68179000,
 152                 {19, 4, 0},
 153                 {114, 3, 3},    /* ignoring bit difference: 0x00008000 */
 154                 {190, 5, 3},
 155                 {191, 5, 3} },
 156         {69924000,
 157                 {83, 17, 0},
 158                 {195, 5, 3},    /* ignoring bit difference: 0x00808000 */
 159                 {195, 5, 3},
 160                 {195, 5, 3} },
 161         {70159000,
 162                 {98, 20, 0},
 163                 {196, 5, 3},    /* ignoring bit difference: 0x00808000 */
 164                 {196, 5, 3},
 165                 {195, 5, 3} },
 166         {72000000,
 167                 {121, 24, 0},
 168                 {161, 4, 3},    /* ignoring bit difference: 0x00808000 */
 169                 {161, 4, 3},
 170                 {161, 4, 3} },
 171         {78750000,
 172                 {33, 3, 1},
 173                 {66, 3, 2},     /* ignoring bit difference: 0x00008000 */
 174                 {110, 5, 2},
 175                 {110, 5, 2} },
 176         {80136000,
 177                 {28, 5, 0},
 178                 {68, 3, 2},     /* ignoring bit difference: 0x00008000 */
 179                 {112, 5, 2},
 180                 {112, 5, 2} },
 181         {83375000,
 182                 {93, 2, 3},
 183                 {93, 4, 2},     /* ignoring bit difference: 0x00800000 */
 184                 {93, 4, 2},     /* ignoring bit difference: 0x00800000 */
 185                 {117, 5, 2} },
 186         {83950000,
 187                 {41, 7, 0},
 188                 {117, 5, 2},    /* ignoring bit difference: 0x00008000 */
 189                 {117, 5, 2},
 190                 {117, 5, 2} },
 191         {84750000,
 192                 {118, 5, 2},
 193                 {118, 5, 2},    /* ignoring bit difference: 0x00808000 */
 194                 {118, 5, 2},
 195                 {118, 5, 2} },
 196         {85860000,
 197                 {84, 7, 1},
 198                 {120, 5, 2},    /* ignoring bit difference: 0x00808000 */
 199                 {120, 5, 2},
 200                 {118, 5, 2} },
 201         {88750000,
 202                 {31, 5, 0},
 203                 {124, 5, 2},    /* ignoring bit difference: 0x00808000 */
 204                 {174, 7, 2},    /* ignoring bit difference: 0x00808000 */
 205                 {124, 5, 2} },
 206         {94500000,
 207                 {33, 5, 0},
 208                 {132, 5, 2},    /* ignoring bit difference: 0x00008000 */
 209                 {132, 5, 2},
 210                 {132, 5, 2} },
 211         {97750000,
 212                 {82, 6, 1},
 213                 {137, 5, 2},    /* ignoring bit difference: 0x00808000 */
 214                 {137, 5, 2},
 215                 {137, 5, 2} },
 216         {101000000,
 217                 {127, 9, 1},
 218                 {141, 5, 2},    /* ignoring bit difference: 0x00808000 */
 219                 {141, 5, 2},
 220                 {141, 5, 2} },
 221         {106500000,
 222                 {119, 4, 2},
 223                 {119, 4, 2},    /* ignoring bit difference: 0x00808000 */
 224                 {119, 4, 2},
 225                 {149, 5, 2} },
 226         {108000000,
 227                 {121, 4, 2},
 228                 {121, 4, 2},    /* ignoring bit difference: 0x00808000 */
 229                 {151, 5, 2},
 230                 {151, 5, 2} },
 231         {113309000,
 232                 {95, 12, 0},
 233                 {95, 3, 2},     /* ignoring bit difference: 0x00808000 */
 234                 {95, 3, 2},
 235                 {159, 5, 2} },
 236         {118840000,
 237                 {83, 5, 1},
 238                 {166, 5, 2},    /* ignoring bit difference: 0x00808000 */
 239                 {166, 5, 2},
 240                 {166, 5, 2} },
 241         {119000000,
 242                 {108, 13, 0},
 243                 {133, 4, 2},    /* ignoring bit difference: 0x00808000 */
 244                 {133, 4, 2},
 245                 {167, 5, 2} },
 246         {121750000,
 247                 {85, 5, 1},
 248                 {170, 5, 2},    /* ignoring bit difference: 0x00808000 */
 249                 {68, 2, 2},
 250                 {0, 0, 0} },
 251         {125104000,
 252                 {53, 6, 0},     /* ignoring bit difference: 0x00008000 */
 253                 {106, 3, 2},    /* ignoring bit difference: 0x00008000 */
 254                 {175, 5, 2},
 255                 {0, 0, 0} },
 256         {135000000,
 257                 {94, 5, 1},
 258                 {28, 3, 0},     /* ignoring bit difference: 0x00804000 */
 259                 {151, 4, 2},
 260                 {189, 5, 2} },
 261         {136700000,
 262                 {115, 12, 0},
 263                 {191, 5, 2},    /* ignoring bit difference: 0x00808000 */
 264                 {191, 5, 2},
 265                 {191, 5, 2} },
 266         {138400000,
 267                 {87, 9, 0},
 268                 {116, 3, 2},    /* ignoring bit difference: 0x00808000 */
 269                 {116, 3, 2},
 270                 {194, 5, 2} },
 271         {146760000,
 272                 {103, 5, 1},
 273                 {206, 5, 2},    /* ignoring bit difference: 0x00808000 */
 274                 {206, 5, 2},
 275                 {206, 5, 2} },
 276         {153920000,
 277                 {86, 8, 0},
 278                 {86, 4, 1},     /* ignoring bit difference: 0x00808000 */
 279                 {86, 4, 1},
 280                 {86, 4, 1} },   /* FIXED: old = {84, 2, 1} */
 281         {156000000,
 282                 {109, 5, 1},
 283                 {109, 5, 1},    /* ignoring bit difference: 0x00808000 */
 284                 {109, 5, 1},
 285                 {108, 5, 1} },
 286         {157500000,
 287                 {55, 5, 0},     /* ignoring bit difference: 0x00008000 */
 288                 {22, 2, 0},     /* ignoring bit difference: 0x00802000 */
 289                 {110, 5, 1},
 290                 {110, 5, 1} },
 291         {162000000,
 292                 {113, 5, 1},
 293                 {113, 5, 1},    /* ignoring bit difference: 0x00808000 */
 294                 {113, 5, 1},
 295                 {113, 5, 1} },
 296         {187000000,
 297                 {118, 9, 0},
 298                 {131, 5, 1},    /* ignoring bit difference: 0x00808000 */
 299                 {131, 5, 1},
 300                 {131, 5, 1} },
 301         {193295000,
 302                 {108, 8, 0},
 303                 {81, 3, 1},     /* ignoring bit difference: 0x00808000 */
 304                 {135, 5, 1},
 305                 {135, 5, 1} },
 306         {202500000,
 307                 {99, 7, 0},
 308                 {85, 3, 1},     /* ignoring bit difference: 0x00808000 */
 309                 {142, 5, 1},
 310                 {142, 5, 1} },
 311         {204000000,
 312                 {100, 7, 0},
 313                 {143, 5, 1},    /* ignoring bit difference: 0x00808000 */
 314                 {143, 5, 1},
 315                 {143, 5, 1} },
 316         {218500000,
 317                 {92, 6, 0},
 318                 {153, 5, 1},    /* ignoring bit difference: 0x00808000 */
 319                 {153, 5, 1},
 320                 {153, 5, 1} },
 321         {234000000,
 322                 {98, 6, 0},
 323                 {98, 3, 1},     /* ignoring bit difference: 0x00008000 */
 324                 {98, 3, 1},
 325                 {164, 5, 1} },
 326         {267250000,
 327                 {112, 6, 0},
 328                 {112, 3, 1},    /* ignoring bit difference: 0x00808000 */
 329                 {187, 5, 1},
 330                 {187, 5, 1} },
 331         {297500000,
 332                 {102, 5, 0},    /* ignoring bit difference: 0x00008000 */
 333                 {166, 4, 1},    /* ignoring bit difference: 0x00008000 */
 334                 {208, 5, 1},
 335                 {208, 5, 1} },
 336         {74481000,
 337                 {26, 5, 0},
 338                 {125, 3, 3},    /* ignoring bit difference: 0x00808000 */
 339                 {208, 5, 3},
 340                 {209, 5, 3} },
 341         {172798000,
 342                 {121, 5, 1},
 343                 {121, 5, 1},    /* ignoring bit difference: 0x00808000 */
 344                 {121, 5, 1},
 345                 {121, 5, 1} },
 346         {122614000,
 347                 {60, 7, 0},
 348                 {137, 4, 2},    /* ignoring bit difference: 0x00808000 */
 349                 {137, 4, 2},
 350                 {172, 5, 2} },
 351         {74270000,
 352                 {83, 8, 1},
 353                 {208, 5, 3},
 354                 {208, 5, 3},
 355                 {0, 0, 0} },
 356         {148500000,
 357                 {83, 8, 0},
 358                 {208, 5, 2},
 359                 {166, 4, 2},
 360                 {208, 5, 2} }
 361 };
 362
 363 static struct fifo_depth_select display_fifo_depth_reg = {
 364         /* IGA1 FIFO Depth_Select */
 365         {IGA1_FIFO_DEPTH_SELECT_REG_NUM, {{SR17, 0, 7} } },
 366         /* IGA2 FIFO Depth_Select */
 367         {IGA2_FIFO_DEPTH_SELECT_REG_NUM,
 368          {{CR68, 4, 7}, {CR94, 7, 7}, {CR95, 7, 7} } }
 369 };
 370
 371 static struct fifo_threshold_select fifo_threshold_select_reg = {
 372         /* IGA1 FIFO Threshold Select */
 373         {IGA1_FIFO_THRESHOLD_REG_NUM, {{SR16, 0, 5}, {SR16, 7, 7} } },
 374         /* IGA2 FIFO Threshold Select */
 375         {IGA2_FIFO_THRESHOLD_REG_NUM, {{CR68, 0, 3}, {CR95, 4, 6} } }
 376 };
 377
 378 static struct fifo_high_threshold_select fifo_high_threshold_select_reg = {
 379         /* IGA1 FIFO High Threshold Select */
 380         {IGA1_FIFO_HIGH_THRESHOLD_REG_NUM, {{SR18, 0, 5}, {SR18, 7, 7} } },
 381         /* IGA2 FIFO High Threshold Select */
 382         {IGA2_FIFO_HIGH_THRESHOLD_REG_NUM, {{CR92, 0, 3}, {CR95, 0, 2} } }
 383 };
 384
 385 static struct display_queue_expire_num display_queue_expire_num_reg = {
 386         /* IGA1 Display Queue Expire Num */
 387         {IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{SR22, 0, 4} } },
 388         /* IGA2 Display Queue Expire Num */
 389         {IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{CR94, 0, 6} } }
 390 };
 391
 392 /* Definition Fetch Count Registers*/
 393 static struct fetch_count fetch_count_reg = {
 394         /* IGA1 Fetch Count Register */
 395         {IGA1_FETCH_COUNT_REG_NUM, {{SR1C, 0, 7}, {SR1D, 0, 1} } },
 396         /* IGA2 Fetch Count Register */
 397         {IGA2_FETCH_COUNT_REG_NUM, {{CR65, 0, 7}, {CR67, 2, 3} } }
 398 };
 399
 400 static struct iga1_crtc_timing iga1_crtc_reg = {
 401         /* IGA1 Horizontal Total */
 402         {IGA1_HOR_TOTAL_REG_NUM, {{CR00, 0, 7}, {CR36, 3, 3} } },
 403         /* IGA1 Horizontal Addressable Video */
 404         {IGA1_HOR_ADDR_REG_NUM, {{CR01, 0, 7} } },
 405         /* IGA1 Horizontal Blank Start */
 406         {IGA1_HOR_BLANK_START_REG_NUM, {{CR02, 0, 7} } },
 407         /* IGA1 Horizontal Blank End */
 408         {IGA1_HOR_BLANK_END_REG_NUM,
 409          {{CR03, 0, 4}, {CR05, 7, 7}, {CR33, 5, 5} } },
 410         /* IGA1 Horizontal Sync Start */
 411         {IGA1_HOR_SYNC_START_REG_NUM, {{CR04, 0, 7}, {CR33, 4, 4} } },
 412         /* IGA1 Horizontal Sync End */
 413         {IGA1_HOR_SYNC_END_REG_NUM, {{CR05, 0, 4} } },
 414         /* IGA1 Vertical Total */
 415         {IGA1_VER_TOTAL_REG_NUM,
 416          {{CR06, 0, 7}, {CR07, 0, 0}, {CR07, 5, 5}, {CR35, 0, 0} } },
 417         /* IGA1 Vertical Addressable Video */
 418         {IGA1_VER_ADDR_REG_NUM,
 419          {{CR12, 0, 7}, {CR07, 1, 1}, {CR07, 6, 6}, {CR35, 2, 2} } },
 420         /* IGA1 Vertical Blank Start */
 421         {IGA1_VER_BLANK_START_REG_NUM,
 422          {{CR15, 0, 7}, {CR07, 3, 3}, {CR09, 5, 5}, {CR35, 3, 3} } },
 423         /* IGA1 Vertical Blank End */
 424         {IGA1_VER_BLANK_END_REG_NUM, {{CR16, 0, 7} } },
 425         /* IGA1 Vertical Sync Start */
 426         {IGA1_VER_SYNC_START_REG_NUM,
 427          {{CR10, 0, 7}, {CR07, 2, 2}, {CR07, 7, 7}, {CR35, 1, 1} } },
 428         /* IGA1 Vertical Sync End */
 429         {IGA1_VER_SYNC_END_REG_NUM, {{CR11, 0, 3} } }
 430 };
 431
 432 static struct iga2_crtc_timing iga2_crtc_reg = {
 433         /* IGA2 Horizontal Total */
 434         {IGA2_HOR_TOTAL_REG_NUM, {{CR50, 0, 7}, {CR55, 0, 3} } },
 435         /* IGA2 Horizontal Addressable Video */
 436         {IGA2_HOR_ADDR_REG_NUM, {{CR51, 0, 7}, {CR55, 4, 6} } },
 437         /* IGA2 Horizontal Blank Start */
 438         {IGA2_HOR_BLANK_START_REG_NUM, {{CR52, 0, 7}, {CR54, 0, 2} } },
 439         /* IGA2 Horizontal Blank End */
 440         {IGA2_HOR_BLANK_END_REG_NUM,
 441          {{CR53, 0, 7}, {CR54, 3, 5}, {CR5D, 6, 6} } },
 442         /* IGA2 Horizontal Sync Start */
 443         {IGA2_HOR_SYNC_START_REG_NUM,
 444          {{CR56, 0, 7}, {CR54, 6, 7}, {CR5C, 7, 7}, {CR5D, 7, 7} } },
 445         /* IGA2 Horizontal Sync End */
 446         {IGA2_HOR_SYNC_END_REG_NUM, {{CR57, 0, 7}, {CR5C, 6, 6} } },
 447         /* IGA2 Vertical Total */
 448         {IGA2_VER_TOTAL_REG_NUM, {{CR58, 0, 7}, {CR5D, 0, 2} } },
 449         /* IGA2 Vertical Addressable Video */
 450         {IGA2_VER_ADDR_REG_NUM, {{CR59, 0, 7}, {CR5D, 3, 5} } },
 451         /* IGA2 Vertical Blank Start */
 452         {IGA2_VER_BLANK_START_REG_NUM, {{CR5A, 0, 7}, {CR5C, 0, 2} } },
 453         /* IGA2 Vertical Blank End */
 454         {IGA2_VER_BLANK_END_REG_NUM, {{CR5B, 0, 7}, {CR5C, 3, 5} } },
 455         /* IGA2 Vertical Sync Start */
 456         {IGA2_VER_SYNC_START_REG_NUM, {{CR5E, 0, 7}, {CR5F, 5, 7} } },
 457         /* IGA2 Vertical Sync End */
 458         {IGA2_VER_SYNC_END_REG_NUM, {{CR5F, 0, 4} } }
 459 };
 460
 461 static struct rgbLUT palLUT_table[] = {
 462         /* {R,G,B} */
 463         /* Index 0x00~0x03 */
 464         {0x00, 0x00, 0x00}, {0x00, 0x00, 0x2A}, {0x00, 0x2A, 0x00}, {0x00,
 465                                                                      0x2A,
 466                                                                      0x2A},
 467         /* Index 0x04~0x07 */
 468         {0x2A, 0x00, 0x00}, {0x2A, 0x00, 0x2A}, {0x2A, 0x15, 0x00}, {0x2A,
 469                                                                      0x2A,
 470                                                                      0x2A},
 471         /* Index 0x08~0x0B */
 472         {0x15, 0x15, 0x15}, {0x15, 0x15, 0x3F}, {0x15, 0x3F, 0x15}, {0x15,
 473                                                                      0x3F,
 474                                                                      0x3F},
 475         /* Index 0x0C~0x0F */
 476         {0x3F, 0x15, 0x15}, {0x3F, 0x15, 0x3F}, {0x3F, 0x3F, 0x15}, {0x3F,
 477                                                                      0x3F,
 478                                                                      0x3F},
 479         /* Index 0x10~0x13 */
 480         {0x00, 0x00, 0x00}, {0x05, 0x05, 0x05}, {0x08, 0x08, 0x08}, {0x0B,
 481                                                                      0x0B,
 482                                                                      0x0B},
 483         /* Index 0x14~0x17 */
 484         {0x0E, 0x0E, 0x0E}, {0x11, 0x11, 0x11}, {0x14, 0x14, 0x14}, {0x18,
 485                                                                      0x18,
 486                                                                      0x18},
 487         /* Index 0x18~0x1B */
 488         {0x1C, 0x1C, 0x1C}, {0x20, 0x20, 0x20}, {0x24, 0x24, 0x24}, {0x28,
 489                                                                      0x28,
 490                                                                      0x28},
 491         /* Index 0x1C~0x1F */
 492         {0x2D, 0x2D, 0x2D}, {0x32, 0x32, 0x32}, {0x38, 0x38, 0x38}, {0x3F,
 493                                                                      0x3F,
 494                                                                      0x3F},
 495         /* Index 0x20~0x23 */
 496         {0x00, 0x00, 0x3F}, {0x10, 0x00, 0x3F}, {0x1F, 0x00, 0x3F}, {0x2F,
 497                                                                      0x00,
 498                                                                      0x3F},
 499         /* Index 0x24~0x27 */
 500         {0x3F, 0x00, 0x3F}, {0x3F, 0x00, 0x2F}, {0x3F, 0x00, 0x1F}, {0x3F,
 501                                                                      0x00,
 502                                                                      0x10},
 503         /* Index 0x28~0x2B */
 504         {0x3F, 0x00, 0x00}, {0x3F, 0x10, 0x00}, {0x3F, 0x1F, 0x00}, {0x3F,
 505                                                                      0x2F,
 506                                                                      0x00},
 507         /* Index 0x2C~0x2F */
 508         {0x3F, 0x3F, 0x00}, {0x2F, 0x3F, 0x00}, {0x1F, 0x3F, 0x00}, {0x10,
 509                                                                      0x3F,
 510                                                                      0x00},
 511         /* Index 0x30~0x33 */
 512         {0x00, 0x3F, 0x00}, {0x00, 0x3F, 0x10}, {0x00, 0x3F, 0x1F}, {0x00,
 513                                                                      0x3F,
 514                                                                      0x2F},
 515         /* Index 0x34~0x37 */
 516         {0x00, 0x3F, 0x3F}, {0x00, 0x2F, 0x3F}, {0x00, 0x1F, 0x3F}, {0x00,
 517                                                                      0x10,
 518                                                                      0x3F},
 519         /* Index 0x38~0x3B */
 520         {0x1F, 0x1F, 0x3F}, {0x27, 0x1F, 0x3F}, {0x2F, 0x1F, 0x3F}, {0x37,
 521                                                                      0x1F,
 522                                                                      0x3F},
 523         /* Index 0x3C~0x3F */
 524         {0x3F, 0x1F, 0x3F}, {0x3F, 0x1F, 0x37}, {0x3F, 0x1F, 0x2F}, {0x3F,
 525                                                                      0x1F,
 526                                                                      0x27},
 527         /* Index 0x40~0x43 */
 528         {0x3F, 0x1F, 0x1F}, {0x3F, 0x27, 0x1F}, {0x3F, 0x2F, 0x1F}, {0x3F,
 529                                                                      0x3F,
 530                                                                      0x1F},
 531         /* Index 0x44~0x47 */
 532         {0x3F, 0x3F, 0x1F}, {0x37, 0x3F, 0x1F}, {0x2F, 0x3F, 0x1F}, {0x27,
 533                                                                      0x3F,
 534                                                                      0x1F},
 535         /* Index 0x48~0x4B */
 536         {0x1F, 0x3F, 0x1F}, {0x1F, 0x3F, 0x27}, {0x1F, 0x3F, 0x2F}, {0x1F,
 537                                                                      0x3F,
 538                                                                      0x37},
 539         /* Index 0x4C~0x4F */
 540         {0x1F, 0x3F, 0x3F}, {0x1F, 0x37, 0x3F}, {0x1F, 0x2F, 0x3F}, {0x1F,
 541                                                                      0x27,
 542                                                                      0x3F},
 543         /* Index 0x50~0x53 */
 544         {0x2D, 0x2D, 0x3F}, {0x31, 0x2D, 0x3F}, {0x36, 0x2D, 0x3F}, {0x3A,
 545                                                                      0x2D,
 546                                                                      0x3F},
 547         /* Index 0x54~0x57 */
 548         {0x3F, 0x2D, 0x3F}, {0x3F, 0x2D, 0x3A}, {0x3F, 0x2D, 0x36}, {0x3F,
 549                                                                      0x2D,
 550                                                                      0x31},
 551         /* Index 0x58~0x5B */
 552         {0x3F, 0x2D, 0x2D}, {0x3F, 0x31, 0x2D}, {0x3F, 0x36, 0x2D}, {0x3F,
 553                                                                      0x3A,
 554                                                                      0x2D},
 555         /* Index 0x5C~0x5F */
 556         {0x3F, 0x3F, 0x2D}, {0x3A, 0x3F, 0x2D}, {0x36, 0x3F, 0x2D}, {0x31,
 557                                                                      0x3F,
 558                                                                      0x2D},
 559         /* Index 0x60~0x63 */
 560         {0x2D, 0x3F, 0x2D}, {0x2D, 0x3F, 0x31}, {0x2D, 0x3F, 0x36}, {0x2D,
 561                                                                      0x3F,
 562                                                                      0x3A},
 563         /* Index 0x64~0x67 */
 564         {0x2D, 0x3F, 0x3F}, {0x2D, 0x3A, 0x3F}, {0x2D, 0x36, 0x3F}, {0x2D,
 565                                                                      0x31,
 566                                                                      0x3F},
 567         /* Index 0x68~0x6B */
 568         {0x00, 0x00, 0x1C}, {0x07, 0x00, 0x1C}, {0x0E, 0x00, 0x1C}, {0x15,
 569                                                                      0x00,
 570                                                                      0x1C},
 571         /* Index 0x6C~0x6F */
 572         {0x1C, 0x00, 0x1C}, {0x1C, 0x00, 0x15}, {0x1C, 0x00, 0x0E}, {0x1C,
 573                                                                      0x00,
 574                                                                      0x07},
 575         /* Index 0x70~0x73 */
 576         {0x1C, 0x00, 0x00}, {0x1C, 0x07, 0x00}, {0x1C, 0x0E, 0x00}, {0x1C,
 577                                                                      0x15,
 578                                                                      0x00},
 579         /* Index 0x74~0x77 */
 580         {0x1C, 0x1C, 0x00}, {0x15, 0x1C, 0x00}, {0x0E, 0x1C, 0x00}, {0x07,
 581                                                                      0x1C,
 582                                                                      0x00},
 583         /* Index 0x78~0x7B */
 584         {0x00, 0x1C, 0x00}, {0x00, 0x1C, 0x07}, {0x00, 0x1C, 0x0E}, {0x00,
 585                                                                      0x1C,
 586                                                                      0x15},
 587         /* Index 0x7C~0x7F */
 588         {0x00, 0x1C, 0x1C}, {0x00, 0x15, 0x1C}, {0x00, 0x0E, 0x1C}, {0x00,
 589                                                                      0x07,
 590                                                                      0x1C},
 591         /* Index 0x80~0x83 */
 592         {0x0E, 0x0E, 0x1C}, {0x11, 0x0E, 0x1C}, {0x15, 0x0E, 0x1C}, {0x18,
 593                                                                      0x0E,
 594                                                                      0x1C},
 595         /* Index 0x84~0x87 */
 596         {0x1C, 0x0E, 0x1C}, {0x1C, 0x0E, 0x18}, {0x1C, 0x0E, 0x15}, {0x1C,
 597                                                                      0x0E,
 598                                                                      0x11},
 599         /* Index 0x88~0x8B */
 600         {0x1C, 0x0E, 0x0E}, {0x1C, 0x11, 0x0E}, {0x1C, 0x15, 0x0E}, {0x1C,
 601                                                                      0x18,
 602                                                                      0x0E},
 603         /* Index 0x8C~0x8F */
 604         {0x1C, 0x1C, 0x0E}, {0x18, 0x1C, 0x0E}, {0x15, 0x1C, 0x0E}, {0x11,
 605                                                                      0x1C,
 606                                                                      0x0E},
 607         /* Index 0x90~0x93 */
 608         {0x0E, 0x1C, 0x0E}, {0x0E, 0x1C, 0x11}, {0x0E, 0x1C, 0x15}, {0x0E,
 609                                                                      0x1C,
 610                                                                      0x18},
 611         /* Index 0x94~0x97 */
 612         {0x0E, 0x1C, 0x1C}, {0x0E, 0x18, 0x1C}, {0x0E, 0x15, 0x1C}, {0x0E,
 613                                                                      0x11,
 614                                                                      0x1C},
 615         /* Index 0x98~0x9B */
 616         {0x14, 0x14, 0x1C}, {0x16, 0x14, 0x1C}, {0x18, 0x14, 0x1C}, {0x1A,
 617                                                                      0x14,
 618                                                                      0x1C},
 619         /* Index 0x9C~0x9F */
 620         {0x1C, 0x14, 0x1C}, {0x1C, 0x14, 0x1A}, {0x1C, 0x14, 0x18}, {0x1C,
 621                                                                      0x14,
 622                                                                      0x16},
 623         /* Index 0xA0~0xA3 */
 624         {0x1C, 0x14, 0x14}, {0x1C, 0x16, 0x14}, {0x1C, 0x18, 0x14}, {0x1C,
 625                                                                      0x1A,
 626                                                                      0x14},
 627         /* Index 0xA4~0xA7 */
 628         {0x1C, 0x1C, 0x14}, {0x1A, 0x1C, 0x14}, {0x18, 0x1C, 0x14}, {0x16,
 629                                                                      0x1C,
 630                                                                      0x14},
 631         /* Index 0xA8~0xAB */
 632         {0x14, 0x1C, 0x14}, {0x14, 0x1C, 0x16}, {0x14, 0x1C, 0x18}, {0x14,
 633                                                                      0x1C,
 634                                                                      0x1A},
 635         /* Index 0xAC~0xAF */
 636         {0x14, 0x1C, 0x1C}, {0x14, 0x1A, 0x1C}, {0x14, 0x18, 0x1C}, {0x14,
 637                                                                      0x16,
 638                                                                      0x1C},
 639         /* Index 0xB0~0xB3 */
 640         {0x00, 0x00, 0x10}, {0x04, 0x00, 0x10}, {0x08, 0x00, 0x10}, {0x0C,
 641                                                                      0x00,
 642                                                                      0x10},
 643         /* Index 0xB4~0xB7 */
 644         {0x10, 0x00, 0x10}, {0x10, 0x00, 0x0C}, {0x10, 0x00, 0x08}, {0x10,
 645                                                                      0x00,
 646                                                                      0x04},
 647         /* Index 0xB8~0xBB */
 648         {0x10, 0x00, 0x00}, {0x10, 0x04, 0x00}, {0x10, 0x08, 0x00}, {0x10,
 649                                                                      0x0C,
 650                                                                      0x00},
 651         /* Index 0xBC~0xBF */
 652         {0x10, 0x10, 0x00}, {0x0C, 0x10, 0x00}, {0x08, 0x10, 0x00}, {0x04,
 653                                                                      0x10,
 654                                                                      0x00},
 655         /* Index 0xC0~0xC3 */
 656         {0x00, 0x10, 0x00}, {0x00, 0x10, 0x04}, {0x00, 0x10, 0x08}, {0x00,
 657                                                                      0x10,
 658                                                                      0x0C},
 659         /* Index 0xC4~0xC7 */
 660         {0x00, 0x10, 0x10}, {0x00, 0x0C, 0x10}, {0x00, 0x08, 0x10}, {0x00,
 661                                                                      0x04,
 662                                                                      0x10},
 663         /* Index 0xC8~0xCB */
 664         {0x08, 0x08, 0x10}, {0x0A, 0x08, 0x10}, {0x0C, 0x08, 0x10}, {0x0E,
 665                                                                      0x08,
 666                                                                      0x10},
 667         /* Index 0xCC~0xCF */
 668         {0x10, 0x08, 0x10}, {0x10, 0x08, 0x0E}, {0x10, 0x08, 0x0C}, {0x10,
 669                                                                      0x08,
 670                                                                      0x0A},
 671         /* Index 0xD0~0xD3 */
 672         {0x10, 0x08, 0x08}, {0x10, 0x0A, 0x08}, {0x10, 0x0C, 0x08}, {0x10,
 673                                                                      0x0E,
 674                                                                      0x08},
 675         /* Index 0xD4~0xD7 */
 676         {0x10, 0x10, 0x08}, {0x0E, 0x10, 0x08}, {0x0C, 0x10, 0x08}, {0x0A,
 677                                                                      0x10,
 678                                                                      0x08},
 679         /* Index 0xD8~0xDB */
 680         {0x08, 0x10, 0x08}, {0x08, 0x10, 0x0A}, {0x08, 0x10, 0x0C}, {0x08,
 681                                                                      0x10,
 682                                                                      0x0E},
 683         /* Index 0xDC~0xDF */
 684         {0x08, 0x10, 0x10}, {0x08, 0x0E, 0x10}, {0x08, 0x0C, 0x10}, {0x08,
 685                                                                      0x0A,
 686                                                                      0x10},
 687         /* Index 0xE0~0xE3 */
 688         {0x0B, 0x0B, 0x10}, {0x0C, 0x0B, 0x10}, {0x0D, 0x0B, 0x10}, {0x0F,
 689                                                                      0x0B,
 690                                                                      0x10},
 691         /* Index 0xE4~0xE7 */
 692         {0x10, 0x0B, 0x10}, {0x10, 0x0B, 0x0F}, {0x10, 0x0B, 0x0D}, {0x10,
 693                                                                      0x0B,
 694                                                                      0x0C},
 695         /* Index 0xE8~0xEB */
 696         {0x10, 0x0B, 0x0B}, {0x10, 0x0C, 0x0B}, {0x10, 0x0D, 0x0B}, {0x10,
 697                                                                      0x0F,
 698                                                                      0x0B},
 699         /* Index 0xEC~0xEF */
 700         {0x10, 0x10, 0x0B}, {0x0F, 0x10, 0x0B}, {0x0D, 0x10, 0x0B}, {0x0C,
 701                                                                      0x10,
 702                                                                      0x0B},
 703         /* Index 0xF0~0xF3 */
 704         {0x0B, 0x10, 0x0B}, {0x0B, 0x10, 0x0C}, {0x0B, 0x10, 0x0D}, {0x0B,
 705                                                                      0x10,
 706                                                                      0x0F},
 707         /* Index 0xF4~0xF7 */
 708         {0x0B, 0x10, 0x10}, {0x0B, 0x0F, 0x10}, {0x0B, 0x0D, 0x10}, {0x0B,
 709                                                                      0x0C,
 710                                                                      0x10},
 711         /* Index 0xF8~0xFB */
 712         {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00,
 713                                                                      0x00,
 714                                                                      0x00},
 715         /* Index 0xFC~0xFF */
 716         {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00,
 717                                                                      0x00,
 718                                                                      0x00}
 719 };
 720
 721 static struct via_device_mapping device_mapping[] = {
 722         {VIA_6C, "6C"},
 723         {VIA_93, "93"},
 724         {VIA_96, "96"},
 725         {VIA_CRT, "CRT"},
 726         {VIA_DVP1, "DVP1"},
 727         {VIA_LVDS1, "LVDS1"},
 728         {VIA_LVDS2, "LVDS2"}
 729 };
 730
 731 static void load_fix_bit_crtc_reg(void);
 732 static void __devinit init_gfx_chip_info(int chip_type);
 733 static void __devinit init_tmds_chip_info(void);
 734 static void __devinit init_lvds_chip_info(void);
 735 static void device_screen_off(void);
 736 static void device_screen_on(void);
 737 static void set_display_channel(void);
 738 static void device_off(void);
 739 static void device_on(void);
 740 static void enable_second_display_channel(void);
 741 static void disable_second_display_channel(void);
 742
 743 void viafb_lock_crt(void)
 744 {
 745         viafb_write_reg_mask(CR11, VIACR, BIT7, BIT7);
 746 }
 747
 748 void viafb_unlock_crt(void)
 749 {
 750         viafb_write_reg_mask(CR11, VIACR, 0, BIT7);
 751         viafb_write_reg_mask(CR47, VIACR, 0, BIT0);
 752 }
 753
 754 void write_dac_reg(u8 index, u8 r, u8 g, u8 b)
 755 {
 756         outb(index, LUT_INDEX_WRITE);
 757         outb(r, LUT_DATA);
 758         outb(g, LUT_DATA);
 759         outb(b, LUT_DATA);
 760 }
 761
 762 static u32 get_dvi_devices(int output_interface)
 763 {
 764         switch (output_interface) {
 765         case INTERFACE_DVP0:
 766                 return VIA_96 | VIA_6C;
 767
 768         case INTERFACE_DVP1:
 769                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
 770                         return VIA_93;
 771                 else
 772                         return VIA_DVP1;
 773
 774         case INTERFACE_DFP_HIGH:
 775                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
 776                         return 0;
 777                 else
 778                         return VIA_LVDS2 | VIA_96;
 779
 780         case INTERFACE_DFP_LOW:
 781                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
 782                         return 0;
 783                 else
 784                         return VIA_DVP1 | VIA_LVDS1;
 785
 786         case INTERFACE_TMDS:
 787                 return VIA_LVDS1;
 788         }
 789
 790         return 0;
 791 }
 792
 793 static u32 get_lcd_devices(int output_interface)
 794 {
 795         switch (output_interface) {
 796         case INTERFACE_DVP0:
 797                 return VIA_96;
 798
 799         case INTERFACE_DVP1:
 800                 return VIA_DVP1;
 801
 802         case INTERFACE_DFP_HIGH:
 803                 return VIA_LVDS2 | VIA_96;
 804
 805         case INTERFACE_DFP_LOW:
 806                 return VIA_LVDS1 | VIA_DVP1;
 807
 808         case INTERFACE_DFP:
 809                 return VIA_LVDS1 | VIA_LVDS2;
 810
 811         case INTERFACE_LVDS0:
 812         case INTERFACE_LVDS0LVDS1:
 813                 return VIA_LVDS1;
 814
 815         case INTERFACE_LVDS1:
 816                 return VIA_LVDS2;
 817         }
 818
 819         return 0;
 820 }
 821
 822 /*Set IGA path for each device*/
 823 void viafb_set_iga_path(void)
 824 {
 825
 826         if (viafb_SAMM_ON == 1) {
 827                 if (viafb_CRT_ON) {
 828                         if (viafb_primary_dev == CRT_Device)
 829                                 viaparinfo->crt_setting_info->iga_path = IGA1;
 830                         else
 831                                 viaparinfo->crt_setting_info->iga_path = IGA2;
 832                 }
 833
 834                 if (viafb_DVI_ON) {
 835                         if (viafb_primary_dev == DVI_Device)
 836                                 viaparinfo->tmds_setting_info->iga_path = IGA1;
 837                         else
 838                                 viaparinfo->tmds_setting_info->iga_path = IGA2;
 839                 }
 840
 841                 if (viafb_LCD_ON) {
 842                         if (viafb_primary_dev == LCD_Device) {
 843                                 if (viafb_dual_fb &&
 844                                         (viaparinfo->chip_info->gfx_chip_name ==
 845                                         UNICHROME_CLE266)) {
 846                                         viaparinfo->
 847                                         lvds_setting_info->iga_path = IGA2;
 848                                         viaparinfo->
 849                                         crt_setting_info->iga_path = IGA1;
 850                                         viaparinfo->
 851                                         tmds_setting_info->iga_path = IGA1;
 852                                 } else
 853                                         viaparinfo->
 854                                         lvds_setting_info->iga_path = IGA1;
 855                         } else {
 856                                 viaparinfo->lvds_setting_info->iga_path = IGA2;
 857                         }
 858                 }
 859                 if (viafb_LCD2_ON) {
 860                         if (LCD2_Device == viafb_primary_dev)
 861                                 viaparinfo->lvds_setting_info2->iga_path = IGA1;
 862                         else
 863                                 viaparinfo->lvds_setting_info2->iga_path = IGA2;
 864                 }
 865         } else {
 866                 viafb_SAMM_ON = 0;
 867
 868                 if (viafb_CRT_ON && viafb_LCD_ON) {
 869                         viaparinfo->crt_setting_info->iga_path = IGA1;
 870                         viaparinfo->lvds_setting_info->iga_path = IGA2;
 871                 } else if (viafb_CRT_ON && viafb_DVI_ON) {
 872                         viaparinfo->crt_setting_info->iga_path = IGA1;
 873                         viaparinfo->tmds_setting_info->iga_path = IGA2;
 874                 } else if (viafb_LCD_ON && viafb_DVI_ON) {
 875                         viaparinfo->tmds_setting_info->iga_path = IGA1;
 876                         viaparinfo->lvds_setting_info->iga_path = IGA2;
 877                 } else if (viafb_LCD_ON && viafb_LCD2_ON) {
 878                         viaparinfo->lvds_setting_info->iga_path = IGA2;
 879                         viaparinfo->lvds_setting_info2->iga_path = IGA2;
 880                 } else if (viafb_CRT_ON) {
 881                         viaparinfo->crt_setting_info->iga_path = IGA1;
 882                 } else if (viafb_LCD_ON) {
 883                         viaparinfo->lvds_setting_info->iga_path = IGA2;
 884                 } else if (viafb_DVI_ON) {
 885                         viaparinfo->tmds_setting_info->iga_path = IGA1;
 886                 }
 887         }
 888
 889         viaparinfo->shared->iga1_devices = 0;
 890         viaparinfo->shared->iga2_devices = 0;
 891         if (viafb_CRT_ON) {
 892                 if (viaparinfo->crt_setting_info->iga_path == IGA1)
 893                         viaparinfo->shared->iga1_devices |= VIA_CRT;
 894                 else
 895                         viaparinfo->shared->iga2_devices |= VIA_CRT;
 896         }
 897
 898         if (viafb_DVI_ON) {
 899                 if (viaparinfo->tmds_setting_info->iga_path == IGA1)
 900                         viaparinfo->shared->iga1_devices |= get_dvi_devices(
 901                                 viaparinfo->chip_info->
 902                                 tmds_chip_info.output_interface);
 903                 else
 904                         viaparinfo->shared->iga2_devices |= get_dvi_devices(
 905                                 viaparinfo->chip_info->
 906                                 tmds_chip_info.output_interface);
 907         }
 908
 909         if (viafb_LCD_ON) {
 910                 if (viaparinfo->lvds_setting_info->iga_path == IGA1)
 911                         viaparinfo->shared->iga1_devices |= get_lcd_devices(
 912                                 viaparinfo->chip_info->
 913                                 lvds_chip_info.output_interface);
 914                 else
 915                         viaparinfo->shared->iga2_devices |= get_lcd_devices(
 916                                 viaparinfo->chip_info->
 917                                 lvds_chip_info.output_interface);
 918         }
 919
 920         if (viafb_LCD2_ON) {
 921                 if (viaparinfo->lvds_setting_info2->iga_path == IGA1)
 922                         viaparinfo->shared->iga1_devices |= get_lcd_devices(
 923                                 viaparinfo->chip_info->
 924                                 lvds_chip_info2.output_interface);
 925                 else
 926                         viaparinfo->shared->iga2_devices |= get_lcd_devices(
 927                                 viaparinfo->chip_info->
 928                                 lvds_chip_info2.output_interface);
 929         }
 930 }
 931
 932 static void set_color_register(u8 index, u8 red, u8 green, u8 blue)
 933 {
 934         outb(0xFF, 0x3C6); /* bit mask of palette */
 935         outb(index, 0x3C8);
 936         outb(red, 0x3C9);
 937         outb(green, 0x3C9);
 938         outb(blue, 0x3C9);
 939 }
 940
 941 void viafb_set_primary_color_register(u8 index, u8 red, u8 green, u8 blue)
 942 {
 943         viafb_write_reg_mask(0x1A, VIASR, 0x00, 0x01);
 944         set_color_register(index, red, green, blue);
 945 }
 946
 947 void viafb_set_secondary_color_register(u8 index, u8 red, u8 green, u8 blue)
 948 {
 949         viafb_write_reg_mask(0x1A, VIASR, 0x01, 0x01);
 950         set_color_register(index, red, green, blue);
 951 }
 952
 953 static void set_source_common(u8 index, u8 offset, u8 iga)
 954 {
 955         u8 value, mask = 1 << offset;
 956
 957         switch (iga) {
 958         case IGA1:
 959                 value = 0x00;
 960                 break;
 961         case IGA2:
 962                 value = mask;
 963                 break;
 964         default:
 965                 printk(KERN_WARNING "viafb: Unsupported source: %d\n", iga);
 966                 return;
 967         }
 968
 969         via_write_reg_mask(VIACR, index, value, mask);
 970 }
 971
 972 static void set_crt_source(u8 iga)
 973 {
 974         u8 value;
 975
 976         switch (iga) {
 977         case IGA1:
 978                 value = 0x00;
 979                 break;
 980         case IGA2:
 981                 value = 0x40;
 982                 break;
 983         default:
 984                 printk(KERN_WARNING "viafb: Unsupported source: %d\n", iga);
 985                 return;
 986         }
 987
 988         via_write_reg_mask(VIASR, 0x16, value, 0x40);
 989 }
 990
 991 static inline void set_6C_source(u8 iga)
 992 {
 993         set_source_common(0x6C, 7, iga);
 994 }
 995
 996 static inline void set_93_source(u8 iga)
 997 {
 998         set_source_common(0x93, 7, iga);
 999 }
1000
1001 static inline void set_96_source(u8 iga)
1002 {
1003         set_source_common(0x96, 4, iga);
1004 }
1005
1006 static inline void set_dvp1_source(u8 iga)
1007 {
1008         set_source_common(0x9B, 4, iga);
1009 }
1010
1011 static inline void set_lvds1_source(u8 iga)
1012 {
1013         set_source_common(0x99, 4, iga);
1014 }
1015
1016 static inline void set_lvds2_source(u8 iga)
1017 {
1018         set_source_common(0x97, 4, iga);
1019 }
1020
1021 void via_set_source(u32 devices, u8 iga)
1022 {
1023         if (devices & VIA_6C)
1024                 set_6C_source(iga);
1025         if (devices & VIA_93)
1026                 set_93_source(iga);
1027         if (devices & VIA_96)
1028                 set_96_source(iga);
1029         if (devices & VIA_CRT)
1030                 set_crt_source(iga);
1031         if (devices & VIA_DVP1)
1032                 set_dvp1_source(iga);
1033         if (devices & VIA_LVDS1)
1034                 set_lvds1_source(iga);
1035         if (devices & VIA_LVDS2)
1036                 set_lvds2_source(iga);
1037 }
1038
1039 static void set_crt_state(u8 state)
1040 {
1041         u8 value;
1042
1043         switch (state) {
1044         case VIA_STATE_ON:
1045                 value = 0x00;
1046                 break;
1047         case VIA_STATE_STANDBY:
1048                 value = 0x10;
1049                 break;
1050         case VIA_STATE_SUSPEND:
1051                 value = 0x20;
1052                 break;
1053         case VIA_STATE_OFF:
1054                 value = 0x30;
1055                 break;
1056         default:
1057                 return;
1058         }
1059
1060         via_write_reg_mask(VIACR, 0x36, value, 0x30);
1061 }
1062
1063 static void set_96_state(u8 state)
1064 {
1065         u8 value;
1066
1067         switch (state) {
1068         case VIA_STATE_ON:
1069                 value = 0xC0;
1070                 break;
1071         case VIA_STATE_OFF:
1072                 value = 0x00;
1073                 break;
1074         default:
1075                 return;
1076         }
1077
1078         via_write_reg_mask(VIASR, 0x1E, value, 0xC0);
1079 }
1080
1081 static void set_dvp1_state(u8 state)
1082 {
1083         u8 value;
1084
1085         switch (state) {
1086         case VIA_STATE_ON:
1087                 value = 0x30;
1088                 break;
1089         case VIA_STATE_OFF:
1090                 value = 0x00;
1091                 break;
1092         default:
1093                 return;
1094         }
1095
1096         via_write_reg_mask(VIASR, 0x1E, value, 0x30);
1097 }
1098
1099 static void set_lvds1_state(u8 state)
1100 {
1101         u8 value;
1102
1103         switch (state) {
1104         case VIA_STATE_ON:
1105                 value = 0x03;
1106                 break;
1107         case VIA_STATE_OFF:
1108                 value = 0x00;
1109                 break;
1110         default:
1111                 return;
1112         }
1113
1114         via_write_reg_mask(VIASR, 0x2A, value, 0x03);
1115 }
1116
1117 static void set_lvds2_state(u8 state)
1118 {
1119         u8 value;
1120
1121         switch (state) {
1122         case VIA_STATE_ON:
1123                 value = 0x0C;
1124                 break;
1125         case VIA_STATE_OFF:
1126                 value = 0x00;
1127                 break;
1128         default:
1129                 return;
1130         }
1131
1132         via_write_reg_mask(VIASR, 0x2A, value, 0x0C);
1133 }
1134
1135 void via_set_state(u32 devices, u8 state)
1136 {
1137         /*
1138         TODO: Can we enable/disable these devices? How?
1139         if (devices & VIA_6C)
1140         if (devices & VIA_93)
1141         */
1142         if (devices & VIA_96)
1143                 set_96_state(state);
1144         if (devices & VIA_CRT)
1145                 set_crt_state(state);
1146         if (devices & VIA_DVP1)
1147                 set_dvp1_state(state);
1148         if (devices & VIA_LVDS1)
1149                 set_lvds1_state(state);
1150         if (devices & VIA_LVDS2)
1151                 set_lvds2_state(state);
1152 }
1153
1154 u32 via_parse_odev(char *input, char **end)
1155 {
1156         char *ptr = input;
1157         u32 odev = 0;
1158         bool next = true;
1159         int i, len;
1160
1161         while (next) {
1162                 next = false;
1163                 for (i = 0; i < ARRAY_SIZE(device_mapping); i++) {
1164                         len = strlen(device_mapping[i].name);
1165                         if (!strncmp(ptr, device_mapping[i].name, len)) {
1166                                 odev |= device_mapping[i].device;
1167                                 ptr += len;
1168                                 if (*ptr == ',') {
1169                                         ptr++;
1170                                         next = true;
1171                                 }
1172                         }
1173                 }
1174         }
1175
1176         *end = ptr;
1177         return odev;
1178 }
1179
1180 void via_odev_to_seq(struct seq_file *m, u32 odev)
1181 {
1182         int i, count = 0;
1183
1184         for (i = 0; i < ARRAY_SIZE(device_mapping); i++) {
1185                 if (odev & device_mapping[i].device) {
1186                         if (count > 0)
1187                                 seq_putc(m, ',');
1188
1189                         seq_puts(m, device_mapping[i].name);
1190                         count++;
1191                 }
1192         }
1193
1194         seq_putc(m, '\n');
1195 }
1196
1197 static void load_fix_bit_crtc_reg(void)
1198 {
1199         /* always set to 1 */
1200         viafb_write_reg_mask(CR03, VIACR, 0x80, BIT7);
1201         /* line compare should set all bits = 1 (extend modes) */
1202         viafb_write_reg(CR18, VIACR, 0xff);
1203         /* line compare should set all bits = 1 (extend modes) */
1204         viafb_write_reg_mask(CR07, VIACR, 0x10, BIT4);
1205         /* line compare should set all bits = 1 (extend modes) */
1206         viafb_write_reg_mask(CR09, VIACR, 0x40, BIT6);
1207         /* line compare should set all bits = 1 (extend modes) */
1208         viafb_write_reg_mask(CR35, VIACR, 0x10, BIT4);
1209         /* line compare should set all bits = 1 (extend modes) */
1210         viafb_write_reg_mask(CR33, VIACR, 0x06, BIT0 + BIT1 + BIT2);
1211         /*viafb_write_reg_mask(CR32, VIACR, 0x01, BIT0); */
1212         /* extend mode always set to e3h */
1213         viafb_write_reg(CR17, VIACR, 0xe3);
1214         /* extend mode always set to 0h */
1215         viafb_write_reg(CR08, VIACR, 0x00);
1216         /* extend mode always set to 0h */
1217         viafb_write_reg(CR14, VIACR, 0x00);
1218
1219         /* If K8M800, enable Prefetch Mode. */
1220         if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800)
1221                 || (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890))
1222                 viafb_write_reg_mask(CR33, VIACR, 0x08, BIT3);
1223         if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
1224             && (viaparinfo->chip_info->gfx_chip_revision == CLE266_REVISION_AX))
1225                 viafb_write_reg_mask(SR1A, VIASR, 0x02, BIT1);
1226
1227 }
1228
1229 void viafb_load_reg(int timing_value, int viafb_load_reg_num,
1230         struct io_register *reg,
1231               int io_type)
1232 {
1233         int reg_mask;
1234         int bit_num = 0;
1235         int data;
1236         int i, j;
1237         int shift_next_reg;
1238         int start_index, end_index, cr_index;
1239         u16 get_bit;
1240
1241         for (i = 0; i < viafb_load_reg_num; i++) {
1242                 reg_mask = 0;
1243                 data = 0;
1244                 start_index = reg[i].start_bit;
1245                 end_index = reg[i].end_bit;
1246                 cr_index = reg[i].io_addr;
1247
1248                 shift_next_reg = bit_num;
1249                 for (j = start_index; j <= end_index; j++) {
1250                         /*if (bit_num==8) timing_value = timing_value >>8; */
1251                         reg_mask = reg_mask | (BIT0 << j);
1252                         get_bit = (timing_value & (BIT0 << bit_num));
1253                         data =
1254                             data | ((get_bit >> shift_next_reg) << start_index);
1255                         bit_num++;
1256                 }
1257                 if (io_type == VIACR)
1258                         viafb_write_reg_mask(cr_index, VIACR, data, reg_mask);
1259                 else
1260                         viafb_write_reg_mask(cr_index, VIASR, data, reg_mask);
1261         }
1262
1263 }
1264
1265 /* Write Registers */
1266 void viafb_write_regx(struct io_reg RegTable[], int ItemNum)
1267 {
1268         int i;
1269
1270         /*DEBUG_MSG(KERN_INFO "Table Size : %x!!\n",ItemNum ); */
1271
1272         for (i = 0; i < ItemNum; i++)
1273                 via_write_reg_mask(RegTable[i].port, RegTable[i].index,
1274                         RegTable[i].value, RegTable[i].mask);
1275 }
1276
1277 void viafb_load_fetch_count_reg(int h_addr, int bpp_byte, int set_iga)
1278 {
1279         int reg_value;
1280         int viafb_load_reg_num;
1281         struct io_register *reg = NULL;
1282
1283         switch (set_iga) {
1284         case IGA1:
1285                 reg_value = IGA1_FETCH_COUNT_FORMULA(h_addr, bpp_byte);
1286                 viafb_load_reg_num = fetch_count_reg.
1287                         iga1_fetch_count_reg.reg_num;
1288                 reg = fetch_count_reg.iga1_fetch_count_reg.reg;
1289                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1290                 break;
1291         case IGA2:
1292                 reg_value = IGA2_FETCH_COUNT_FORMULA(h_addr, bpp_byte);
1293                 viafb_load_reg_num = fetch_count_reg.
1294                         iga2_fetch_count_reg.reg_num;
1295                 reg = fetch_count_reg.iga2_fetch_count_reg.reg;
1296                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1297                 break;
1298         }
1299
1300 }
1301
1302 void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active)
1303 {
1304         int reg_value;
1305         int viafb_load_reg_num;
1306         struct io_register *reg = NULL;
1307         int iga1_fifo_max_depth = 0, iga1_fifo_threshold =
1308             0, iga1_fifo_high_threshold = 0, iga1_display_queue_expire_num = 0;
1309         int iga2_fifo_max_depth = 0, iga2_fifo_threshold =
1310             0, iga2_fifo_high_threshold = 0, iga2_display_queue_expire_num = 0;
1311
1312         if (set_iga == IGA1) {
1313                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1314                         iga1_fifo_max_depth = K800_IGA1_FIFO_MAX_DEPTH;
1315                         iga1_fifo_threshold = K800_IGA1_FIFO_THRESHOLD;
1316                         iga1_fifo_high_threshold =
1317                             K800_IGA1_FIFO_HIGH_THRESHOLD;
1318                         /* If resolution > 1280x1024, expire length = 64, else
1319                            expire length = 128 */
1320                         if ((hor_active > 1280) && (ver_active > 1024))
1321                                 iga1_display_queue_expire_num = 16;
1322                         else
1323                                 iga1_display_queue_expire_num =
1324                                     K800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1325
1326                 }
1327
1328                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_PM800) {
1329                         iga1_fifo_max_depth = P880_IGA1_FIFO_MAX_DEPTH;
1330                         iga1_fifo_threshold = P880_IGA1_FIFO_THRESHOLD;
1331                         iga1_fifo_high_threshold =
1332                             P880_IGA1_FIFO_HIGH_THRESHOLD;
1333                         iga1_display_queue_expire_num =
1334                             P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1335
1336                         /* If resolution > 1280x1024, expire length = 64, else
1337                            expire length = 128 */
1338                         if ((hor_active > 1280) && (ver_active > 1024))
1339                                 iga1_display_queue_expire_num = 16;
1340                         else
1341                                 iga1_display_queue_expire_num =
1342                                     P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1343                 }
1344
1345                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CN700) {
1346                         iga1_fifo_max_depth = CN700_IGA1_FIFO_MAX_DEPTH;
1347                         iga1_fifo_threshold = CN700_IGA1_FIFO_THRESHOLD;
1348                         iga1_fifo_high_threshold =
1349                             CN700_IGA1_FIFO_HIGH_THRESHOLD;
1350
1351                         /* If resolution > 1280x1024, expire length = 64,
1352                            else expire length = 128 */
1353                         if ((hor_active > 1280) && (ver_active > 1024))
1354                                 iga1_display_queue_expire_num = 16;
1355                         else
1356                                 iga1_display_queue_expire_num =
1357                                     CN700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1358                 }
1359
1360                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
1361                         iga1_fifo_max_depth = CX700_IGA1_FIFO_MAX_DEPTH;
1362                         iga1_fifo_threshold = CX700_IGA1_FIFO_THRESHOLD;
1363                         iga1_fifo_high_threshold =
1364                             CX700_IGA1_FIFO_HIGH_THRESHOLD;
1365                         iga1_display_queue_expire_num =
1366                             CX700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1367                 }
1368
1369                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890) {
1370                         iga1_fifo_max_depth = K8M890_IGA1_FIFO_MAX_DEPTH;
1371                         iga1_fifo_threshold = K8M890_IGA1_FIFO_THRESHOLD;
1372                         iga1_fifo_high_threshold =
1373                             K8M890_IGA1_FIFO_HIGH_THRESHOLD;
1374                         iga1_display_queue_expire_num =
1375                             K8M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1376                 }
1377
1378                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M890) {
1379                         iga1_fifo_max_depth = P4M890_IGA1_FIFO_MAX_DEPTH;
1380                         iga1_fifo_threshold = P4M890_IGA1_FIFO_THRESHOLD;
1381                         iga1_fifo_high_threshold =
1382                             P4M890_IGA1_FIFO_HIGH_THRESHOLD;
1383                         iga1_display_queue_expire_num =
1384                             P4M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1385                 }
1386
1387                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M900) {
1388                         iga1_fifo_max_depth = P4M900_IGA1_FIFO_MAX_DEPTH;
1389                         iga1_fifo_threshold = P4M900_IGA1_FIFO_THRESHOLD;
1390                         iga1_fifo_high_threshold =
1391                             P4M900_IGA1_FIFO_HIGH_THRESHOLD;
1392                         iga1_display_queue_expire_num =
1393                             P4M900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1394                 }
1395
1396                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX800) {
1397                         iga1_fifo_max_depth = VX800_IGA1_FIFO_MAX_DEPTH;
1398                         iga1_fifo_threshold = VX800_IGA1_FIFO_THRESHOLD;
1399                         iga1_fifo_high_threshold =
1400                             VX800_IGA1_FIFO_HIGH_THRESHOLD;
1401                         iga1_display_queue_expire_num =
1402                             VX800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1403                 }
1404
1405                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX855) {
1406                         iga1_fifo_max_depth = VX855_IGA1_FIFO_MAX_DEPTH;
1407                         iga1_fifo_threshold = VX855_IGA1_FIFO_THRESHOLD;
1408                         iga1_fifo_high_threshold =
1409                             VX855_IGA1_FIFO_HIGH_THRESHOLD;
1410                         iga1_display_queue_expire_num =
1411                             VX855_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1412                 }
1413
1414                 /* Set Display FIFO Depath Select */
1415                 reg_value = IGA1_FIFO_DEPTH_SELECT_FORMULA(iga1_fifo_max_depth);
1416                 viafb_load_reg_num =
1417                     display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg_num;
1418                 reg = display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg;
1419                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1420
1421                 /* Set Display FIFO Threshold Select */
1422                 reg_value = IGA1_FIFO_THRESHOLD_FORMULA(iga1_fifo_threshold);
1423                 viafb_load_reg_num =
1424                     fifo_threshold_select_reg.
1425                     iga1_fifo_threshold_select_reg.reg_num;
1426                 reg =
1427                     fifo_threshold_select_reg.
1428                     iga1_fifo_threshold_select_reg.reg;
1429                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1430
1431                 /* Set FIFO High Threshold Select */
1432                 reg_value =
1433                     IGA1_FIFO_HIGH_THRESHOLD_FORMULA(iga1_fifo_high_threshold);
1434                 viafb_load_reg_num =
1435                     fifo_high_threshold_select_reg.
1436                     iga1_fifo_high_threshold_select_reg.reg_num;
1437                 reg =
1438                     fifo_high_threshold_select_reg.
1439                     iga1_fifo_high_threshold_select_reg.reg;
1440                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1441
1442                 /* Set Display Queue Expire Num */
1443                 reg_value =
1444                     IGA1_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA
1445                     (iga1_display_queue_expire_num);
1446                 viafb_load_reg_num =
1447                     display_queue_expire_num_reg.
1448                     iga1_display_queue_expire_num_reg.reg_num;
1449                 reg =
1450                     display_queue_expire_num_reg.
1451                     iga1_display_queue_expire_num_reg.reg;
1452                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1453
1454         } else {
1455                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1456                         iga2_fifo_max_depth = K800_IGA2_FIFO_MAX_DEPTH;
1457                         iga2_fifo_threshold = K800_IGA2_FIFO_THRESHOLD;
1458                         iga2_fifo_high_threshold =
1459                             K800_IGA2_FIFO_HIGH_THRESHOLD;
1460
1461                         /* If resolution > 1280x1024, expire length = 64,
1462                            else  expire length = 128 */
1463                         if ((hor_active > 1280) && (ver_active > 1024))
1464                                 iga2_display_queue_expire_num = 16;
1465                         else
1466                                 iga2_display_queue_expire_num =
1467                                     K800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1468                 }
1469
1470                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_PM800) {
1471                         iga2_fifo_max_depth = P880_IGA2_FIFO_MAX_DEPTH;
1472                         iga2_fifo_threshold = P880_IGA2_FIFO_THRESHOLD;
1473                         iga2_fifo_high_threshold =
1474                             P880_IGA2_FIFO_HIGH_THRESHOLD;
1475
1476                         /* If resolution > 1280x1024, expire length = 64,
1477                            else  expire length = 128 */
1478                         if ((hor_active > 1280) && (ver_active > 1024))
1479                                 iga2_display_queue_expire_num = 16;
1480                         else
1481                                 iga2_display_queue_expire_num =
1482                                     P880_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1483                 }
1484
1485                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CN700) {
1486                         iga2_fifo_max_depth = CN700_IGA2_FIFO_MAX_DEPTH;
1487                         iga2_fifo_threshold = CN700_IGA2_FIFO_THRESHOLD;
1488                         iga2_fifo_high_threshold =
1489                             CN700_IGA2_FIFO_HIGH_THRESHOLD;
1490
1491                         /* If resolution > 1280x1024, expire length = 64,
1492                            else expire length = 128 */
1493                         if ((hor_active > 1280) && (ver_active > 1024))
1494                                 iga2_display_queue_expire_num = 16;
1495                         else
1496                                 iga2_display_queue_expire_num =
1497                                     CN700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1498                 }
1499
1500                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
1501                         iga2_fifo_max_depth = CX700_IGA2_FIFO_MAX_DEPTH;
1502                         iga2_fifo_threshold = CX700_IGA2_FIFO_THRESHOLD;
1503                         iga2_fifo_high_threshold =
1504                             CX700_IGA2_FIFO_HIGH_THRESHOLD;
1505                         iga2_display_queue_expire_num =
1506                             CX700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1507                 }
1508
1509                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890) {
1510                         iga2_fifo_max_depth = K8M890_IGA2_FIFO_MAX_DEPTH;
1511                         iga2_fifo_threshold = K8M890_IGA2_FIFO_THRESHOLD;
1512                         iga2_fifo_high_threshold =
1513                             K8M890_IGA2_FIFO_HIGH_THRESHOLD;
1514                         iga2_display_queue_expire_num =
1515                             K8M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1516                 }
1517
1518                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M890) {
1519                         iga2_fifo_max_depth = P4M890_IGA2_FIFO_MAX_DEPTH;
1520                         iga2_fifo_threshold = P4M890_IGA2_FIFO_THRESHOLD;
1521                         iga2_fifo_high_threshold =
1522                             P4M890_IGA2_FIFO_HIGH_THRESHOLD;
1523                         iga2_display_queue_expire_num =
1524                             P4M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1525                 }
1526
1527                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M900) {
1528                         iga2_fifo_max_depth = P4M900_IGA2_FIFO_MAX_DEPTH;
1529                         iga2_fifo_threshold = P4M900_IGA2_FIFO_THRESHOLD;
1530                         iga2_fifo_high_threshold =
1531                             P4M900_IGA2_FIFO_HIGH_THRESHOLD;
1532                         iga2_display_queue_expire_num =
1533                             P4M900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1534                 }
1535
1536                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX800) {
1537                         iga2_fifo_max_depth = VX800_IGA2_FIFO_MAX_DEPTH;
1538                         iga2_fifo_threshold = VX800_IGA2_FIFO_THRESHOLD;
1539                         iga2_fifo_high_threshold =
1540                             VX800_IGA2_FIFO_HIGH_THRESHOLD;
1541                         iga2_display_queue_expire_num =
1542                             VX800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1543                 }
1544
1545                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX855) {
1546                         iga2_fifo_max_depth = VX855_IGA2_FIFO_MAX_DEPTH;
1547                         iga2_fifo_threshold = VX855_IGA2_FIFO_THRESHOLD;
1548                         iga2_fifo_high_threshold =
1549                             VX855_IGA2_FIFO_HIGH_THRESHOLD;
1550                         iga2_display_queue_expire_num =
1551                             VX855_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1552                 }
1553
1554                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1555                         /* Set Display FIFO Depath Select */
1556                         reg_value =
1557                             IGA2_FIFO_DEPTH_SELECT_FORMULA(iga2_fifo_max_depth)
1558                             - 1;
1559                         /* Patch LCD in IGA2 case */
1560                         viafb_load_reg_num =
1561                             display_fifo_depth_reg.
1562                             iga2_fifo_depth_select_reg.reg_num;
1563                         reg =
1564                             display_fifo_depth_reg.
1565                             iga2_fifo_depth_select_reg.reg;
1566                         viafb_load_reg(reg_value,
1567                                 viafb_load_reg_num, reg, VIACR);
1568                 } else {
1569
1570                         /* Set Display FIFO Depath Select */
1571                         reg_value =
1572                             IGA2_FIFO_DEPTH_SELECT_FORMULA(iga2_fifo_max_depth);
1573                         viafb_load_reg_num =
1574                             display_fifo_depth_reg.
1575                             iga2_fifo_depth_select_reg.reg_num;
1576                         reg =
1577                             display_fifo_depth_reg.
1578                             iga2_fifo_depth_select_reg.reg;
1579                         viafb_load_reg(reg_value,
1580                                 viafb_load_reg_num, reg, VIACR);
1581                 }
1582
1583                 /* Set Display FIFO Threshold Select */
1584                 reg_value = IGA2_FIFO_THRESHOLD_FORMULA(iga2_fifo_threshold);
1585                 viafb_load_reg_num =
1586                     fifo_threshold_select_reg.
1587                     iga2_fifo_threshold_select_reg.reg_num;
1588                 reg =
1589                     fifo_threshold_select_reg.
1590                     iga2_fifo_threshold_select_reg.reg;
1591                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1592
1593                 /* Set FIFO High Threshold Select */
1594                 reg_value =
1595                     IGA2_FIFO_HIGH_THRESHOLD_FORMULA(iga2_fifo_high_threshold);
1596                 viafb_load_reg_num =
1597                     fifo_high_threshold_select_reg.
1598                     iga2_fifo_high_threshold_select_reg.reg_num;
1599                 reg =
1600                     fifo_high_threshold_select_reg.
1601                     iga2_fifo_high_threshold_select_reg.reg;
1602                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1603
1604                 /* Set Display Queue Expire Num */
1605                 reg_value =
1606                     IGA2_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA
1607                     (iga2_display_queue_expire_num);
1608                 viafb_load_reg_num =
1609                     display_queue_expire_num_reg.
1610                     iga2_display_queue_expire_num_reg.reg_num;
1611                 reg =
1612                     display_queue_expire_num_reg.
1613                     iga2_display_queue_expire_num_reg.reg;
1614                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1615
1616         }
1617
1618 }
1619
1620 static u32 cle266_encode_pll(struct pll_config pll)
1621 {
1622         return (pll.multiplier << 8)
1623                 | (pll.rshift << 6)
1624                 | pll.divisor;
1625 }
1626
1627 static u32 k800_encode_pll(struct pll_config pll)
1628 {
1629         return ((pll.divisor - 2) << 16)
1630                 | (pll.rshift << 10)
1631                 | (pll.multiplier - 2);
1632 }
1633
1634 static u32 vx855_encode_pll(struct pll_config pll)
1635 {
1636         return (pll.divisor << 16)
1637                 | (pll.rshift << 10)
1638                 | pll.multiplier;
1639 }
1640
1641 u32 viafb_get_clk_value(int clk)
1642 {
1643         u32 value = 0;
1644         int i = 0;
1645
1646         while (i < NUM_TOTAL_PLL_TABLE && clk != pll_value[i].clk)
1647                 i++;
1648
1649         if (i == NUM_TOTAL_PLL_TABLE) {
1650                 printk(KERN_WARNING "viafb_get_clk_value: PLL lookup failed!");
1651         } else {
1652                 switch (viaparinfo->chip_info->gfx_chip_name) {
1653                 case UNICHROME_CLE266:
1654                 case UNICHROME_K400:
1655                         value = cle266_encode_pll(pll_value[i].cle266_pll);
1656                         break;
1657
1658                 case UNICHROME_K800:
1659                 case UNICHROME_PM800:
1660                 case UNICHROME_CN700:
1661                         value = k800_encode_pll(pll_value[i].k800_pll);
1662                         break;
1663
1664                 case UNICHROME_CX700:
1665                 case UNICHROME_CN750:
1666                 case UNICHROME_K8M890:
1667                 case UNICHROME_P4M890:
1668                 case UNICHROME_P4M900:
1669                 case UNICHROME_VX800:
1670                         value = k800_encode_pll(pll_value[i].cx700_pll);
1671                         break;
1672
1673                 case UNICHROME_VX855:
1674                         value = vx855_encode_pll(pll_value[i].vx855_pll);
1675                         break;
1676                 }
1677         }
1678
1679         return value;
1680 }
1681
1682 /* Set VCLK*/
1683 void viafb_set_vclock(u32 clk, int set_iga)
1684 {
1685         /* H.W. Reset : ON */
1686         viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
1687
1688         if (set_iga == IGA1) {
1689                 /* Change D,N FOR VCLK */
1690                 switch (viaparinfo->chip_info->gfx_chip_name) {
1691                 case UNICHROME_CLE266:
1692                 case UNICHROME_K400:
1693                         via_write_reg(VIASR, SR46, (clk & 0x00FF));
1694                         via_write_reg(VIASR, SR47, (clk & 0xFF00) >> 8);
1695                         break;
1696
1697                 case UNICHROME_K800:
1698                 case UNICHROME_PM800:
1699                 case UNICHROME_CN700:
1700                 case UNICHROME_CX700:
1701                 case UNICHROME_CN750:
1702                 case UNICHROME_K8M890:
1703                 case UNICHROME_P4M890:
1704                 case UNICHROME_P4M900:
1705                 case UNICHROME_VX800:
1706                 case UNICHROME_VX855:
1707                         via_write_reg(VIASR, SR44, (clk & 0x0000FF));
1708                         via_write_reg(VIASR, SR45, (clk & 0x00FF00) >> 8);
1709                         via_write_reg(VIASR, SR46, (clk & 0xFF0000) >> 16);
1710                         break;
1711                 }
1712         }
1713
1714         if (set_iga == IGA2) {
1715                 /* Change D,N FOR LCK */
1716                 switch (viaparinfo->chip_info->gfx_chip_name) {
1717                 case UNICHROME_CLE266:
1718                 case UNICHROME_K400:
1719                         via_write_reg(VIASR, SR44, (clk & 0x00FF));
1720                         via_write_reg(VIASR, SR45, (clk & 0xFF00) >> 8);
1721                         break;
1722
1723                 case UNICHROME_K800:
1724                 case UNICHROME_PM800:
1725                 case UNICHROME_CN700:
1726                 case UNICHROME_CX700:
1727                 case UNICHROME_CN750:
1728                 case UNICHROME_K8M890:
1729                 case UNICHROME_P4M890:
1730                 case UNICHROME_P4M900:
1731                 case UNICHROME_VX800:
1732                 case UNICHROME_VX855:
1733                         via_write_reg(VIASR, SR4A, (clk & 0x0000FF));
1734                         via_write_reg(VIASR, SR4B, (clk & 0x00FF00) >> 8);
1735                         via_write_reg(VIASR, SR4C, (clk & 0xFF0000) >> 16);
1736                         break;
1737                 }
1738         }
1739
1740         /* H.W. Reset : OFF */
1741         viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
1742
1743         /* Reset PLL */
1744         if (set_iga == IGA1) {
1745                 viafb_write_reg_mask(SR40, VIASR, 0x02, BIT1);
1746                 viafb_write_reg_mask(SR40, VIASR, 0x00, BIT1);
1747         }
1748
1749         if (set_iga == IGA2) {
1750                 viafb_write_reg_mask(SR40, VIASR, 0x04, BIT2);
1751                 viafb_write_reg_mask(SR40, VIASR, 0x00, BIT2);
1752         }
1753
1754         /* Fire! */
1755         via_write_misc_reg_mask(0x0C, 0x0C); /* select external clock */
1756 }
1757
1758 void viafb_load_crtc_timing(struct display_timing device_timing,
1759         int set_iga)
1760 {
1761         int i;
1762         int viafb_load_reg_num = 0;
1763         int reg_value = 0;
1764         struct io_register *reg = NULL;
1765
1766         viafb_unlock_crt();
1767
1768         for (i = 0; i < 12; i++) {
1769                 if (set_iga == IGA1) {
1770                         switch (i) {
1771                         case H_TOTAL_INDEX:
1772                                 reg_value =
1773                                     IGA1_HOR_TOTAL_FORMULA(device_timing.
1774                                                            hor_total);
1775                                 viafb_load_reg_num =
1776                                         iga1_crtc_reg.hor_total.reg_num;
1777                                 reg = iga1_crtc_reg.hor_total.reg;
1778                                 break;
1779                         case H_ADDR_INDEX:
1780                                 reg_value =
1781                                     IGA1_HOR_ADDR_FORMULA(device_timing.
1782                                                           hor_addr);
1783                                 viafb_load_reg_num =
1784                                         iga1_crtc_reg.hor_addr.reg_num;
1785                                 reg = iga1_crtc_reg.hor_addr.reg;
1786                                 break;
1787                         case H_BLANK_START_INDEX:
1788                                 reg_value =
1789                                     IGA1_HOR_BLANK_START_FORMULA
1790                                     (device_timing.hor_blank_start);
1791                                 viafb_load_reg_num =
1792                                     iga1_crtc_reg.hor_blank_start.reg_num;
1793                                 reg = iga1_crtc_reg.hor_blank_start.reg;
1794                                 break;
1795                         case H_BLANK_END_INDEX:
1796                                 reg_value =
1797                                     IGA1_HOR_BLANK_END_FORMULA
1798                                     (device_timing.hor_blank_start,
1799                                      device_timing.hor_blank_end);
1800                                 viafb_load_reg_num =
1801                                     iga1_crtc_reg.hor_blank_end.reg_num;
1802                                 reg = iga1_crtc_reg.hor_blank_end.reg;
1803                                 break;
1804                         case H_SYNC_START_INDEX:
1805                                 reg_value =
1806                                     IGA1_HOR_SYNC_START_FORMULA
1807                                     (device_timing.hor_sync_start);
1808                                 viafb_load_reg_num =
1809                                     iga1_crtc_reg.hor_sync_start.reg_num;
1810                                 reg = iga1_crtc_reg.hor_sync_start.reg;
1811                                 break;
1812                         case H_SYNC_END_INDEX:
1813                                 reg_value =
1814                                     IGA1_HOR_SYNC_END_FORMULA
1815                                     (device_timing.hor_sync_start,
1816                                      device_timing.hor_sync_end);
1817                                 viafb_load_reg_num =
1818                                     iga1_crtc_reg.hor_sync_end.reg_num;
1819                                 reg = iga1_crtc_reg.hor_sync_end.reg;
1820                                 break;
1821                         case V_TOTAL_INDEX:
1822                                 reg_value =
1823                                     IGA1_VER_TOTAL_FORMULA(device_timing.
1824                                                            ver_total);
1825                                 viafb_load_reg_num =
1826                                         iga1_crtc_reg.ver_total.reg_num;
1827                                 reg = iga1_crtc_reg.ver_total.reg;
1828                                 break;
1829                         case V_ADDR_INDEX:
1830                                 reg_value =
1831                                     IGA1_VER_ADDR_FORMULA(device_timing.
1832                                                           ver_addr);
1833                                 viafb_load_reg_num =
1834                                         iga1_crtc_reg.ver_addr.reg_num;
1835                                 reg = iga1_crtc_reg.ver_addr.reg;
1836                                 break;
1837                         case V_BLANK_START_INDEX:
1838                                 reg_value =
1839                                     IGA1_VER_BLANK_START_FORMULA
1840                                     (device_timing.ver_blank_start);
1841                                 viafb_load_reg_num =
1842                                     iga1_crtc_reg.ver_blank_start.reg_num;
1843                                 reg = iga1_crtc_reg.ver_blank_start.reg;
1844                                 break;
1845                         case V_BLANK_END_INDEX:
1846                                 reg_value =
1847                                     IGA1_VER_BLANK_END_FORMULA
1848                                     (device_timing.ver_blank_start,
1849                                      device_timing.ver_blank_end);
1850                                 viafb_load_reg_num =
1851                                     iga1_crtc_reg.ver_blank_end.reg_num;
1852                                 reg = iga1_crtc_reg.ver_blank_end.reg;
1853                                 break;
1854                         case V_SYNC_START_INDEX:
1855                                 reg_value =
1856                                     IGA1_VER_SYNC_START_FORMULA
1857                                     (device_timing.ver_sync_start);
1858                                 viafb_load_reg_num =
1859                                     iga1_crtc_reg.ver_sync_start.reg_num;
1860                                 reg = iga1_crtc_reg.ver_sync_start.reg;
1861                                 break;
1862                         case V_SYNC_END_INDEX:
1863                                 reg_value =
1864                                     IGA1_VER_SYNC_END_FORMULA
1865                                     (device_timing.ver_sync_start,
1866                                      device_timing.ver_sync_end);
1867                                 viafb_load_reg_num =
1868                                     iga1_crtc_reg.ver_sync_end.reg_num;
1869                                 reg = iga1_crtc_reg.ver_sync_end.reg;
1870                                 break;
1871
1872                         }
1873                 }
1874
1875                 if (set_iga == IGA2) {
1876                         switch (i) {
1877                         case H_TOTAL_INDEX:
1878                                 reg_value =
1879                                     IGA2_HOR_TOTAL_FORMULA(device_timing.
1880                                                            hor_total);
1881                                 viafb_load_reg_num =
1882                                         iga2_crtc_reg.hor_total.reg_num;
1883                                 reg = iga2_crtc_reg.hor_total.reg;
1884                                 break;
1885                         case H_ADDR_INDEX:
1886                                 reg_value =
1887                                     IGA2_HOR_ADDR_FORMULA(device_timing.
1888                                                           hor_addr);
1889                                 viafb_load_reg_num =
1890                                         iga2_crtc_reg.hor_addr.reg_num;
1891                                 reg = iga2_crtc_reg.hor_addr.reg;
1892                                 break;
1893                         case H_BLANK_START_INDEX:
1894                                 reg_value =
1895                                     IGA2_HOR_BLANK_START_FORMULA
1896                                     (device_timing.hor_blank_start);
1897                                 viafb_load_reg_num =
1898                                     iga2_crtc_reg.hor_blank_start.reg_num;
1899                                 reg = iga2_crtc_reg.hor_blank_start.reg;
1900                                 break;
1901                         case H_BLANK_END_INDEX:
1902                                 reg_value =
1903                                     IGA2_HOR_BLANK_END_FORMULA
1904                                     (device_timing.hor_blank_start,
1905                                      device_timing.hor_blank_end);
1906                                 viafb_load_reg_num =
1907                                     iga2_crtc_reg.hor_blank_end.reg_num;
1908                                 reg = iga2_crtc_reg.hor_blank_end.reg;
1909                                 break;
1910                         case H_SYNC_START_INDEX:
1911                                 reg_value =
1912                                     IGA2_HOR_SYNC_START_FORMULA
1913                                     (device_timing.hor_sync_start);
1914                                 if (UNICHROME_CN700 <=
1915                                         viaparinfo->chip_info->gfx_chip_name)
1916                                         viafb_load_reg_num =
1917                                             iga2_crtc_reg.hor_sync_start.
1918                                             reg_num;
1919                                 else
1920                                         viafb_load_reg_num = 3;
1921                                 reg = iga2_crtc_reg.hor_sync_start.reg;
1922                                 break;
1923                         case H_SYNC_END_INDEX:
1924                                 reg_value =
1925                                     IGA2_HOR_SYNC_END_FORMULA
1926                                     (device_timing.hor_sync_start,
1927                                      device_timing.hor_sync_end);
1928                                 viafb_load_reg_num =
1929                                     iga2_crtc_reg.hor_sync_end.reg_num;
1930                                 reg = iga2_crtc_reg.hor_sync_end.reg;
1931                                 break;
1932                         case V_TOTAL_INDEX:
1933                                 reg_value =
1934                                     IGA2_VER_TOTAL_FORMULA(device_timing.
1935                                                            ver_total);
1936                                 viafb_load_reg_num =
1937                                         iga2_crtc_reg.ver_total.reg_num;
1938                                 reg = iga2_crtc_reg.ver_total.reg;
1939                                 break;
1940                         case V_ADDR_INDEX:
1941                                 reg_value =
1942                                     IGA2_VER_ADDR_FORMULA(device_timing.
1943                                                           ver_addr);
1944                                 viafb_load_reg_num =
1945                                         iga2_crtc_reg.ver_addr.reg_num;
1946                                 reg = iga2_crtc_reg.ver_addr.reg;
1947                                 break;
1948                         case V_BLANK_START_INDEX:
1949                                 reg_value =
1950                                     IGA2_VER_BLANK_START_FORMULA
1951                                     (device_timing.ver_blank_start);
1952                                 viafb_load_reg_num =
1953                                     iga2_crtc_reg.ver_blank_start.reg_num;
1954                                 reg = iga2_crtc_reg.ver_blank_start.reg;
1955                                 break;
1956                         case V_BLANK_END_INDEX:
1957                                 reg_value =
1958                                     IGA2_VER_BLANK_END_FORMULA
1959                                     (device_timing.ver_blank_start,
1960                                      device_timing.ver_blank_end);
1961                                 viafb_load_reg_num =
1962                                     iga2_crtc_reg.ver_blank_end.reg_num;
1963                                 reg = iga2_crtc_reg.ver_blank_end.reg;
1964                                 break;
1965                         case V_SYNC_START_INDEX:
1966                                 reg_value =
1967                                     IGA2_VER_SYNC_START_FORMULA
1968                                     (device_timing.ver_sync_start);
1969                                 viafb_load_reg_num =
1970                                     iga2_crtc_reg.ver_sync_start.reg_num;
1971                                 reg = iga2_crtc_reg.ver_sync_start.reg;
1972                                 break;
1973                         case V_SYNC_END_INDEX:
1974                                 reg_value =
1975                                     IGA2_VER_SYNC_END_FORMULA
1976                                     (device_timing.ver_sync_start,
1977                                      device_timing.ver_sync_end);
1978                                 viafb_load_reg_num =
1979                                     iga2_crtc_reg.ver_sync_end.reg_num;
1980                                 reg = iga2_crtc_reg.ver_sync_end.reg;
1981                                 break;
1982
1983                         }
1984                 }
1985                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1986         }
1987
1988         viafb_lock_crt();
1989 }
1990
1991 void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
1992         struct VideoModeTable *video_mode, int bpp_byte, int set_iga)
1993 {
1994         struct display_timing crt_reg;
1995         int i;
1996         int index = 0;
1997         int h_addr, v_addr;
1998         u32 pll_D_N;
1999         u8 polarity = 0;
2000
2001         for (i = 0; i < video_mode->mode_array; i++) {
2002                 index = i;
2003
2004                 if (crt_table[i].refresh_rate == viaparinfo->
2005                         crt_setting_info->refresh_rate)
2006                         break;
2007         }
2008
2009         crt_reg = crt_table[index].crtc;
2010
2011         /* Mode 640x480 has border, but LCD/DFP didn't have border. */
2012         /* So we would delete border. */
2013         if ((viafb_LCD_ON | viafb_DVI_ON)
2014             && video_mode->crtc[0].crtc.hor_addr == 640
2015             && video_mode->crtc[0].crtc.ver_addr == 480
2016             && viaparinfo->crt_setting_info->refresh_rate == 60) {
2017                 /* The border is 8 pixels. */
2018                 crt_reg.hor_blank_start = crt_reg.hor_blank_start - 8;
2019
2020                 /* Blanking time should add left and right borders. */
2021                 crt_reg.hor_blank_end = crt_reg.hor_blank_end + 16;
2022         }
2023
2024         h_addr = crt_reg.hor_addr;
2025         v_addr = crt_reg.ver_addr;
2026
2027         /* update polarity for CRT timing */
2028         if (crt_table[index].h_sync_polarity == NEGATIVE)
2029                 polarity |= BIT6;
2030         if (crt_table[index].v_sync_polarity == NEGATIVE)
2031                 polarity |= BIT7;
2032         via_write_misc_reg_mask(polarity, BIT6 | BIT7);
2033
2034         if (set_iga == IGA1) {
2035                 viafb_unlock_crt();
2036                 viafb_write_reg(CR09, VIACR, 0x00);     /*initial CR09=0 */
2037                 viafb_write_reg_mask(CR11, VIACR, 0x00, BIT4 + BIT5 + BIT6);
2038                 viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
2039         }
2040
2041         switch (set_iga) {
2042         case IGA1:
2043                 viafb_load_crtc_timing(crt_reg, IGA1);
2044                 break;
2045         case IGA2:
2046                 viafb_load_crtc_timing(crt_reg, IGA2);
2047                 break;
2048         }
2049
2050         load_fix_bit_crtc_reg();
2051         viafb_lock_crt();
2052         viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
2053         viafb_load_fetch_count_reg(h_addr, bpp_byte, set_iga);
2054
2055         /* load FIFO */
2056         if ((viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266)
2057             && (viaparinfo->chip_info->gfx_chip_name != UNICHROME_K400))
2058                 viafb_load_FIFO_reg(set_iga, h_addr, v_addr);
2059
2060         pll_D_N = viafb_get_clk_value(crt_table[index].clk);
2061         DEBUG_MSG(KERN_INFO "PLL=%x", pll_D_N);
2062         viafb_set_vclock(pll_D_N, set_iga);
2063
2064 }
2065
2066 void __devinit viafb_init_chip_info(int chip_type)
2067 {
2068         init_gfx_chip_info(chip_type);
2069         init_tmds_chip_info();
2070         init_lvds_chip_info();
2071
2072         viaparinfo->crt_setting_info->iga_path = IGA1;
2073         viaparinfo->crt_setting_info->refresh_rate = viafb_refresh;
2074
2075         /*Set IGA path for each device */
2076         viafb_set_iga_path();
2077
2078         viaparinfo->lvds_setting_info->display_method = viafb_lcd_dsp_method;
2079         viaparinfo->lvds_setting_info->lcd_mode = viafb_lcd_mode;
2080         viaparinfo->lvds_setting_info2->display_method =
2081                 viaparinfo->lvds_setting_info->display_method;
2082         viaparinfo->lvds_setting_info2->lcd_mode =
2083                 viaparinfo->lvds_setting_info->lcd_mode;
2084 }
2085
2086 void viafb_update_device_setting(int hres, int vres,
2087         int bpp, int vmode_refresh, int flag)
2088 {
2089         if (flag == 0) {
2090                 viaparinfo->crt_setting_info->h_active = hres;
2091                 viaparinfo->crt_setting_info->v_active = vres;
2092                 viaparinfo->crt_setting_info->bpp = bpp;
2093                 viaparinfo->crt_setting_info->refresh_rate =
2094                         vmode_refresh;
2095
2096                 viaparinfo->tmds_setting_info->h_active = hres;
2097                 viaparinfo->tmds_setting_info->v_active = vres;
2098
2099                 viaparinfo->lvds_setting_info->h_active = hres;
2100                 viaparinfo->lvds_setting_info->v_active = vres;
2101                 viaparinfo->lvds_setting_info->bpp = bpp;
2102                 viaparinfo->lvds_setting_info->refresh_rate =
2103                         vmode_refresh;
2104                 viaparinfo->lvds_setting_info2->h_active = hres;
2105                 viaparinfo->lvds_setting_info2->v_active = vres;
2106                 viaparinfo->lvds_setting_info2->bpp = bpp;
2107                 viaparinfo->lvds_setting_info2->refresh_rate =
2108                         vmode_refresh;
2109         } else {
2110
2111                 if (viaparinfo->tmds_setting_info->iga_path == IGA2) {
2112                         viaparinfo->tmds_setting_info->h_active = hres;
2113                         viaparinfo->tmds_setting_info->v_active = vres;
2114                 }
2115
2116                 if (viaparinfo->lvds_setting_info->iga_path == IGA2) {
2117                         viaparinfo->lvds_setting_info->h_active = hres;
2118                         viaparinfo->lvds_setting_info->v_active = vres;
2119                         viaparinfo->lvds_setting_info->bpp = bpp;
2120                         viaparinfo->lvds_setting_info->refresh_rate =
2121                                 vmode_refresh;
2122                 }
2123                 if (IGA2 == viaparinfo->lvds_setting_info2->iga_path) {
2124                         viaparinfo->lvds_setting_info2->h_active = hres;
2125                         viaparinfo->lvds_setting_info2->v_active = vres;
2126                         viaparinfo->lvds_setting_info2->bpp = bpp;
2127                         viaparinfo->lvds_setting_info2->refresh_rate =
2128                                 vmode_refresh;
2129                 }
2130         }
2131 }
2132
2133 static void __devinit init_gfx_chip_info(int chip_type)
2134 {
2135         u8 tmp;
2136
2137         viaparinfo->chip_info->gfx_chip_name = chip_type;
2138
2139         /* Check revision of CLE266 Chip */
2140         if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
2141                 /* CR4F only define in CLE266.CX chip */
2142                 tmp = viafb_read_reg(VIACR, CR4F);
2143                 viafb_write_reg(CR4F, VIACR, 0x55);
2144                 if (viafb_read_reg(VIACR, CR4F) != 0x55)
2145                         viaparinfo->chip_info->gfx_chip_revision =
2146                         CLE266_REVISION_AX;
2147                 else
2148                         viaparinfo->chip_info->gfx_chip_revision =
2149                         CLE266_REVISION_CX;
2150                 /* restore orignal CR4F value */
2151                 viafb_write_reg(CR4F, VIACR, tmp);
2152         }
2153
2154         if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
2155                 tmp = viafb_read_reg(VIASR, SR43);
2156                 DEBUG_MSG(KERN_INFO "SR43:%X\n", tmp);
2157                 if (tmp & 0x02) {
2158                         viaparinfo->chip_info->gfx_chip_revision =
2159                                 CX700_REVISION_700M2;
2160                 } else if (tmp & 0x40) {
2161                         viaparinfo->chip_info->gfx_chip_revision =
2162                                 CX700_REVISION_700M;
2163                 } else {
2164                         viaparinfo->chip_info->gfx_chip_revision =
2165                                 CX700_REVISION_700;
2166                 }
2167         }
2168
2169         /* Determine which 2D engine we have */
2170         switch (viaparinfo->chip_info->gfx_chip_name) {
2171         case UNICHROME_VX800:
2172         case UNICHROME_VX855:
2173                 viaparinfo->chip_info->twod_engine = VIA_2D_ENG_M1;
2174                 break;
2175         case UNICHROME_K8M890:
2176         case UNICHROME_P4M900:
2177                 viaparinfo->chip_info->twod_engine = VIA_2D_ENG_H5;
2178                 break;
2179         default:
2180                 viaparinfo->chip_info->twod_engine = VIA_2D_ENG_H2;
2181                 break;
2182         }
2183 }
2184
2185 static void __devinit init_tmds_chip_info(void)
2186 {
2187         viafb_tmds_trasmitter_identify();
2188
2189         if (INTERFACE_NONE == viaparinfo->chip_info->tmds_chip_info.
2190                 output_interface) {
2191                 switch (viaparinfo->chip_info->gfx_chip_name) {
2192                 case UNICHROME_CX700:
2193                         {
2194                                 /* we should check support by hardware layout.*/
2195                                 if ((viafb_display_hardware_layout ==
2196                                      HW_LAYOUT_DVI_ONLY)
2197                                     || (viafb_display_hardware_layout ==
2198                                         HW_LAYOUT_LCD_DVI)) {
2199                                         viaparinfo->chip_info->tmds_chip_info.
2200                                             output_interface = INTERFACE_TMDS;
2201                                 } else {
2202                                         viaparinfo->chip_info->tmds_chip_info.
2203                                                 output_interface =
2204                                                 INTERFACE_NONE;
2205                                 }
2206                                 break;
2207                         }
2208                 case UNICHROME_K8M890:
2209                 case UNICHROME_P4M900:
2210                 case UNICHROME_P4M890:
2211                         /* TMDS on PCIE, we set DFPLOW as default. */
2212                         viaparinfo->chip_info->tmds_chip_info.output_interface =
2213                             INTERFACE_DFP_LOW;
2214                         break;
2215                 default:
2216                         {
2217                                 /* set DVP1 default for DVI */
2218                                 viaparinfo->chip_info->tmds_chip_info
2219                                 .output_interface = INTERFACE_DVP1;
2220                         }
2221                 }
2222         }
2223
2224         DEBUG_MSG(KERN_INFO "TMDS Chip = %d\n",
2225                   viaparinfo->chip_info->tmds_chip_info.tmds_chip_name);
2226         viafb_init_dvi_size(&viaparinfo->shared->chip_info.tmds_chip_info,
2227                 &viaparinfo->shared->tmds_setting_info);
2228 }
2229
2230 static void __devinit init_lvds_chip_info(void)
2231 {
2232         viafb_lvds_trasmitter_identify();
2233         viafb_init_lcd_size();
2234         viafb_init_lvds_output_interface(&viaparinfo->chip_info->lvds_chip_info,
2235                                    viaparinfo->lvds_setting_info);
2236         if (viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name) {
2237                 viafb_init_lvds_output_interface(&viaparinfo->chip_info->
2238                         lvds_chip_info2, viaparinfo->lvds_setting_info2);
2239         }
2240         /*If CX700,two singel LCD, we need to reassign
2241            LCD interface to different LVDS port */
2242         if ((UNICHROME_CX700 == viaparinfo->chip_info->gfx_chip_name)
2243             && (HW_LAYOUT_LCD1_LCD2 == viafb_display_hardware_layout)) {
2244                 if ((INTEGRATED_LVDS == viaparinfo->chip_info->lvds_chip_info.
2245                         lvds_chip_name) && (INTEGRATED_LVDS ==
2246                         viaparinfo->chip_info->
2247                         lvds_chip_info2.lvds_chip_name)) {
2248                         viaparinfo->chip_info->lvds_chip_info.output_interface =
2249                                 INTERFACE_LVDS0;
2250                         viaparinfo->chip_info->lvds_chip_info2.
2251                                 output_interface =
2252                             INTERFACE_LVDS1;
2253                 }
2254         }
2255
2256         DEBUG_MSG(KERN_INFO "LVDS Chip = %d\n",
2257                   viaparinfo->chip_info->lvds_chip_info.lvds_chip_name);
2258         DEBUG_MSG(KERN_INFO "LVDS1 output_interface = %d\n",
2259                   viaparinfo->chip_info->lvds_chip_info.output_interface);
2260         DEBUG_MSG(KERN_INFO "LVDS2 output_interface = %d\n",
2261                   viaparinfo->chip_info->lvds_chip_info.output_interface);
2262 }
2263
2264 void __devinit viafb_init_dac(int set_iga)
2265 {
2266         int i;
2267         u8 tmp;
2268
2269         if (set_iga == IGA1) {
2270                 /* access Primary Display's LUT */
2271                 viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0);
2272                 /* turn off LCK */
2273                 viafb_write_reg_mask(SR1B, VIASR, 0x00, BIT7 + BIT6);
2274                 for (i = 0; i < 256; i++) {
2275                         write_dac_reg(i, palLUT_table[i].red,
2276                                       palLUT_table[i].green,
2277                                       palLUT_table[i].blue);
2278                 }
2279                 /* turn on LCK */
2280                 viafb_write_reg_mask(SR1B, VIASR, 0xC0, BIT7 + BIT6);
2281         } else {
2282                 tmp = viafb_read_reg(VIACR, CR6A);
2283                 /* access Secondary Display's LUT */
2284                 viafb_write_reg_mask(CR6A, VIACR, 0x40, BIT6);
2285                 viafb_write_reg_mask(SR1A, VIASR, 0x01, BIT0);
2286                 for (i = 0; i < 256; i++) {
2287                         write_dac_reg(i, palLUT_table[i].red,
2288                                       palLUT_table[i].green,
2289                                       palLUT_table[i].blue);
2290                 }
2291                 /* set IGA1 DAC for default */
2292                 viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0);
2293                 viafb_write_reg(CR6A, VIACR, tmp);
2294         }
2295 }
2296
2297 static void device_screen_off(void)
2298 {
2299         /* turn off CRT screen (IGA1) */
2300         viafb_write_reg_mask(SR01, VIASR, 0x20, BIT5);
2301 }
2302
2303 static void device_screen_on(void)
2304 {
2305         /* turn on CRT screen (IGA1) */
2306         viafb_write_reg_mask(SR01, VIASR, 0x00, BIT5);
2307 }
2308
2309 static void set_display_channel(void)
2310 {
2311         /*If viafb_LCD2_ON, on cx700, internal lvds's information
2312         is keeped on lvds_setting_info2 */
2313         if (viafb_LCD2_ON &&
2314                 viaparinfo->lvds_setting_info2->device_lcd_dualedge) {
2315                 /* For dual channel LCD: */
2316                 /* Set to Dual LVDS channel. */
2317                 viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);
2318         } else if (viafb_LCD_ON && viafb_DVI_ON) {
2319                 /* For LCD+DFP: */
2320                 /* Set to LVDS1 + TMDS channel. */
2321                 viafb_write_reg_mask(CRD2, VIACR, 0x10, BIT4 + BIT5);
2322         } else if (viafb_DVI_ON) {
2323                 /* Set to single TMDS channel. */
2324                 viafb_write_reg_mask(CRD2, VIACR, 0x30, BIT4 + BIT5);
2325         } else if (viafb_LCD_ON) {
2326                 if (viaparinfo->lvds_setting_info->device_lcd_dualedge) {
2327                         /* For dual channel LCD: */
2328                         /* Set to Dual LVDS channel. */
2329                         viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);
2330                 } else {
2331                         /* Set to LVDS0 + LVDS1 channel. */
2332                         viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT4 + BIT5);
2333                 }
2334         }
2335 }
2336
2337 int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp,
2338         struct VideoModeTable *vmode_tbl1, int video_bpp1)
2339 {
2340         int i, j;
2341         int port;
2342         u32 devices = viaparinfo->shared->iga1_devices
2343                 | viaparinfo->shared->iga2_devices;
2344         u8 value, index, mask;
2345         struct crt_mode_table *crt_timing;
2346         struct crt_mode_table *crt_timing1 = NULL;
2347
2348         device_screen_off();
2349         crt_timing = vmode_tbl->crtc;
2350
2351         if (viafb_SAMM_ON == 1) {
2352                 crt_timing1 = vmode_tbl1->crtc;
2353         }
2354
2355         inb(VIAStatus);
2356         outb(0x00, VIAAR);
2357
2358         /* Write Common Setting for Video Mode */
2359         switch (viaparinfo->chip_info->gfx_chip_name) {
2360         case UNICHROME_CLE266:
2361                 viafb_write_regx(CLE266_ModeXregs, NUM_TOTAL_CLE266_ModeXregs);
2362                 break;
2363
2364         case UNICHROME_K400:
2365                 viafb_write_regx(KM400_ModeXregs, NUM_TOTAL_KM400_ModeXregs);
2366                 break;
2367
2368         case UNICHROME_K800:
2369         case UNICHROME_PM800:
2370                 viafb_write_regx(CN400_ModeXregs, NUM_TOTAL_CN400_ModeXregs);
2371                 break;
2372
2373         case UNICHROME_CN700:
2374         case UNICHROME_K8M890:
2375         case UNICHROME_P4M890:
2376         case UNICHROME_P4M900:
2377                 viafb_write_regx(CN700_ModeXregs, NUM_TOTAL_CN700_ModeXregs);
2378                 break;
2379
2380         case UNICHROME_CX700:
2381         case UNICHROME_VX800:
2382                 viafb_write_regx(CX700_ModeXregs, NUM_TOTAL_CX700_ModeXregs);
2383                 break;
2384
2385         case UNICHROME_VX855:
2386                 viafb_write_regx(VX855_ModeXregs, NUM_TOTAL_VX855_ModeXregs);
2387                 break;
2388         }
2389
2390         device_off();
2391         via_set_state(devices, VIA_STATE_OFF);
2392
2393         /* Fill VPIT Parameters */
2394         /* Write Misc Register */
2395         outb(VPIT.Misc, VIA_MISC_REG_WRITE);
2396
2397         /* Write Sequencer */
2398         for (i = 1; i <= StdSR; i++)
2399                 via_write_reg(VIASR, i, VPIT.SR[i - 1]);
2400
2401         viafb_write_reg_mask(0x15, VIASR, 0xA2, 0xA2);
2402
2403         /* Write CRTC */
2404         viafb_fill_crtc_timing(crt_timing, vmode_tbl, video_bpp / 8, IGA1);
2405
2406         /* Write Graphic Controller */
2407         for (i = 0; i < StdGR; i++)
2408                 via_write_reg(VIAGR, i, VPIT.GR[i]);
2409
2410         /* Write Attribute Controller */
2411         for (i = 0; i < StdAR; i++) {
2412                 inb(VIAStatus);
2413                 outb(i, VIAAR);
2414                 outb(VPIT.AR[i], VIAAR);
2415         }
2416
2417         inb(VIAStatus);
2418         outb(0x20, VIAAR);
2419
2420         /* Update Patch Register */
2421
2422         if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266
2423             || viaparinfo->chip_info->gfx_chip_name == UNICHROME_K400)
2424             && vmode_tbl->crtc[0].crtc.hor_addr == 1024
2425             && vmode_tbl->crtc[0].crtc.ver_addr == 768) {
2426                 for (j = 0; j < res_patch_table[0].table_length; j++) {
2427                         index = res_patch_table[0].io_reg_table[j].index;
2428                         port = res_patch_table[0].io_reg_table[j].port;
2429                         value = res_patch_table[0].io_reg_table[j].value;
2430                         mask = res_patch_table[0].io_reg_table[j].mask;
2431                         viafb_write_reg_mask(index, port, value, mask);
2432                 }
2433         }
2434
2435         via_set_primary_pitch(viafbinfo->fix.line_length);
2436         via_set_secondary_pitch(viafb_dual_fb ? viafbinfo1->fix.line_length
2437                 : viafbinfo->fix.line_length);
2438         via_set_primary_color_depth(viaparinfo->depth);
2439         via_set_secondary_color_depth(viafb_dual_fb ? viaparinfo1->depth
2440                 : viaparinfo->depth);
2441         via_set_source(viaparinfo->shared->iga1_devices, IGA1);
2442         via_set_source(viaparinfo->shared->iga2_devices, IGA2);
2443         if (viaparinfo->shared->iga2_devices)
2444                 enable_second_display_channel();
2445         else
2446                 disable_second_display_channel();
2447
2448         /* Update Refresh Rate Setting */
2449
2450         /* Clear On Screen */
2451
2452         /* CRT set mode */
2453         if (viafb_CRT_ON) {
2454                 if (viafb_SAMM_ON && (viaparinfo->crt_setting_info->iga_path ==
2455                         IGA2)) {
2456                         viafb_fill_crtc_timing(crt_timing1, vmode_tbl1,
2457                                 video_bpp1 / 8,
2458                                 viaparinfo->crt_setting_info->iga_path);
2459                 } else {
2460                         viafb_fill_crtc_timing(crt_timing, vmode_tbl,
2461                                 video_bpp / 8,
2462                                 viaparinfo->crt_setting_info->iga_path);
2463                 }
2464
2465                 /* Patch if set_hres is not 8 alignment (1366) to viafb_setmode
2466                 to 8 alignment (1368),there is several pixels (2 pixels)
2467                 on right side of screen. */
2468                 if (vmode_tbl->crtc[0].crtc.hor_addr % 8) {
2469                         viafb_unlock_crt();
2470                         viafb_write_reg(CR02, VIACR,
2471                                 viafb_read_reg(VIACR, CR02) - 1);
2472                         viafb_lock_crt();
2473                 }
2474         }
2475
2476         if (viafb_DVI_ON) {
2477                 if (viafb_SAMM_ON &&
2478                         (viaparinfo->tmds_setting_info->iga_path == IGA2)) {
2479                         viafb_dvi_set_mode(viafb_get_mode
2480                                      (viaparinfo->tmds_setting_info->h_active,
2481                                       viaparinfo->tmds_setting_info->
2482                                       v_active),
2483                                      video_bpp1, viaparinfo->
2484                                      tmds_setting_info->iga_path);
2485                 } else {
2486                         viafb_dvi_set_mode(viafb_get_mode
2487                                      (viaparinfo->tmds_setting_info->h_active,
2488                                       viaparinfo->
2489                                       tmds_setting_info->v_active),
2490                                      video_bpp, viaparinfo->
2491                                      tmds_setting_info->iga_path);
2492                 }
2493         }
2494
2495         if (viafb_LCD_ON) {
2496                 if (viafb_SAMM_ON &&
2497                         (viaparinfo->lvds_setting_info->iga_path == IGA2)) {
2498                         viaparinfo->lvds_setting_info->bpp = video_bpp1;
2499                         viafb_lcd_set_mode(crt_timing1, viaparinfo->
2500                                 lvds_setting_info,
2501                                      &viaparinfo->chip_info->lvds_chip_info);
2502                 } else {
2503                         /* IGA1 doesn't have LCD scaling, so set it center. */
2504                         if (viaparinfo->lvds_setting_info->iga_path == IGA1) {
2505                                 viaparinfo->lvds_setting_info->display_method =
2506                                     LCD_CENTERING;
2507                         }
2508                         viaparinfo->lvds_setting_info->bpp = video_bpp;
2509                         viafb_lcd_set_mode(crt_timing, viaparinfo->
2510                                 lvds_setting_info,
2511                                      &viaparinfo->chip_info->lvds_chip_info);
2512                 }
2513         }
2514         if (viafb_LCD2_ON) {
2515                 if (viafb_SAMM_ON &&
2516                         (viaparinfo->lvds_setting_info2->iga_path == IGA2)) {
2517                         viaparinfo->lvds_setting_info2->bpp = video_bpp1;
2518                         viafb_lcd_set_mode(crt_timing1, viaparinfo->
2519                                 lvds_setting_info2,
2520                                      &viaparinfo->chip_info->lvds_chip_info2);
2521                 } else {
2522                         /* IGA1 doesn't have LCD scaling, so set it center. */
2523                         if (viaparinfo->lvds_setting_info2->iga_path == IGA1) {
2524                                 viaparinfo->lvds_setting_info2->display_method =
2525                                     LCD_CENTERING;
2526                         }
2527                         viaparinfo->lvds_setting_info2->bpp = video_bpp;
2528                         viafb_lcd_set_mode(crt_timing, viaparinfo->
2529                                 lvds_setting_info2,
2530                                      &viaparinfo->chip_info->lvds_chip_info2);
2531                 }
2532         }
2533
2534         if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700)
2535             && (viafb_LCD_ON || viafb_DVI_ON))
2536                 set_display_channel();
2537
2538         /* If set mode normally, save resolution information for hot-plug . */
2539         if (!viafb_hotplug) {
2540                 viafb_hotplug_Xres = vmode_tbl->crtc[0].crtc.hor_addr;
2541                 viafb_hotplug_Yres = vmode_tbl->crtc[0].crtc.ver_addr;
2542                 viafb_hotplug_bpp = video_bpp;
2543                 viafb_hotplug_refresh = viafb_refresh;
2544
2545                 if (viafb_DVI_ON)
2546                         viafb_DeviceStatus = DVI_Device;
2547                 else
2548                         viafb_DeviceStatus = CRT_Device;
2549         }
2550         device_on();
2551         via_set_state(devices, VIA_STATE_ON);
2552         device_screen_on();
2553         return 1;
2554 }
2555
2556 int viafb_get_pixclock(int hres, int vres, int vmode_refresh)
2557 {
2558         int i;
2559
2560         for (i = 0; i < NUM_TOTAL_RES_MAP_REFRESH; i++) {
2561                 if ((hres == res_map_refresh_tbl[i].hres)
2562                     && (vres == res_map_refresh_tbl[i].vres)
2563                     && (vmode_refresh == res_map_refresh_tbl[i].vmode_refresh))
2564                         return res_map_refresh_tbl[i].pixclock;
2565         }
2566         return RES_640X480_60HZ_PIXCLOCK;
2567
2568 }
2569
2570 int viafb_get_refresh(int hres, int vres, u32 long_refresh)
2571 {
2572 #define REFRESH_TOLERANCE 3
2573         int i, nearest = -1, diff = REFRESH_TOLERANCE;
2574         for (i = 0; i < NUM_TOTAL_RES_MAP_REFRESH; i++) {
2575                 if ((hres == res_map_refresh_tbl[i].hres)
2576                     && (vres == res_map_refresh_tbl[i].vres)
2577                     && (diff > (abs(long_refresh -
2578                     res_map_refresh_tbl[i].vmode_refresh)))) {
2579                         diff = abs(long_refresh - res_map_refresh_tbl[i].
2580                                 vmode_refresh);
2581                         nearest = i;
2582                 }
2583         }
2584 #undef REFRESH_TOLERANCE
2585         if (nearest > 0)
2586                 return res_map_refresh_tbl[nearest].vmode_refresh;
2587         return 60;
2588 }
2589
2590 static void device_off(void)
2591 {
2592         viafb_dvi_disable();
2593         viafb_lcd_disable();
2594 }
2595
2596 static void device_on(void)
2597 {
2598         if (viafb_DVI_ON == 1)
2599                 viafb_dvi_enable();
2600         if (viafb_LCD_ON == 1)
2601                 viafb_lcd_enable();
2602 }
2603
2604 static void enable_second_display_channel(void)
2605 {
2606         /* to enable second display channel. */
2607         viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6);
2608         viafb_write_reg_mask(CR6A, VIACR, BIT7, BIT7);
2609         viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6);
2610 }
2611
2612 static void disable_second_display_channel(void)
2613 {
2614         /* to disable second display channel. */
2615         viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6);
2616         viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT7);
2617         viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6);
2618 }
2619
2620 void viafb_set_dpa_gfx(int output_interface, struct GFX_DPA_SETTING\
2621                                         *p_gfx_dpa_setting)
2622 {
2623         switch (output_interface) {
2624         case INTERFACE_DVP0:
2625                 {
2626                         /* DVP0 Clock Polarity and Adjust: */
2627                         viafb_write_reg_mask(CR96, VIACR,
2628                                        p_gfx_dpa_setting->DVP0, 0x0F);
2629
2630                         /* DVP0 Clock and Data Pads Driving: */
2631                         viafb_write_reg_mask(SR1E, VIASR,
2632                                        p_gfx_dpa_setting->DVP0ClockDri_S, BIT2);
2633                         viafb_write_reg_mask(SR2A, VIASR,
2634                                        p_gfx_dpa_setting->DVP0ClockDri_S1,
2635                                        BIT4);
2636                         viafb_write_reg_mask(SR1B, VIASR,
2637                                        p_gfx_dpa_setting->DVP0DataDri_S, BIT1);
2638                         viafb_write_reg_mask(SR2A, VIASR,
2639                                        p_gfx_dpa_setting->DVP0DataDri_S1, BIT5);
2640                         break;
2641                 }
2642
2643         case INTERFACE_DVP1:
2644                 {
2645                         /* DVP1 Clock Polarity and Adjust: */
2646                         viafb_write_reg_mask(CR9B, VIACR,
2647                                        p_gfx_dpa_setting->DVP1, 0x0F);
2648
2649                         /* DVP1 Clock and Data Pads Driving: */
2650                         viafb_write_reg_mask(SR65, VIASR,
2651                                        p_gfx_dpa_setting->DVP1Driving, 0x0F);
2652                         break;
2653                 }
2654
2655         case INTERFACE_DFP_HIGH:
2656                 {
2657                         viafb_write_reg_mask(CR97, VIACR,
2658                                        p_gfx_dpa_setting->DFPHigh, 0x0F);
2659                         break;
2660                 }
2661
2662         case INTERFACE_DFP_LOW:
2663                 {
2664                         viafb_write_reg_mask(CR99, VIACR,
2665                                        p_gfx_dpa_setting->DFPLow, 0x0F);
2666                         break;
2667                 }
2668
2669         case INTERFACE_DFP:
2670                 {
2671                         viafb_write_reg_mask(CR97, VIACR,
2672                                        p_gfx_dpa_setting->DFPHigh, 0x0F);
2673                         viafb_write_reg_mask(CR99, VIACR,
2674                                        p_gfx_dpa_setting->DFPLow, 0x0F);
2675                         break;
2676                 }
2677         }
2678 }
2679
2680 /*According var's xres, yres fill var's other timing information*/
2681 void viafb_fill_var_timing_info(struct fb_var_screeninfo *var, int refresh,
2682         struct VideoModeTable *vmode_tbl)
2683 {
2684         struct crt_mode_table *crt_timing = NULL;
2685         struct display_timing crt_reg;
2686         int i = 0, index = 0;
2687         crt_timing = vmode_tbl->crtc;
2688         for (i = 0; i < vmode_tbl->mode_array; i++) {
2689                 index = i;
2690                 if (crt_timing[i].refresh_rate == refresh)
2691                         break;
2692         }
2693
2694         crt_reg = crt_timing[index].crtc;
2695         var->pixclock = viafb_get_pixclock(var->xres, var->yres, refresh);
2696         var->left_margin =
2697             crt_reg.hor_total - (crt_reg.hor_sync_start + crt_reg.hor_sync_end);
2698         var->right_margin = crt_reg.hor_sync_start - crt_reg.hor_addr;
2699         var->hsync_len = crt_reg.hor_sync_end;
2700         var->upper_margin =
2701             crt_reg.ver_total - (crt_reg.ver_sync_start + crt_reg.ver_sync_end);
2702         var->lower_margin = crt_reg.ver_sync_start - crt_reg.ver_addr;
2703         var->vsync_len = crt_reg.ver_sync_end;
2704 }