2 * Frame buffer driver for Trident Blade and Image series
4 * Copyright 2001, 2002 - Jani Monoses <jani@iv.ro>
7 * CREDITS:(in order of appearance)
8 * skeletonfb.c by Geert Uytterhoeven and other fb code in drivers/video
9 * Special thanks ;) to Mattia Crivellini <tia@mclink.it>
10 * much inspired by the XFree86 4.x Trident driver sources
11 * by Alan Hourihane the FreeVGA project
12 * Francesco Salvestrini <salvestrini@users.sf.net> XP support,
15 * timing value tweaking so it looks good on every monitor in every mode
19 #include <linux/module.h>
21 #include <linux/init.h>
22 #include <linux/pci.h>
24 #include <linux/delay.h>
25 #include <video/trident.h>
27 #define VERSION "0.7.9-NEWAPI"
29 struct tridentfb_par {
30 void __iomem *io_virt; /* iospace virtual memory address */
36 static unsigned char eng_oper; /* engine operation... */
37 static struct fb_ops tridentfb_ops;
39 static struct fb_fix_screeninfo tridentfb_fix = {
41 .type = FB_TYPE_PACKED_PIXELS,
43 .visual = FB_VISUAL_PSEUDOCOLOR,
44 .accel = FB_ACCEL_NONE,
47 /* defaults which are normally overriden by user values */
50 static char *mode_option __devinitdata = "640x480";
51 static int bpp __devinitdata = 8;
53 static int noaccel __devinitdata;
58 static int fp __devinitdata;
59 static int crt __devinitdata;
61 static int memsize __devinitdata;
62 static int memdiff __devinitdata;
65 module_param(mode_option, charp, 0);
66 MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'");
67 module_param_named(mode, mode_option, charp, 0);
68 MODULE_PARM_DESC(mode, "Initial video mode e.g. '648x480-8@60' (deprecated)");
69 module_param(bpp, int, 0);
70 module_param(center, int, 0);
71 module_param(stretch, int, 0);
72 module_param(noaccel, int, 0);
73 module_param(memsize, int, 0);
74 module_param(memdiff, int, 0);
75 module_param(nativex, int, 0);
76 module_param(fp, int, 0);
77 MODULE_PARM_DESC(fp, "Define if flatpanel is connected");
78 module_param(crt, int, 0);
79 MODULE_PARM_DESC(crt, "Define if CRT is connected");
81 static int is_blade(int id)
83 return (id == BLADE3D) ||
84 (id == CYBERBLADEE4) ||
85 (id == CYBERBLADEi7) ||
86 (id == CYBERBLADEi7D) ||
87 (id == CYBERBLADEi1) ||
88 (id == CYBERBLADEi1D) ||
89 (id == CYBERBLADEAi1) ||
90 (id == CYBERBLADEAi1D);
93 static int is_xp(int id)
95 return (id == CYBERBLADEXPAi1) ||
96 (id == CYBERBLADEXPm8) ||
97 (id == CYBERBLADEXPm16);
100 static int is3Dchip(int id)
102 return ((id == BLADE3D) || (id == CYBERBLADEE4) ||
103 (id == CYBERBLADEi7) || (id == CYBERBLADEi7D) ||
104 (id == CYBER9397) || (id == CYBER9397DVD) ||
105 (id == CYBER9520) || (id == CYBER9525DVD) ||
106 (id == IMAGE975) || (id == IMAGE985) ||
107 (id == CYBERBLADEi1) || (id == CYBERBLADEi1D) ||
108 (id == CYBERBLADEAi1) || (id == CYBERBLADEAi1D) ||
109 (id == CYBERBLADEXPm8) || (id == CYBERBLADEXPm16) ||
110 (id == CYBERBLADEXPAi1));
113 static int iscyber(int id)
129 case CYBERBLADEXPAi1:
137 case CYBERBLADEi7: /* VIA MPV4 integrated version */
140 /* case CYBERBLDAEXPm8: Strange */
141 /* case CYBERBLDAEXPm16: Strange */
146 #define CRT 0x3D0 /* CRTC registers offset for color display */
148 static inline void t_outb(struct tridentfb_par *p, u8 val, u16 reg)
150 fb_writeb(val, p->io_virt + reg);
153 static inline u8 t_inb(struct tridentfb_par *p, u16 reg)
155 return fb_readb(p->io_virt + reg);
158 static struct accel_switch {
159 void (*init_accel) (struct tridentfb_par *, int, int);
160 void (*wait_engine) (struct tridentfb_par *);
162 (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32);
164 (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32);
167 static inline void writemmr(struct tridentfb_par *par, u16 r, u32 v)
169 fb_writel(v, par->io_virt + r);
172 static inline u32 readmmr(struct tridentfb_par *par, u16 r)
174 return fb_readl(par->io_virt + r);
178 * Blade specific acceleration.
181 #define point(x, y) ((y) << 16 | (x))
193 static void blade_init_accel(struct tridentfb_par *par, int pitch, int bpp)
195 int v1 = (pitch >> 3) << 20;
212 v2 = v1 | (tmp << 29);
213 writemmr(par, 0x21C0, v2);
214 writemmr(par, 0x21C4, v2);
215 writemmr(par, 0x21B8, v2);
216 writemmr(par, 0x21BC, v2);
217 writemmr(par, 0x21D0, v1);
218 writemmr(par, 0x21D4, v1);
219 writemmr(par, 0x21C8, v1);
220 writemmr(par, 0x21CC, v1);
221 writemmr(par, 0x216C, 0);
224 static void blade_wait_engine(struct tridentfb_par *par)
226 while (readmmr(par, STA) & 0xFA800000) ;
229 static void blade_fill_rect(struct tridentfb_par *par,
230 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
232 writemmr(par, CLR, c);
233 writemmr(par, ROP, rop ? 0x66 : ROP_S);
234 writemmr(par, CMD, 0x20000000 | 1 << 19 | 1 << 4 | 2 << 2);
236 writemmr(par, DR1, point(x, y));
237 writemmr(par, DR2, point(x + w - 1, y + h - 1));
240 static void blade_copy_rect(struct tridentfb_par *par,
241 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
246 s2 = point(x1 + w - 1, y1 + h - 1);
248 d2 = point(x2 + w - 1, y2 + h - 1);
250 if ((y1 > y2) || ((y1 == y2) && (x1 > x2)))
253 writemmr(par, ROP, ROP_S);
254 writemmr(par, CMD, 0xE0000000 | 1 << 19 | 1 << 4 | 1 << 2 | direction);
256 writemmr(par, SR1, direction ? s2 : s1);
257 writemmr(par, SR2, direction ? s1 : s2);
258 writemmr(par, DR1, direction ? d2 : d1);
259 writemmr(par, DR2, direction ? d1 : d2);
262 static struct accel_switch accel_blade = {
270 * BladeXP specific acceleration functions
274 #define masked_point(x, y) ((y & 0xffff)<<16|(x & 0xffff))
276 static void xp_init_accel(struct tridentfb_par *par, int pitch, int bpp)
296 switch (pitch << (bpp >> 3)) {
312 t_outb(par, x, 0x2125);
332 writemmr(par, 0x2154, v1);
333 writemmr(par, 0x2150, v1);
334 t_outb(par, 3, 0x2126);
337 static void xp_wait_engine(struct tridentfb_par *par)
345 busy = t_inb(par, STA) & 0x80;
349 if (count == 10000000) {
355 t_outb(par, 0x00, 0x2120);
362 static void xp_fill_rect(struct tridentfb_par *par,
363 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
365 writemmr(par, 0x2127, ROP_P);
366 writemmr(par, 0x2158, c);
367 writemmr(par, 0x2128, 0x4000);
368 writemmr(par, 0x2140, masked_point(h, w));
369 writemmr(par, 0x2138, masked_point(y, x));
370 t_outb(par, 0x01, 0x2124);
371 t_outb(par, eng_oper, 0x2125);
374 static void xp_copy_rect(struct tridentfb_par *par,
375 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
378 u32 x1_tmp, x2_tmp, y1_tmp, y2_tmp;
382 if ((x1 < x2) && (y1 == y2)) {
400 writemmr(par, 0x2128, direction);
401 t_outb(par, ROP_S, 0x2127);
402 writemmr(par, 0x213C, masked_point(y1_tmp, x1_tmp));
403 writemmr(par, 0x2138, masked_point(y2_tmp, x2_tmp));
404 writemmr(par, 0x2140, masked_point(h, w));
405 t_outb(par, 0x01, 0x2124);
408 static struct accel_switch accel_xp = {
416 * Image specific acceleration functions
418 static void image_init_accel(struct tridentfb_par *par, int pitch, int bpp)
436 writemmr(par, 0x2120, 0xF0000000);
437 writemmr(par, 0x2120, 0x40000000 | tmp);
438 writemmr(par, 0x2120, 0x80000000);
439 writemmr(par, 0x2144, 0x00000000);
440 writemmr(par, 0x2148, 0x00000000);
441 writemmr(par, 0x2150, 0x00000000);
442 writemmr(par, 0x2154, 0x00000000);
443 writemmr(par, 0x2120, 0x60000000 | (pitch << 16) | pitch);
444 writemmr(par, 0x216C, 0x00000000);
445 writemmr(par, 0x2170, 0x00000000);
446 writemmr(par, 0x217C, 0x00000000);
447 writemmr(par, 0x2120, 0x10000000);
448 writemmr(par, 0x2130, (2047 << 16) | 2047);
451 static void image_wait_engine(struct tridentfb_par *par)
453 while (readmmr(par, 0x2164) & 0xF0000000) ;
456 static void image_fill_rect(struct tridentfb_par *par,
457 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
459 writemmr(par, 0x2120, 0x80000000);
460 writemmr(par, 0x2120, 0x90000000 | ROP_S);
462 writemmr(par, 0x2144, c);
464 writemmr(par, DR1, point(x, y));
465 writemmr(par, DR2, point(x + w - 1, y + h - 1));
467 writemmr(par, 0x2124, 0x80000000 | 3 << 22 | 1 << 10 | 1 << 9);
470 static void image_copy_rect(struct tridentfb_par *par,
471 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
476 s2 = point(x1 + w - 1, y1 + h - 1);
478 d2 = point(x2 + w - 1, y2 + h - 1);
480 if ((y1 > y2) || ((y1 == y2) && (x1 > x2)))
483 writemmr(par, 0x2120, 0x80000000);
484 writemmr(par, 0x2120, 0x90000000 | ROP_S);
486 writemmr(par, SR1, direction ? s2 : s1);
487 writemmr(par, SR2, direction ? s1 : s2);
488 writemmr(par, DR1, direction ? d2 : d1);
489 writemmr(par, DR2, direction ? d1 : d2);
490 writemmr(par, 0x2124,
491 0x80000000 | 1 << 22 | 1 << 10 | 1 << 7 | direction);
494 static struct accel_switch accel_image = {
502 * Accel functions called by the upper layers
504 #ifdef CONFIG_FB_TRIDENT_ACCEL
505 static void tridentfb_fillrect(struct fb_info *info,
506 const struct fb_fillrect *fr)
508 struct tridentfb_par *par = info->par;
509 int bpp = info->var.bits_per_pixel;
520 col = ((u32 *)(info->pseudo_palette))[fr->color];
523 col = ((u32 *)(info->pseudo_palette))[fr->color];
527 acc->fill_rect(par, fr->dx, fr->dy, fr->width,
528 fr->height, col, fr->rop);
529 acc->wait_engine(par);
531 static void tridentfb_copyarea(struct fb_info *info,
532 const struct fb_copyarea *ca)
534 struct tridentfb_par *par = info->par;
536 acc->copy_rect(par, ca->sx, ca->sy, ca->dx, ca->dy,
537 ca->width, ca->height);
538 acc->wait_engine(par);
540 #else /* !CONFIG_FB_TRIDENT_ACCEL */
541 #define tridentfb_fillrect cfb_fillrect
542 #define tridentfb_copyarea cfb_copyarea
543 #endif /* CONFIG_FB_TRIDENT_ACCEL */
547 * Hardware access functions
550 static inline unsigned char read3X4(struct tridentfb_par *par, int reg)
552 writeb(reg, par->io_virt + CRT + 4);
553 return readb(par->io_virt + CRT + 5);
556 static inline void write3X4(struct tridentfb_par *par, int reg,
559 writeb(reg, par->io_virt + CRT + 4);
560 writeb(val, par->io_virt + CRT + 5);
563 static inline unsigned char read3C4(struct tridentfb_par *par, int reg)
565 t_outb(par, reg, 0x3C4);
566 return t_inb(par, 0x3C5);
569 static inline void write3C4(struct tridentfb_par *par, int reg,
572 t_outb(par, reg, 0x3C4);
573 t_outb(par, val, 0x3C5);
576 static inline unsigned char read3CE(struct tridentfb_par *par, int reg)
578 t_outb(par, reg, 0x3CE);
579 return t_inb(par, 0x3CF);
582 static inline void writeAttr(struct tridentfb_par *par, int reg,
585 fb_readb(par->io_virt + CRT + 0x0A); /* flip-flop to index */
586 t_outb(par, reg, 0x3C0);
587 t_outb(par, val, 0x3C0);
590 static inline void write3CE(struct tridentfb_par *par, int reg,
593 t_outb(par, reg, 0x3CE);
594 t_outb(par, val, 0x3CF);
597 static void enable_mmio(void)
603 /* Unprotect registers */
604 outb(NewMode1, 0x3C4);
609 outb(inb(0x3D5) | 0x01, 0x3D5);
612 static void disable_mmio(struct tridentfb_par *par)
615 t_outb(par, 0x0B, 0x3C4);
618 /* Unprotect registers */
619 t_outb(par, NewMode1, 0x3C4);
620 t_outb(par, 0x80, 0x3C5);
623 t_outb(par, PCIReg, 0x3D4);
624 t_outb(par, t_inb(par, 0x3D5) & ~0x01, 0x3D5);
627 static void crtc_unlock(struct tridentfb_par *par)
629 write3X4(par, CRTVSyncEnd, read3X4(par, CRTVSyncEnd) & 0x7F);
632 /* Return flat panel's maximum x resolution */
633 static int __devinit get_nativex(struct tridentfb_par *par)
640 tmp = (read3CE(par, VertStretch) >> 4) & 3;
661 output("%dx%d flat panel found\n", x, y);
666 static void set_lwidth(struct tridentfb_par *par, int width)
668 write3X4(par, Offset, width & 0xFF);
669 write3X4(par, AddColReg,
670 (read3X4(par, AddColReg) & 0xCF) | ((width & 0x300) >> 4));
673 /* For resolutions smaller than FP resolution stretch */
674 static void screen_stretch(struct tridentfb_par *par)
676 if (par->chip_id != CYBERBLADEXPAi1)
677 write3CE(par, BiosReg, 0);
679 write3CE(par, BiosReg, 8);
680 write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 1);
681 write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 1);
684 /* For resolutions smaller than FP resolution center */
685 static void screen_center(struct tridentfb_par *par)
687 write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 0x80);
688 write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 0x80);
691 /* Address of first shown pixel in display memory */
692 static void set_screen_start(struct tridentfb_par *par, int base)
695 write3X4(par, StartAddrLow, base & 0xFF);
696 write3X4(par, StartAddrHigh, (base & 0xFF00) >> 8);
697 tmp = read3X4(par, CRTCModuleTest) & 0xDF;
698 write3X4(par, CRTCModuleTest, tmp | ((base & 0x10000) >> 11));
699 tmp = read3X4(par, CRTHiOrd) & 0xF8;
700 write3X4(par, CRTHiOrd, tmp | ((base & 0xE0000) >> 17));
703 /* Set dotclock frequency */
704 static void set_vclk(struct tridentfb_par *par, unsigned long freq)
707 unsigned long f, fi, d, di;
708 unsigned char lo = 0, hi = 0;
711 for (k = 2; k >= 0; k--)
712 for (m = 0; m < 63; m++)
713 for (n = 0; n < 128; n++) {
714 fi = ((14318l * (n + 8)) / (m + 2)) >> k;
715 if ((di = abs(fi - freq)) < d) {
724 if (is3Dchip(par->chip_id)) {
725 write3C4(par, ClockHigh, hi);
726 write3C4(par, ClockLow, lo);
731 debug("VCLK = %X %X\n", hi, lo);
734 /* Set number of lines for flat panels*/
735 static void set_number_of_lines(struct tridentfb_par *par, int lines)
737 int tmp = read3CE(par, CyberEnhance) & 0x8F;
740 else if (lines > 768)
742 else if (lines > 600)
744 else if (lines > 480)
746 write3CE(par, CyberEnhance, tmp);
750 * If we see that FP is active we assume we have one.
751 * Otherwise we have a CRT display. User can override.
753 static int __devinit is_flatpanel(struct tridentfb_par *par)
757 if (crt || !iscyber(par->chip_id))
759 return (read3CE(par, FPConfig) & 0x10) ? 1 : 0;
762 /* Try detecting the video memory size */
763 static unsigned int __devinit get_memsize(struct tridentfb_par *par)
765 unsigned char tmp, tmp2;
768 /* If memory size provided by user */
772 switch (par->chip_id) {
777 tmp = read3X4(par, SPR) & 0x0F;
793 k = 10 * Mb; /* XP */
799 k = 12 * Mb; /* XP */
802 k = 14 * Mb; /* XP */
805 k = 16 * Mb; /* XP */
809 tmp2 = read3C4(par, 0xC1);
839 output("framebuffer size = %d Kb\n", k / Kb);
843 /* See if we can handle the video mode described in var */
844 static int tridentfb_check_var(struct fb_var_screeninfo *var,
845 struct fb_info *info)
847 struct tridentfb_par *par = info->par;
848 int bpp = var->bits_per_pixel;
851 /* check color depth */
853 bpp = var->bits_per_pixel = 32;
854 /* check whether resolution fits on panel and in memory */
855 if (par->flatpanel && nativex && var->xres > nativex)
857 if (var->xres * var->yres_virtual * bpp / 8 > info->fix.smem_len)
863 var->green.offset = 0;
864 var->blue.offset = 0;
866 var->green.length = 6;
867 var->blue.length = 6;
870 var->red.offset = 11;
871 var->green.offset = 5;
872 var->blue.offset = 0;
874 var->green.length = 6;
875 var->blue.length = 5;
878 var->red.offset = 16;
879 var->green.offset = 8;
880 var->blue.offset = 0;
882 var->green.length = 8;
883 var->blue.length = 8;
894 /* Pan the display */
895 static int tridentfb_pan_display(struct fb_var_screeninfo *var,
896 struct fb_info *info)
898 struct tridentfb_par *par = info->par;
902 offset = (var->xoffset + (var->yoffset * var->xres))
903 * var->bits_per_pixel / 32;
904 info->var.xoffset = var->xoffset;
905 info->var.yoffset = var->yoffset;
906 set_screen_start(par, offset);
911 static void shadowmode_on(struct tridentfb_par *par)
913 write3CE(par, CyberControl, read3CE(par, CyberControl) | 0x81);
916 static void shadowmode_off(struct tridentfb_par *par)
918 write3CE(par, CyberControl, read3CE(par, CyberControl) & 0x7E);
921 /* Set the hardware to the requested video mode */
922 static int tridentfb_set_par(struct fb_info *info)
924 struct tridentfb_par *par = (struct tridentfb_par *)(info->par);
925 u32 htotal, hdispend, hsyncstart, hsyncend, hblankstart, hblankend;
926 u32 vtotal, vdispend, vsyncstart, vsyncend, vblankstart, vblankend;
927 struct fb_var_screeninfo *var = &info->var;
928 int bpp = var->bits_per_pixel;
933 hdispend = var->xres / 8 - 1;
934 hsyncstart = (var->xres + var->right_margin) / 8;
935 hsyncend = var->hsync_len / 8;
937 (var->xres + var->left_margin + var->right_margin +
938 var->hsync_len) / 8 - 10;
939 hblankstart = hdispend + 1;
940 hblankend = htotal + 5;
942 vdispend = var->yres - 1;
943 vsyncstart = var->yres + var->lower_margin;
944 vsyncend = var->vsync_len;
945 vtotal = var->upper_margin + vsyncstart + vsyncend - 2;
946 vblankstart = var->yres;
947 vblankend = vtotal + 2;
950 write3CE(par, CyberControl, 8);
952 if (par->flatpanel && var->xres < nativex) {
954 * on flat panels with native size larger
955 * than requested resolution decide whether
956 * we stretch or center
958 t_outb(par, 0xEB, 0x3C2);
968 t_outb(par, 0x2B, 0x3C2);
969 write3CE(par, CyberControl, 8);
972 /* vertical timing values */
973 write3X4(par, CRTVTotal, vtotal & 0xFF);
974 write3X4(par, CRTVDispEnd, vdispend & 0xFF);
975 write3X4(par, CRTVSyncStart, vsyncstart & 0xFF);
976 write3X4(par, CRTVSyncEnd, (vsyncend & 0x0F));
977 write3X4(par, CRTVBlankStart, vblankstart & 0xFF);
978 write3X4(par, CRTVBlankEnd, 0 /* p->vblankend & 0xFF */);
980 /* horizontal timing values */
981 write3X4(par, CRTHTotal, htotal & 0xFF);
982 write3X4(par, CRTHDispEnd, hdispend & 0xFF);
983 write3X4(par, CRTHSyncStart, hsyncstart & 0xFF);
984 write3X4(par, CRTHSyncEnd,
985 (hsyncend & 0x1F) | ((hblankend & 0x20) << 2));
986 write3X4(par, CRTHBlankStart, hblankstart & 0xFF);
987 write3X4(par, CRTHBlankEnd, 0 /* (p->hblankend & 0x1F) */);
989 /* higher bits of vertical timing values */
991 if (vtotal & 0x100) tmp |= 0x01;
992 if (vdispend & 0x100) tmp |= 0x02;
993 if (vsyncstart & 0x100) tmp |= 0x04;
994 if (vblankstart & 0x100) tmp |= 0x08;
996 if (vtotal & 0x200) tmp |= 0x20;
997 if (vdispend & 0x200) tmp |= 0x40;
998 if (vsyncstart & 0x200) tmp |= 0x80;
999 write3X4(par, CRTOverflow, tmp);
1001 tmp = read3X4(par, CRTHiOrd) | 0x08; /* line compare bit 10 */
1002 if (vtotal & 0x400) tmp |= 0x80;
1003 if (vblankstart & 0x400) tmp |= 0x40;
1004 if (vsyncstart & 0x400) tmp |= 0x20;
1005 if (vdispend & 0x400) tmp |= 0x10;
1006 write3X4(par, CRTHiOrd, tmp);
1009 if (htotal & 0x800) tmp |= 0x800 >> 11;
1010 if (hblankstart & 0x800) tmp |= 0x800 >> 7;
1011 write3X4(par, HorizOverflow, tmp);
1014 if (vblankstart & 0x200) tmp |= 0x20;
1015 //FIXME if (info->var.vmode & FB_VMODE_DOUBLE) tmp |= 0x80; /* double scan for 200 line modes */
1016 write3X4(par, CRTMaxScanLine, tmp);
1018 write3X4(par, CRTLineCompare, 0xFF);
1019 write3X4(par, CRTPRowScan, 0);
1020 write3X4(par, CRTModeControl, 0xC3);
1022 write3X4(par, LinearAddReg, 0x20); /* enable linear addressing */
1024 tmp = (info->var.vmode & FB_VMODE_INTERLACED) ? 0x84 : 0x80;
1025 /* enable access extended memory */
1026 write3X4(par, CRTCModuleTest, tmp);
1028 /* enable GE for text acceleration */
1029 write3X4(par, GraphEngReg, 0x80);
1031 #ifdef CONFIG_FB_TRIDENT_ACCEL
1032 acc->init_accel(par, info->var.xres, bpp);
1050 write3X4(par, PixelBusReg, tmp);
1053 if (iscyber(par->chip_id))
1055 write3X4(par, DRAMControl, tmp); /* both IO, linear enable */
1057 write3X4(par, InterfaceSel, read3X4(par, InterfaceSel) | 0x40);
1058 write3X4(par, Performance, 0x92);
1059 /* MMIO & PCI read and write burst enable */
1060 write3X4(par, PCIReg, 0x07);
1062 /* convert from picoseconds to kHz */
1063 vclk = PICOS2KHZ(info->var.pixclock);
1066 set_vclk(par, vclk);
1068 write3C4(par, 0, 3);
1069 write3C4(par, 1, 1); /* set char clock 8 dots wide */
1070 /* enable 4 maps because needed in chain4 mode */
1071 write3C4(par, 2, 0x0F);
1072 write3C4(par, 3, 0);
1073 write3C4(par, 4, 0x0E); /* memory mode enable bitmaps ?? */
1075 /* divide clock by 2 if 32bpp chain4 mode display and CPU path */
1076 write3CE(par, MiscExtFunc, (bpp == 32) ? 0x1A : 0x12);
1077 write3CE(par, 0x5, 0x40); /* no CGA compat, allow 256 col */
1078 write3CE(par, 0x6, 0x05); /* graphics mode */
1079 write3CE(par, 0x7, 0x0F); /* planes? */
1081 if (par->chip_id == CYBERBLADEXPAi1) {
1082 /* This fixes snow-effect in 32 bpp */
1083 write3X4(par, CRTHSyncStart, 0x84);
1086 /* graphics mode and support 256 color modes */
1087 writeAttr(par, 0x10, 0x41);
1088 writeAttr(par, 0x12, 0x0F); /* planes */
1089 writeAttr(par, 0x13, 0); /* horizontal pel panning */
1092 for (tmp = 0; tmp < 0x10; tmp++)
1093 writeAttr(par, tmp, tmp);
1094 fb_readb(par->io_virt + CRT + 0x0A); /* flip-flop to index */
1095 t_outb(par, 0x20, 0x3C0); /* enable attr */
1118 t_outb(par, tmp, 0x3C6);
1122 set_number_of_lines(par, info->var.yres);
1123 set_lwidth(par, info->var.xres * bpp / (4 * 16));
1124 info->fix.visual = (bpp == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
1125 info->fix.line_length = info->var.xres * (bpp >> 3);
1126 info->cmap.len = (bpp == 8) ? 256 : 16;
1131 /* Set one color register */
1132 static int tridentfb_setcolreg(unsigned regno, unsigned red, unsigned green,
1133 unsigned blue, unsigned transp,
1134 struct fb_info *info)
1136 int bpp = info->var.bits_per_pixel;
1137 struct tridentfb_par *par = info->par;
1139 if (regno >= info->cmap.len)
1143 t_outb(par, 0xFF, 0x3C6);
1144 t_outb(par, regno, 0x3C8);
1146 t_outb(par, red >> 10, 0x3C9);
1147 t_outb(par, green >> 10, 0x3C9);
1148 t_outb(par, blue >> 10, 0x3C9);
1150 } else if (regno < 16) {
1151 if (bpp == 16) { /* RGB 565 */
1154 col = (red & 0xF800) | ((green & 0xFC00) >> 5) |
1155 ((blue & 0xF800) >> 11);
1157 ((u32 *)(info->pseudo_palette))[regno] = col;
1158 } else if (bpp == 32) /* ARGB 8888 */
1159 ((u32*)info->pseudo_palette)[regno] =
1160 ((transp & 0xFF00) << 16) |
1161 ((red & 0xFF00) << 8) |
1162 ((green & 0xFF00)) |
1163 ((blue & 0xFF00) >> 8);
1166 /* debug("exit\n"); */
1170 /* Try blanking the screen.For flat panels it does nothing */
1171 static int tridentfb_blank(int blank_mode, struct fb_info *info)
1173 unsigned char PMCont, DPMSCont;
1174 struct tridentfb_par *par = info->par;
1179 t_outb(par, 0x04, 0x83C8); /* Read DPMS Control */
1180 PMCont = t_inb(par, 0x83C6) & 0xFC;
1181 DPMSCont = read3CE(par, PowerStatus) & 0xFC;
1182 switch (blank_mode) {
1183 case FB_BLANK_UNBLANK:
1184 /* Screen: On, HSync: On, VSync: On */
1185 case FB_BLANK_NORMAL:
1186 /* Screen: Off, HSync: On, VSync: On */
1190 case FB_BLANK_HSYNC_SUSPEND:
1191 /* Screen: Off, HSync: Off, VSync: On */
1195 case FB_BLANK_VSYNC_SUSPEND:
1196 /* Screen: Off, HSync: On, VSync: Off */
1200 case FB_BLANK_POWERDOWN:
1201 /* Screen: Off, HSync: Off, VSync: Off */
1207 write3CE(par, PowerStatus, DPMSCont);
1208 t_outb(par, 4, 0x83C8);
1209 t_outb(par, PMCont, 0x83C6);
1213 /* let fbcon do a softblank for us */
1214 return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0;
1217 static struct fb_ops tridentfb_ops = {
1218 .owner = THIS_MODULE,
1219 .fb_setcolreg = tridentfb_setcolreg,
1220 .fb_pan_display = tridentfb_pan_display,
1221 .fb_blank = tridentfb_blank,
1222 .fb_check_var = tridentfb_check_var,
1223 .fb_set_par = tridentfb_set_par,
1224 .fb_fillrect = tridentfb_fillrect,
1225 .fb_copyarea = tridentfb_copyarea,
1226 .fb_imageblit = cfb_imageblit,
1229 static int __devinit trident_pci_probe(struct pci_dev *dev,
1230 const struct pci_device_id *id)
1233 unsigned char revision;
1234 struct fb_info *info;
1235 struct tridentfb_par *default_par;
1240 err = pci_enable_device(dev);
1244 info = framebuffer_alloc(sizeof(struct tridentfb_par), &dev->dev);
1247 default_par = info->par;
1249 chip_id = id->device;
1251 if (chip_id == CYBERBLADEi1)
1252 output("*** Please do use cyblafb, Cyberblade/i1 support "
1253 "will soon be removed from tridentfb!\n");
1256 /* If PCI id is 0x9660 then further detect chip type */
1258 if (chip_id == TGUI9660) {
1259 outb(RevisionID, 0x3C4);
1260 revision = inb(0x3C5);
1265 chip_id = CYBER9397;
1268 chip_id = CYBER9397DVD;
1277 chip_id = CYBER9385;
1280 chip_id = CYBER9382;
1283 chip_id = CYBER9388;
1290 chip3D = is3Dchip(chip_id);
1292 if (is_xp(chip_id)) {
1294 } else if (is_blade(chip_id)) {
1300 default_par->chip_id = chip_id;
1302 /* acceleration is on by default for 3D chips */
1303 defaultaccel = chip3D && !noaccel;
1305 /* setup MMIO region */
1306 tridentfb_fix.mmio_start = pci_resource_start(dev, 1);
1307 tridentfb_fix.mmio_len = chip3D ? 0x20000 : 0x10000;
1309 if (!request_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len, "tridentfb")) {
1310 debug("request_region failed!\n");
1314 default_par->io_virt = ioremap_nocache(tridentfb_fix.mmio_start,
1315 tridentfb_fix.mmio_len);
1317 if (!default_par->io_virt) {
1318 debug("ioremap failed\n");
1325 /* setup framebuffer memory */
1326 tridentfb_fix.smem_start = pci_resource_start(dev, 0);
1327 tridentfb_fix.smem_len = get_memsize(default_par);
1329 if (!request_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len, "tridentfb")) {
1330 debug("request_mem_region failed!\n");
1331 disable_mmio(info->par);
1336 info->screen_base = ioremap_nocache(tridentfb_fix.smem_start,
1337 tridentfb_fix.smem_len);
1339 if (!info->screen_base) {
1340 debug("ioremap failed\n");
1345 output("%s board found\n", pci_name(dev));
1346 default_par->flatpanel = is_flatpanel(default_par);
1348 if (default_par->flatpanel)
1349 nativex = get_nativex(default_par);
1351 info->fix = tridentfb_fix;
1352 info->fbops = &tridentfb_ops;
1355 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
1356 #ifdef CONFIG_FB_TRIDENT_ACCEL
1357 info->flags |= FBINFO_HWACCEL_COPYAREA | FBINFO_HWACCEL_FILLRECT;
1359 if (!fb_find_mode(&info->var, info,
1360 mode_option, NULL, 0, NULL, bpp)) {
1364 err = fb_alloc_cmap(&info->cmap, 256, 0);
1368 if (defaultaccel && acc)
1369 info->var.accel_flags |= FB_ACCELF_TEXT;
1371 info->var.accel_flags &= ~FB_ACCELF_TEXT;
1372 info->var.activate |= FB_ACTIVATE_NOW;
1373 info->device = &dev->dev;
1374 if (register_framebuffer(info) < 0) {
1375 printk(KERN_ERR "tridentfb: could not register Trident framebuffer\n");
1376 fb_dealloc_cmap(&info->cmap);
1380 output("fb%d: %s frame buffer device %dx%d-%dbpp\n",
1381 info->node, info->fix.id, info->var.xres,
1382 info->var.yres, info->var.bits_per_pixel);
1384 pci_set_drvdata(dev, info);
1388 if (info->screen_base)
1389 iounmap(info->screen_base);
1390 release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len);
1391 disable_mmio(info->par);
1393 if (default_par->io_virt)
1394 iounmap(default_par->io_virt);
1395 release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len);
1396 framebuffer_release(info);
1400 static void __devexit trident_pci_remove(struct pci_dev *dev)
1402 struct fb_info *info = pci_get_drvdata(dev);
1403 struct tridentfb_par *par = info->par;
1405 unregister_framebuffer(info);
1406 iounmap(par->io_virt);
1407 iounmap(info->screen_base);
1408 release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len);
1409 release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len);
1410 pci_set_drvdata(dev, NULL);
1411 framebuffer_release(info);
1414 /* List of boards that we are trying to support */
1415 static struct pci_device_id trident_devices[] = {
1416 {PCI_VENDOR_ID_TRIDENT, BLADE3D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1417 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1418 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1419 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1420 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1421 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1422 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1423 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEE4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1424 {PCI_VENDOR_ID_TRIDENT, TGUI9660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1425 {PCI_VENDOR_ID_TRIDENT, IMAGE975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1426 {PCI_VENDOR_ID_TRIDENT, IMAGE985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1427 {PCI_VENDOR_ID_TRIDENT, CYBER9320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1428 {PCI_VENDOR_ID_TRIDENT, CYBER9388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1429 {PCI_VENDOR_ID_TRIDENT, CYBER9520, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1430 {PCI_VENDOR_ID_TRIDENT, CYBER9525DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1431 {PCI_VENDOR_ID_TRIDENT, CYBER9397, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1432 {PCI_VENDOR_ID_TRIDENT, CYBER9397DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1433 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1434 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1435 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm16, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1439 MODULE_DEVICE_TABLE(pci, trident_devices);
1441 static struct pci_driver tridentfb_pci_driver = {
1442 .name = "tridentfb",
1443 .id_table = trident_devices,
1444 .probe = trident_pci_probe,
1445 .remove = __devexit_p(trident_pci_remove)
1449 * Parse user specified options (`video=trident:')
1451 * video=trident:800x600,bpp=16,noaccel
1454 static int __init tridentfb_setup(char *options)
1457 if (!options || !*options)
1459 while ((opt = strsep(&options, ",")) != NULL) {
1462 if (!strncmp(opt, "noaccel", 7))
1464 else if (!strncmp(opt, "fp", 2))
1466 else if (!strncmp(opt, "crt", 3))
1468 else if (!strncmp(opt, "bpp=", 4))
1469 bpp = simple_strtoul(opt + 4, NULL, 0);
1470 else if (!strncmp(opt, "center", 6))
1472 else if (!strncmp(opt, "stretch", 7))
1474 else if (!strncmp(opt, "memsize=", 8))
1475 memsize = simple_strtoul(opt + 8, NULL, 0);
1476 else if (!strncmp(opt, "memdiff=", 8))
1477 memdiff = simple_strtoul(opt + 8, NULL, 0);
1478 else if (!strncmp(opt, "nativex=", 8))
1479 nativex = simple_strtoul(opt + 8, NULL, 0);
1487 static int __init tridentfb_init(void)
1490 char *option = NULL;
1492 if (fb_get_options("tridentfb", &option))
1494 tridentfb_setup(option);
1496 output("Trident framebuffer %s initializing\n", VERSION);
1497 return pci_register_driver(&tridentfb_pci_driver);
1500 static void __exit tridentfb_exit(void)
1502 pci_unregister_driver(&tridentfb_pci_driver);
1505 module_init(tridentfb_init);
1506 module_exit(tridentfb_exit);
1508 MODULE_AUTHOR("Jani Monoses <jani@iv.ro>");
1509 MODULE_DESCRIPTION("Framebuffer driver for Trident cards");
1510 MODULE_LICENSE("GPL");