1 // SPDX-License-Identifier: GPL-2.0+
3 * Allwinner DE2 display driver
5 * (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
12 #include <efi_loader.h>
14 #include <fdt_support.h>
18 #include <asm/global_data.h>
20 #include <asm/arch/clock.h>
21 #include <asm/arch/display2.h>
22 #include <dm/device-internal.h>
23 #include <dm/uclass-internal.h>
24 #include "simplefb_common.h"
26 DECLARE_GLOBAL_DATA_PTR;
29 /* Maximum LCD size we support */
31 LCD_MAX_HEIGHT = 2160,
32 LCD_MAX_LOG2_BPP = VIDEO_BPP32,
35 static void sunxi_de2_composer_init(void)
37 struct sunxi_ccm_reg * const ccm =
38 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
40 #ifdef CONFIG_MACH_SUN50I
43 /* set SRAM for video use (A64 only) */
44 reg_value = readl(SUNXI_SRAMC_BASE + 0x04);
45 reg_value &= ~(0x01 << 24);
46 writel(reg_value, SUNXI_SRAMC_BASE + 0x04);
49 clock_set_pll10(432000000);
51 /* Set DE parent to pll10 */
52 clrsetbits_le32(&ccm->de_clk_cfg, CCM_DE2_CTRL_PLL_MASK,
55 /* Set ahb gating to pass */
56 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DE);
57 setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_DE);
60 setbits_le32(&ccm->de_clk_cfg, CCM_DE2_CTRL_GATE);
63 static void sunxi_de2_mode_set(int mux, const struct display_timing *mode,
64 int bpp, ulong address, bool is_composite)
66 ulong de_mux_base = (mux == 0) ?
67 SUNXI_DE2_MUX0_BASE : SUNXI_DE2_MUX1_BASE;
68 struct de_clk * const de_clk_regs =
69 (struct de_clk *)(SUNXI_DE2_BASE);
70 struct de_glb * const de_glb_regs =
71 (struct de_glb *)(de_mux_base +
72 SUNXI_DE2_MUX_GLB_REGS);
73 struct de_bld * const de_bld_regs =
74 (struct de_bld *)(de_mux_base +
75 SUNXI_DE2_MUX_BLD_REGS);
76 struct de_ui * const de_ui_regs =
77 (struct de_ui *)(de_mux_base +
78 SUNXI_DE2_MUX_CHAN_REGS +
79 SUNXI_DE2_MUX_CHAN_SZ * 1);
80 struct de_csc * const de_csc_regs =
81 (struct de_csc *)(de_mux_base +
82 SUNXI_DE2_MUX_DCSC_REGS);
83 u32 size = SUNXI_DE2_WH(mode->hactive.typ, mode->vactive.typ);
88 #ifdef CONFIG_MACH_SUN8I_H3
89 setbits_le32(&de_clk_regs->rst_cfg, (mux == 0) ? 1 : 4);
91 setbits_le32(&de_clk_regs->rst_cfg, BIT(mux));
93 setbits_le32(&de_clk_regs->gate_cfg, BIT(mux));
94 setbits_le32(&de_clk_regs->bus_cfg, BIT(mux));
96 clrbits_le32(&de_clk_regs->sel_cfg, 1);
98 writel(SUNXI_DE2_MUX_GLB_CTL_EN, &de_glb_regs->ctl);
99 writel(0, &de_glb_regs->status);
100 writel(1, &de_glb_regs->dbuff);
101 writel(size, &de_glb_regs->size);
103 for (channel = 0; channel < 4; channel++) {
104 void *ch = (void *)(de_mux_base + SUNXI_DE2_MUX_CHAN_REGS +
105 SUNXI_DE2_MUX_CHAN_SZ * channel);
106 memset(ch, 0, (channel == 0) ?
107 sizeof(struct de_vi) : sizeof(struct de_ui));
109 memset(de_bld_regs, 0, sizeof(struct de_bld));
111 writel(0x00000101, &de_bld_regs->fcolor_ctl);
113 writel(1, &de_bld_regs->route);
115 writel(0, &de_bld_regs->premultiply);
116 writel(0xff000000, &de_bld_regs->bkcolor);
118 writel(0x03010301, &de_bld_regs->bld_mode[0]);
120 writel(size, &de_bld_regs->output_size);
121 writel(mode->flags & DISPLAY_FLAGS_INTERLACED ? 2 : 0,
122 &de_bld_regs->out_ctl);
123 writel(0, &de_bld_regs->ck_ctl);
125 writel(0xff000000, &de_bld_regs->attr[0].fcolor);
126 writel(size, &de_bld_regs->attr[0].insize);
128 /* Disable all other units */
129 writel(0, de_mux_base + SUNXI_DE2_MUX_VSU_REGS);
130 writel(0, de_mux_base + SUNXI_DE2_MUX_GSU1_REGS);
131 writel(0, de_mux_base + SUNXI_DE2_MUX_GSU2_REGS);
132 writel(0, de_mux_base + SUNXI_DE2_MUX_GSU3_REGS);
133 writel(0, de_mux_base + SUNXI_DE2_MUX_FCE_REGS);
134 writel(0, de_mux_base + SUNXI_DE2_MUX_BWS_REGS);
135 writel(0, de_mux_base + SUNXI_DE2_MUX_LTI_REGS);
136 writel(0, de_mux_base + SUNXI_DE2_MUX_PEAK_REGS);
137 writel(0, de_mux_base + SUNXI_DE2_MUX_ASE_REGS);
138 writel(0, de_mux_base + SUNXI_DE2_MUX_FCC_REGS);
141 /* set CSC coefficients */
142 writel(0x107, &de_csc_regs->coef11);
143 writel(0x204, &de_csc_regs->coef12);
144 writel(0x64, &de_csc_regs->coef13);
145 writel(0x4200, &de_csc_regs->coef14);
146 writel(0x1f68, &de_csc_regs->coef21);
147 writel(0x1ed6, &de_csc_regs->coef22);
148 writel(0x1c2, &de_csc_regs->coef23);
149 writel(0x20200, &de_csc_regs->coef24);
150 writel(0x1c2, &de_csc_regs->coef31);
151 writel(0x1e87, &de_csc_regs->coef32);
152 writel(0x1fb7, &de_csc_regs->coef33);
153 writel(0x20200, &de_csc_regs->coef34);
155 /* enable CSC unit */
156 writel(1, &de_csc_regs->csc_ctl);
158 writel(0, &de_csc_regs->csc_ctl);
163 format = SUNXI_DE2_UI_CFG_ATTR_FMT(SUNXI_DE2_FORMAT_RGB_565);
167 format = SUNXI_DE2_UI_CFG_ATTR_FMT(SUNXI_DE2_FORMAT_XRGB_8888);
171 writel(SUNXI_DE2_UI_CFG_ATTR_EN | format, &de_ui_regs->cfg[0].attr);
172 writel(size, &de_ui_regs->cfg[0].size);
173 writel(0, &de_ui_regs->cfg[0].coord);
174 writel((bpp / 8) * mode->hactive.typ, &de_ui_regs->cfg[0].pitch);
175 writel(address, &de_ui_regs->cfg[0].top_laddr);
176 writel(size, &de_ui_regs->ovl_size);
179 writel(1, &de_glb_regs->dbuff);
182 static int sunxi_de2_init(struct udevice *dev, ulong fbbase,
183 enum video_log2_bpp l2bpp,
184 struct udevice *disp, int mux, bool is_composite)
186 struct video_priv *uc_priv = dev_get_uclass_priv(dev);
187 struct display_timing timing;
188 struct display_plat *disp_uc_plat;
191 disp_uc_plat = dev_get_uclass_platdata(disp);
192 debug("Using device '%s', disp_uc_priv=%p\n", disp->name, disp_uc_plat);
193 if (display_in_use(disp)) {
194 debug(" - device in use\n");
198 disp_uc_plat->source_id = mux;
200 ret = device_probe(disp);
202 debug("%s: device '%s' display won't probe (ret=%d)\n",
203 __func__, dev->name, ret);
207 ret = display_read_timing(disp, &timing);
209 debug("%s: Failed to read timings\n", __func__);
213 sunxi_de2_composer_init();
214 sunxi_de2_mode_set(mux, &timing, 1 << l2bpp, fbbase, is_composite);
216 ret = display_enable(disp, 1 << l2bpp, &timing);
218 debug("%s: Failed to enable display\n", __func__);
222 uc_priv->xsize = timing.hactive.typ;
223 uc_priv->ysize = timing.vactive.typ;
224 uc_priv->bpix = l2bpp;
225 debug("fb=%lx, size=%d %d\n", fbbase, uc_priv->xsize, uc_priv->ysize);
227 #ifdef CONFIG_EFI_LOADER
228 efi_add_memory_map(fbbase,
229 timing.hactive.typ * timing.vactive.typ *
231 EFI_RESERVED_MEMORY_TYPE);
237 static int sunxi_de2_probe(struct udevice *dev)
239 struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
240 struct udevice *disp;
243 /* Before relocation we don't need to do anything */
244 if (!(gd->flags & GD_FLG_RELOC))
247 ret = uclass_find_device_by_name(UCLASS_DISPLAY,
254 ret = sunxi_de2_init(dev, plat->base, VIDEO_BPP32, disp, mux,
257 video_set_flush_dcache(dev, 1);
262 debug("%s: lcd display not found (ret=%d)\n", __func__, ret);
264 ret = uclass_find_device_by_name(UCLASS_DISPLAY,
265 "sunxi_dw_hdmi", &disp);
268 if (IS_ENABLED(CONFIG_MACH_SUNXI_H3_H5))
273 ret = sunxi_de2_init(dev, plat->base, VIDEO_BPP32, disp, mux,
276 video_set_flush_dcache(dev, 1);
281 debug("%s: hdmi display not found (ret=%d)\n", __func__, ret);
283 ret = uclass_find_device_by_name(UCLASS_DISPLAY,
286 debug("%s: tv not found (ret=%d)\n", __func__, ret);
290 ret = sunxi_de2_init(dev, plat->base, VIDEO_BPP32, disp, 1, true);
294 video_set_flush_dcache(dev, 1);
299 static int sunxi_de2_bind(struct udevice *dev)
301 struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
303 plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
304 (1 << LCD_MAX_LOG2_BPP) / 8;
309 static const struct video_ops sunxi_de2_ops = {
312 U_BOOT_DRIVER(sunxi_de2) = {
315 .ops = &sunxi_de2_ops,
316 .bind = sunxi_de2_bind,
317 .probe = sunxi_de2_probe,
318 .flags = DM_FLAG_PRE_RELOC,
321 U_BOOT_DEVICE(sunxi_de2) = {
328 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_VIDEO_DT_SIMPLEFB)
329 int sunxi_simplefb_setup(void *blob)
331 struct udevice *de2, *hdmi, *lcd;
332 struct video_priv *de2_priv;
333 struct video_uc_platdata *de2_plat;
337 const char *pipeline = NULL;
339 debug("Setting up simplefb\n");
341 if (IS_ENABLED(CONFIG_MACH_SUNXI_H3_H5))
346 /* Skip simplefb setting if DE2 / HDMI is not present */
347 ret = uclass_find_device_by_name(UCLASS_VIDEO,
350 debug("DE2 not present\n");
352 } else if (!device_active(de2)) {
353 debug("DE2 present but not probed\n");
357 ret = uclass_find_device_by_name(UCLASS_DISPLAY,
358 "sunxi_dw_hdmi", &hdmi);
360 debug("HDMI not present\n");
361 } else if (device_active(hdmi)) {
363 pipeline = "mixer0-lcd0-hdmi";
365 pipeline = "mixer1-lcd1-hdmi";
367 debug("HDMI present but not probed\n");
370 ret = uclass_find_device_by_name(UCLASS_DISPLAY,
373 debug("LCD not present\n");
374 else if (device_active(lcd))
375 pipeline = "mixer0-lcd0";
377 debug("LCD present but not probed\n");
380 debug("No active display present\n");
384 de2_priv = dev_get_uclass_priv(de2);
385 de2_plat = dev_get_uclass_platdata(de2);
387 offset = sunxi_simplefb_fdt_match(blob, pipeline);
389 eprintf("Cannot setup simplefb: node not found\n");
390 return 0; /* Keep older kernels working */
393 start = gd->bd->bi_dram[0].start;
394 size = de2_plat->base - start;
395 ret = fdt_fixup_memory_banks(blob, &start, &size, 1);
397 eprintf("Cannot setup simplefb: Error reserving memory\n");
401 ret = fdt_setup_simplefb_node(blob, offset, de2_plat->base,
402 de2_priv->xsize, de2_priv->ysize,
403 VNBYTES(de2_priv->bpix) * de2_priv->xsize,
406 eprintf("Cannot setup simplefb: Error setting properties\n");
410 #endif /* CONFIG_OF_BOARD_SETUP && CONFIG_VIDEO_DT_SIMPLEFB */