1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2015 Google, Inc
4 * Copyright 2014 Rockchip Inc.
18 #include <asm/arch-rockchip/clock.h>
19 #include <asm/arch-rockchip/edp_rk3288.h>
20 #include <asm/arch-rockchip/vop_rk3288.h>
21 #include <dm/device-internal.h>
22 #include <dm/uclass-internal.h>
23 #include <linux/err.h>
24 #include <power/regulator.h>
27 DECLARE_GLOBAL_DATA_PTR;
36 static void rkvop_enable(struct rk3288_vop *regs, ulong fbbase,
37 int fb_bits_per_pixel,
38 const struct display_timing *edid)
42 u32 hactive = edid->hactive.typ;
43 u32 vactive = edid->vactive.typ;
45 writel(V_ACT_WIDTH(hactive - 1) | V_ACT_HEIGHT(vactive - 1),
46 ®s->win0_act_info);
48 writel(V_DSP_XST(edid->hsync_len.typ + edid->hback_porch.typ) |
49 V_DSP_YST(edid->vsync_len.typ + edid->vback_porch.typ),
52 writel(V_DSP_WIDTH(hactive - 1) |
53 V_DSP_HEIGHT(vactive - 1),
54 ®s->win0_dsp_info);
56 clrsetbits_le32(®s->win0_color_key, M_WIN0_KEY_EN | M_WIN0_KEY_COLOR,
57 V_WIN0_KEY_EN(0) | V_WIN0_KEY_COLOR(0));
59 switch (fb_bits_per_pixel) {
62 writel(V_RGB565_VIRWIDTH(hactive), ®s->win0_vir);
66 writel(V_RGB888_VIRWIDTH(hactive), ®s->win0_vir);
71 writel(V_ARGB888_VIRWIDTH(hactive), ®s->win0_vir);
76 lb_mode = LB_RGB_3840X2;
77 else if (hactive > 1920)
78 lb_mode = LB_RGB_2560X4;
79 else if (hactive > 1280)
80 lb_mode = LB_RGB_1920X5;
82 lb_mode = LB_RGB_1280X8;
84 clrsetbits_le32(®s->win0_ctrl0,
85 M_WIN0_LB_MODE | M_WIN0_DATA_FMT | M_WIN0_EN,
86 V_WIN0_LB_MODE(lb_mode) | V_WIN0_DATA_FMT(rgb_mode) |
89 writel(fbbase, ®s->win0_yrgb_mst);
90 writel(0x01, ®s->reg_cfg_done); /* enable reg config */
93 static void rkvop_set_pin_polarity(struct udevice *dev,
94 enum vop_modes mode, u32 polarity)
96 struct rkvop_driverdata *ops =
97 (struct rkvop_driverdata *)dev_get_driver_data(dev);
99 if (ops->set_pin_polarity)
100 ops->set_pin_polarity(dev, mode, polarity);
103 static void rkvop_enable_output(struct udevice *dev, enum vop_modes mode)
105 struct rk_vop_priv *priv = dev_get_priv(dev);
106 struct rk3288_vop *regs = priv->regs;
108 /* remove from standby */
109 clrbits_le32(®s->sys_ctrl, V_STANDBY_EN(1));
113 clrsetbits_le32(®s->sys_ctrl, M_ALL_OUT_EN,
118 clrsetbits_le32(®s->sys_ctrl, M_ALL_OUT_EN,
122 #if defined(CONFIG_ROCKCHIP_RK3288)
124 clrsetbits_le32(®s->sys_ctrl, M_ALL_OUT_EN,
130 clrsetbits_le32(®s->sys_ctrl, M_ALL_OUT_EN,
135 debug("%s: unsupported output mode %x\n", __func__, mode);
139 static void rkvop_mode_set(struct udevice *dev,
140 const struct display_timing *edid,
143 struct rk_vop_priv *priv = dev_get_priv(dev);
144 struct rk3288_vop *regs = priv->regs;
145 struct rkvop_driverdata *data =
146 (struct rkvop_driverdata *)dev_get_driver_data(dev);
148 u32 hactive = edid->hactive.typ;
149 u32 vactive = edid->vactive.typ;
150 u32 hsync_len = edid->hsync_len.typ;
151 u32 hback_porch = edid->hback_porch.typ;
152 u32 vsync_len = edid->vsync_len.typ;
153 u32 vback_porch = edid->vback_porch.typ;
154 u32 hfront_porch = edid->hfront_porch.typ;
155 u32 vfront_porch = edid->vfront_porch.typ;
159 pin_polarity = BIT(DCLK_INVERT);
160 if (edid->flags & DISPLAY_FLAGS_HSYNC_HIGH)
161 pin_polarity |= BIT(HSYNC_POSITIVE);
162 if (edid->flags & DISPLAY_FLAGS_VSYNC_HIGH)
163 pin_polarity |= BIT(VSYNC_POSITIVE);
165 rkvop_set_pin_polarity(dev, mode, pin_polarity);
166 rkvop_enable_output(dev, mode);
168 mode_flags = 0; /* RGB888 */
169 if ((data->features & VOP_FEATURE_OUTPUT_10BIT) &&
170 (mode == VOP_MODE_HDMI || mode == VOP_MODE_EDP))
171 mode_flags = 15; /* RGBaaa */
173 clrsetbits_le32(®s->dsp_ctrl0, M_DSP_OUT_MODE,
174 V_DSP_OUT_MODE(mode_flags));
176 writel(V_HSYNC(hsync_len) |
177 V_HORPRD(hsync_len + hback_porch + hactive + hfront_porch),
178 ®s->dsp_htotal_hs_end);
180 writel(V_HEAP(hsync_len + hback_porch + hactive) |
181 V_HASP(hsync_len + hback_porch),
182 ®s->dsp_hact_st_end);
184 writel(V_VSYNC(vsync_len) |
185 V_VERPRD(vsync_len + vback_porch + vactive + vfront_porch),
186 ®s->dsp_vtotal_vs_end);
188 writel(V_VAEP(vsync_len + vback_porch + vactive)|
189 V_VASP(vsync_len + vback_porch),
190 ®s->dsp_vact_st_end);
192 writel(V_HEAP(hsync_len + hback_porch + hactive) |
193 V_HASP(hsync_len + hback_porch),
194 ®s->post_dsp_hact_info);
196 writel(V_VAEP(vsync_len + vback_porch + vactive)|
197 V_VASP(vsync_len + vback_porch),
198 ®s->post_dsp_vact_info);
200 writel(0x01, ®s->reg_cfg_done); /* enable reg config */
204 * rk_display_init() - Try to enable the given display device
206 * This function performs many steps:
207 * - Finds the display device being referenced by @ep_node
208 * - Puts the VOP's ID into its uclass platform data
209 * - Probes the device to set it up
210 * - Reads the EDID timing information
211 * - Sets up the VOP clocks, etc. for the selected pixel clock and display mode
212 * - Enables the display (the display device handles this and will do different
213 * things depending on the display type)
214 * - Tells the uclass about the display resolution so that the console will
217 * @dev: VOP device that we want to connect to the display
218 * @fbbase: Frame buffer address
219 * @ep_node: Device tree node to process - this is the offset of an endpoint
220 * node within the VOP's 'port' list.
221 * @return 0 if OK, -ve if something went wrong
223 static int rk_display_init(struct udevice *dev, ulong fbbase, ofnode ep_node)
225 struct video_priv *uc_priv = dev_get_uclass_priv(dev);
226 struct rk_vop_priv *priv = dev_get_priv(dev);
227 int vop_id, remote_vop_id;
228 struct rk3288_vop *regs = priv->regs;
229 struct display_timing timing;
230 struct udevice *disp;
233 struct display_plat *disp_uc_plat;
235 enum video_log2_bpp l2bpp;
238 debug("%s(%s, %lu, %s)\n", __func__,
239 dev_read_name(dev), fbbase, ofnode_get_name(ep_node));
241 vop_id = ofnode_read_s32_default(ep_node, "reg", -1);
242 debug("vop_id=%d\n", vop_id);
243 ret = ofnode_read_u32(ep_node, "remote-endpoint", &remote_phandle);
247 remote = ofnode_get_by_phandle(remote_phandle);
248 if (!ofnode_valid(remote))
250 remote_vop_id = ofnode_read_u32_default(remote, "reg", -1);
251 debug("remote vop_id=%d\n", remote_vop_id);
254 * The remote-endpoint references into a subnode of the encoder
255 * (i.e. HDMI, MIPI, etc.) with the DTS looking something like
256 * the following (assume 'hdmi_in_vopl' to be referenced):
258 * hdmi: hdmi@ff940000 {
261 * hdmi_in_vopb: endpoint@0 { ... };
262 * hdmi_in_vopl: endpoint@1 { ... };
267 * The original code had 3 steps of "walking the parent", but
268 * a much better (as in: less likely to break if the DTS
269 * changes) way of doing this is to "find the enclosing device
270 * of UCLASS_DISPLAY".
272 while (ofnode_valid(remote)) {
273 remote = ofnode_get_parent(remote);
274 if (!ofnode_valid(remote)) {
275 debug("%s(%s): no UCLASS_DISPLAY for remote-endpoint\n",
276 __func__, dev_read_name(dev));
280 uclass_find_device_by_ofnode(UCLASS_DISPLAY, remote, &disp);
285 disp_uc_plat = dev_get_uclass_platdata(disp);
286 debug("Found device '%s', disp_uc_priv=%p\n", disp->name, disp_uc_plat);
287 if (display_in_use(disp)) {
288 debug(" - device in use\n");
292 disp_uc_plat->source_id = remote_vop_id;
293 disp_uc_plat->src_dev = dev;
295 ret = device_probe(disp);
297 debug("%s: device '%s' display won't probe (ret=%d)\n",
298 __func__, dev->name, ret);
302 ret = display_read_timing(disp, &timing);
304 debug("%s: Failed to read timings\n", __func__);
308 ret = clk_get_by_index(dev, 1, &clk);
310 ret = clk_set_rate(&clk, timing.pixelclock.typ);
311 if (IS_ERR_VALUE(ret)) {
312 debug("%s: Failed to set pixel clock: ret=%d\n", __func__, ret);
316 /* Set bitwidth for vop display according to vop mode */
319 #if defined(CONFIG_ROCKCHIP_RK3288)
332 rkvop_mode_set(dev, &timing, vop_id);
333 rkvop_enable(regs, fbbase, 1 << l2bpp, &timing);
335 ret = display_enable(disp, 1 << l2bpp, &timing);
339 uc_priv->xsize = timing.hactive.typ;
340 uc_priv->ysize = timing.vactive.typ;
341 uc_priv->bpix = l2bpp;
342 debug("fb=%lx, size=%d %d\n", fbbase, uc_priv->xsize, uc_priv->ysize);
347 void rk_vop_probe_regulators(struct udevice *dev,
348 const char * const *names, int cnt)
354 for (i = 0; i < cnt; ++i) {
356 debug("%s: probing regulator '%s'\n", dev->name, name);
358 ret = regulator_autoset_by_name(name, ®);
360 ret = regulator_set_enable(reg, true);
364 int rk_vop_probe(struct udevice *dev)
366 struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
367 struct rk_vop_priv *priv = dev_get_priv(dev);
371 /* Before relocation we don't need to do anything */
372 if (!(gd->flags & GD_FLG_RELOC))
375 priv->regs = (struct rk3288_vop *)dev_read_addr(dev);
378 * Try all the ports until we find one that works. In practice this
379 * tries EDP first if available, then HDMI.
381 * Note that rockchip_vop_set_clk() always uses NPLL as the source
382 * clock so it is currently not possible to use more than one display
383 * device simultaneously.
385 port = dev_read_subnode(dev, "port");
386 if (!ofnode_valid(port)) {
387 debug("%s(%s): 'port' subnode not found\n",
388 __func__, dev_read_name(dev));
392 for (node = ofnode_first_subnode(port);
394 node = dev_read_next_subnode(node)) {
395 ret = rk_display_init(dev, plat->base, node);
397 debug("Device failed: ret=%d\n", ret);
401 video_set_flush_dcache(dev, 1);
406 int rk_vop_bind(struct udevice *dev)
408 struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
410 plat->size = 4 * (CONFIG_VIDEO_ROCKCHIP_MAX_XRES *
411 CONFIG_VIDEO_ROCKCHIP_MAX_YRES);