2 * linux/drivers/video/pxafb.c
4 * Copyright (C) 1999 Eric A. Thomas.
5 * Copyright (C) 2004 Jean-Frederic Clere.
6 * Copyright (C) 2004 Ian Campbell.
7 * Copyright (C) 2004 Jeff Lackey.
8 * Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas
10 * Based on acornfb.c Copyright (C) Russell King.
12 * This file is subject to the terms and conditions of the GNU General Public
13 * License. See the file COPYING in the main directory of this archive for
16 * Intel PXA250/210 LCD Controller Frame Buffer Driver
18 * Please direct your questions and comments on this driver to the following
21 * linux-arm-kernel@lists.arm.linux.org.uk
25 #include <linux/module.h>
26 #include <linux/moduleparam.h>
27 #include <linux/kernel.h>
28 #include <linux/sched.h>
29 #include <linux/errno.h>
30 #include <linux/string.h>
31 #include <linux/interrupt.h>
32 #include <linux/slab.h>
34 #include <linux/delay.h>
35 #include <linux/init.h>
36 #include <linux/ioport.h>
37 #include <linux/cpufreq.h>
38 #include <linux/platform_device.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/clk.h>
41 #include <linux/err.h>
43 #include <asm/hardware.h>
46 #include <asm/div64.h>
47 #include <asm/arch/pxa-regs.h>
48 #include <asm/arch/pxa2xx-gpio.h>
49 #include <asm/arch/bitfield.h>
50 #include <asm/arch/pxafb.h>
53 * Complain if VAR is out of range.
59 /* Bits which should not be set in machine configuration structures */
60 #define LCCR0_INVALID_CONFIG_MASK (LCCR0_OUM | LCCR0_BM | LCCR0_QDM |\
61 LCCR0_DIS | LCCR0_EFM | LCCR0_IUM |\
62 LCCR0_SFM | LCCR0_LDM | LCCR0_ENB)
64 #define LCCR3_INVALID_CONFIG_MASK (LCCR3_HSP | LCCR3_VSP |\
65 LCCR3_PCD | LCCR3_BPP)
67 static void (*pxafb_backlight_power)(int);
68 static void (*pxafb_lcd_power)(int, struct fb_var_screeninfo *);
70 static int pxafb_activate_var(struct fb_var_screeninfo *var,
72 static void set_ctrlr_state(struct pxafb_info *fbi, u_int state);
74 static inline void pxafb_schedule_work(struct pxafb_info *fbi, u_int state)
78 local_irq_save(flags);
80 * We need to handle two requests being made at the same time.
81 * There are two important cases:
82 * 1. When we are changing VT (C_REENABLE) while unblanking
83 * (C_ENABLE) We must perform the unblanking, which will
84 * do our REENABLE for us.
85 * 2. When we are blanking, but immediately unblank before
86 * we have blanked. We do the "REENABLE" thing here as
87 * well, just to be sure.
89 if (fbi->task_state == C_ENABLE && state == C_REENABLE)
91 if (fbi->task_state == C_DISABLE && state == C_ENABLE)
94 if (state != (u_int)-1) {
95 fbi->task_state = state;
96 schedule_work(&fbi->task);
98 local_irq_restore(flags);
101 static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
104 chan >>= 16 - bf->length;
105 return chan << bf->offset;
109 pxafb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
110 u_int trans, struct fb_info *info)
112 struct pxafb_info *fbi = (struct pxafb_info *)info;
115 if (regno >= fbi->palette_size)
118 if (fbi->fb.var.grayscale) {
119 fbi->palette_cpu[regno] = ((blue >> 8) & 0x00ff);
123 switch (fbi->lccr4 & LCCR4_PAL_FOR_MASK) {
124 case LCCR4_PAL_FOR_0:
125 val = ((red >> 0) & 0xf800);
126 val |= ((green >> 5) & 0x07e0);
127 val |= ((blue >> 11) & 0x001f);
128 fbi->palette_cpu[regno] = val;
130 case LCCR4_PAL_FOR_1:
131 val = ((red << 8) & 0x00f80000);
132 val |= ((green >> 0) & 0x0000fc00);
133 val |= ((blue >> 8) & 0x000000f8);
134 ((u32 *)(fbi->palette_cpu))[regno] = val;
136 case LCCR4_PAL_FOR_2:
137 val = ((red << 8) & 0x00fc0000);
138 val |= ((green >> 0) & 0x0000fc00);
139 val |= ((blue >> 8) & 0x000000fc);
140 ((u32 *)(fbi->palette_cpu))[regno] = val;
148 pxafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
149 u_int trans, struct fb_info *info)
151 struct pxafb_info *fbi = (struct pxafb_info *)info;
156 * If inverse mode was selected, invert all the colours
157 * rather than the register number. The register number
158 * is what you poke into the framebuffer to produce the
159 * colour you requested.
161 if (fbi->cmap_inverse) {
163 green = 0xffff - green;
164 blue = 0xffff - blue;
168 * If greyscale is true, then we convert the RGB value
169 * to greyscale no matter what visual we are using.
171 if (fbi->fb.var.grayscale)
172 red = green = blue = (19595 * red + 38470 * green +
175 switch (fbi->fb.fix.visual) {
176 case FB_VISUAL_TRUECOLOR:
178 * 16-bit True Colour. We encode the RGB value
179 * according to the RGB bitfield information.
182 u32 *pal = fbi->fb.pseudo_palette;
184 val = chan_to_field(red, &fbi->fb.var.red);
185 val |= chan_to_field(green, &fbi->fb.var.green);
186 val |= chan_to_field(blue, &fbi->fb.var.blue);
193 case FB_VISUAL_STATIC_PSEUDOCOLOR:
194 case FB_VISUAL_PSEUDOCOLOR:
195 ret = pxafb_setpalettereg(regno, red, green, blue, trans, info);
203 * pxafb_bpp_to_lccr3():
204 * Convert a bits per pixel value to the correct bit pattern for LCCR3
206 static int pxafb_bpp_to_lccr3(struct fb_var_screeninfo *var)
209 switch (var->bits_per_pixel) {
210 case 1: ret = LCCR3_1BPP; break;
211 case 2: ret = LCCR3_2BPP; break;
212 case 4: ret = LCCR3_4BPP; break;
213 case 8: ret = LCCR3_8BPP; break;
214 case 16: ret = LCCR3_16BPP; break;
219 #ifdef CONFIG_CPU_FREQ
221 * pxafb_display_dma_period()
222 * Calculate the minimum period (in picoseconds) between two DMA
223 * requests for the LCD controller. If we hit this, it means we're
224 * doing nothing but LCD DMA.
226 static unsigned int pxafb_display_dma_period(struct fb_var_screeninfo *var)
229 * Period = pixclock * bits_per_byte * bytes_per_transfer
230 * / memory_bits_per_pixel;
232 return var->pixclock * 8 * 16 / var->bits_per_pixel;
237 * Select the smallest mode that allows the desired resolution to be
238 * displayed. If desired parameters can be rounded up.
240 static struct pxafb_mode_info *pxafb_getmode(struct pxafb_mach_info *mach,
241 struct fb_var_screeninfo *var)
243 struct pxafb_mode_info *mode = NULL;
244 struct pxafb_mode_info *modelist = mach->modes;
245 unsigned int best_x = 0xffffffff, best_y = 0xffffffff;
248 for (i = 0; i < mach->num_modes; i++) {
249 if (modelist[i].xres >= var->xres &&
250 modelist[i].yres >= var->yres &&
251 modelist[i].xres < best_x &&
252 modelist[i].yres < best_y &&
253 modelist[i].bpp >= var->bits_per_pixel) {
254 best_x = modelist[i].xres;
255 best_y = modelist[i].yres;
263 static void pxafb_setmode(struct fb_var_screeninfo *var,
264 struct pxafb_mode_info *mode)
266 var->xres = mode->xres;
267 var->yres = mode->yres;
268 var->bits_per_pixel = mode->bpp;
269 var->pixclock = mode->pixclock;
270 var->hsync_len = mode->hsync_len;
271 var->left_margin = mode->left_margin;
272 var->right_margin = mode->right_margin;
273 var->vsync_len = mode->vsync_len;
274 var->upper_margin = mode->upper_margin;
275 var->lower_margin = mode->lower_margin;
276 var->sync = mode->sync;
277 var->grayscale = mode->cmap_greyscale;
278 var->xres_virtual = var->xres;
279 var->yres_virtual = var->yres;
284 * Get the video params out of 'var'. If a value doesn't fit, round it up,
285 * if it's too big, return -EINVAL.
287 * Round up in the following order: bits_per_pixel, xres,
288 * yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale,
289 * bitfields, horizontal timing, vertical timing.
291 static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
293 struct pxafb_info *fbi = (struct pxafb_info *)info;
294 struct pxafb_mach_info *inf = fbi->dev->platform_data;
296 if (var->xres < MIN_XRES)
297 var->xres = MIN_XRES;
298 if (var->yres < MIN_YRES)
299 var->yres = MIN_YRES;
301 if (inf->fixed_modes) {
302 struct pxafb_mode_info *mode;
304 mode = pxafb_getmode(inf, var);
307 pxafb_setmode(var, mode);
309 if (var->xres > inf->modes->xres)
311 if (var->yres > inf->modes->yres)
313 if (var->bits_per_pixel > inf->modes->bpp)
318 max(var->xres_virtual, var->xres);
320 max(var->yres_virtual, var->yres);
323 * Setup the RGB parameters for this display.
325 * The pixel packing format is described on page 7-11 of the
326 * PXA2XX Developer's Manual.
328 if (var->bits_per_pixel == 16) {
329 var->red.offset = 11; var->red.length = 5;
330 var->green.offset = 5; var->green.length = 6;
331 var->blue.offset = 0; var->blue.length = 5;
332 var->transp.offset = var->transp.length = 0;
334 var->red.offset = var->green.offset = 0;
335 var->blue.offset = var->transp.offset = 0;
337 var->green.length = 8;
338 var->blue.length = 8;
339 var->transp.length = 0;
342 #ifdef CONFIG_CPU_FREQ
343 pr_debug("pxafb: dma period = %d ps, clock = %d kHz\n",
344 pxafb_display_dma_period(var),
345 get_clk_frequency_khz(0));
351 static inline void pxafb_set_truecolor(u_int is_true_color)
353 /* do your machine-specific setup if needed */
358 * Set the user defined part of the display for the specified console
360 static int pxafb_set_par(struct fb_info *info)
362 struct pxafb_info *fbi = (struct pxafb_info *)info;
363 struct fb_var_screeninfo *var = &info->var;
365 if (var->bits_per_pixel == 16)
366 fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR;
367 else if (!fbi->cmap_static)
368 fbi->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
371 * Some people have weird ideas about wanting static
372 * pseudocolor maps. I suspect their user space
373 * applications are broken.
375 fbi->fb.fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR;
378 fbi->fb.fix.line_length = var->xres_virtual *
379 var->bits_per_pixel / 8;
380 if (var->bits_per_pixel == 16)
381 fbi->palette_size = 0;
383 fbi->palette_size = var->bits_per_pixel == 1 ?
384 4 : 1 << var->bits_per_pixel;
386 fbi->palette_cpu = (u16 *)&fbi->dma_buff->palette[0];
389 * Set (any) board control register to handle new color depth
391 pxafb_set_truecolor(fbi->fb.fix.visual == FB_VISUAL_TRUECOLOR);
393 if (fbi->fb.var.bits_per_pixel == 16)
394 fb_dealloc_cmap(&fbi->fb.cmap);
396 fb_alloc_cmap(&fbi->fb.cmap, 1<<fbi->fb.var.bits_per_pixel, 0);
398 pxafb_activate_var(var, fbi);
405 * Blank the display by setting all palette values to zero. Note, the
406 * 16 bpp mode does not really use the palette, so this will not
407 * blank the display in all modes.
409 static int pxafb_blank(int blank, struct fb_info *info)
411 struct pxafb_info *fbi = (struct pxafb_info *)info;
415 case FB_BLANK_POWERDOWN:
416 case FB_BLANK_VSYNC_SUSPEND:
417 case FB_BLANK_HSYNC_SUSPEND:
418 case FB_BLANK_NORMAL:
419 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
420 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
421 for (i = 0; i < fbi->palette_size; i++)
422 pxafb_setpalettereg(i, 0, 0, 0, 0, info);
424 pxafb_schedule_work(fbi, C_DISABLE);
425 /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */
428 case FB_BLANK_UNBLANK:
429 /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */
430 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
431 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
432 fb_set_cmap(&fbi->fb.cmap, info);
433 pxafb_schedule_work(fbi, C_ENABLE);
438 static int pxafb_mmap(struct fb_info *info,
439 struct vm_area_struct *vma)
441 struct pxafb_info *fbi = (struct pxafb_info *)info;
442 unsigned long off = vma->vm_pgoff << PAGE_SHIFT;
444 if (off < info->fix.smem_len) {
446 return dma_mmap_writecombine(fbi->dev, vma, fbi->map_cpu,
447 fbi->map_dma, fbi->map_size);
452 static struct fb_ops pxafb_ops = {
453 .owner = THIS_MODULE,
454 .fb_check_var = pxafb_check_var,
455 .fb_set_par = pxafb_set_par,
456 .fb_setcolreg = pxafb_setcolreg,
457 .fb_fillrect = cfb_fillrect,
458 .fb_copyarea = cfb_copyarea,
459 .fb_imageblit = cfb_imageblit,
460 .fb_blank = pxafb_blank,
461 .fb_mmap = pxafb_mmap,
465 * Calculate the PCD value from the clock rate (in picoseconds).
466 * We take account of the PPCR clock setting.
467 * From PXA Developer's Manual:
478 * LCLK = LCD/Memory Clock
481 * PixelClock here is in Hz while the pixclock argument given is the
482 * period in picoseconds. Hence PixelClock = 1 / ( pixclock * 10^-12 )
484 * The function get_lclk_frequency_10khz returns LCLK in units of
485 * 10khz. Calling the result of this function lclk gives us the
488 * PCD = (lclk * 10^4 ) * ( pixclock * 10^-12 )
489 * -------------------------------------- - 1
492 * Factoring the 10^4 and 10^-12 out gives 10^-8 == 1 / 100000000 as used below.
494 static inline unsigned int get_pcd(struct pxafb_info *fbi,
495 unsigned int pixclock)
497 unsigned long long pcd;
499 /* FIXME: Need to take into account Double Pixel Clock mode
500 * (DPC) bit? or perhaps set it based on the various clock
502 pcd = (unsigned long long)(clk_get_rate(fbi->clk) / 10000);
504 do_div(pcd, 100000000 * 2);
505 /* no need for this, since we should subtract 1 anyway. they cancel */
506 /* pcd += 1; */ /* make up for integer math truncations */
507 return (unsigned int)pcd;
511 * Some touchscreens need hsync information from the video driver to
512 * function correctly. We export it here. Note that 'hsync_time' and
513 * the value returned from pxafb_get_hsync_time() is the *reciprocal*
514 * of the hsync period in seconds.
516 static inline void set_hsync_time(struct pxafb_info *fbi, unsigned int pcd)
520 if ((pcd == 0) || (fbi->fb.var.hsync_len == 0)) {
525 htime = clk_get_rate(fbi->clk) / (pcd * fbi->fb.var.hsync_len);
527 fbi->hsync_time = htime;
530 unsigned long pxafb_get_hsync_time(struct device *dev)
532 struct pxafb_info *fbi = dev_get_drvdata(dev);
534 /* If display is blanked/suspended, hsync isn't active */
535 if (!fbi || (fbi->state != C_ENABLE))
538 return fbi->hsync_time;
540 EXPORT_SYMBOL(pxafb_get_hsync_time);
542 static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal,
543 unsigned int offset, size_t size)
545 struct pxafb_dma_descriptor *dma_desc, *pal_desc;
546 unsigned int dma_desc_off, pal_desc_off;
548 if (dma < 0 || dma >= DMA_MAX)
551 dma_desc = &fbi->dma_buff->dma_desc[dma];
552 dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[dma]);
554 dma_desc->fsadr = fbi->screen_dma + offset;
556 dma_desc->ldcmd = size;
558 if (pal < 0 || pal >= PAL_MAX) {
559 dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
560 fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off;
562 pal_desc = &fbi->dma_buff->pal_desc[dma];
563 pal_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[pal]);
565 pal_desc->fsadr = fbi->dma_buff_phys + pal * PALETTE_SIZE;
568 if ((fbi->lccr4 & LCCR4_PAL_FOR_MASK) == LCCR4_PAL_FOR_0)
569 pal_desc->ldcmd = fbi->palette_size * sizeof(u16);
571 pal_desc->ldcmd = fbi->palette_size * sizeof(u32);
573 pal_desc->ldcmd |= LDCMD_PAL;
575 /* flip back and forth between palette and frame buffer */
576 pal_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
577 dma_desc->fdadr = fbi->dma_buff_phys + pal_desc_off;
578 fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off;
585 * pxafb_activate_var():
586 * Configures LCD Controller based on entries in var parameter.
587 * Settings are only written to the controller if changes were made.
589 static int pxafb_activate_var(struct fb_var_screeninfo *var,
590 struct pxafb_info *fbi)
592 struct pxafb_lcd_reg new_regs;
594 u_int lines_per_panel, pcd = get_pcd(fbi, var->pixclock);
598 if (var->xres < 16 || var->xres > 1024)
599 printk(KERN_ERR "%s: invalid xres %d\n",
600 fbi->fb.fix.id, var->xres);
601 switch (var->bits_per_pixel) {
609 printk(KERN_ERR "%s: invalid bit depth %d\n",
610 fbi->fb.fix.id, var->bits_per_pixel);
613 if (var->hsync_len < 1 || var->hsync_len > 64)
614 printk(KERN_ERR "%s: invalid hsync_len %d\n",
615 fbi->fb.fix.id, var->hsync_len);
616 if (var->left_margin < 1 || var->left_margin > 255)
617 printk(KERN_ERR "%s: invalid left_margin %d\n",
618 fbi->fb.fix.id, var->left_margin);
619 if (var->right_margin < 1 || var->right_margin > 255)
620 printk(KERN_ERR "%s: invalid right_margin %d\n",
621 fbi->fb.fix.id, var->right_margin);
622 if (var->yres < 1 || var->yres > 1024)
623 printk(KERN_ERR "%s: invalid yres %d\n",
624 fbi->fb.fix.id, var->yres);
625 if (var->vsync_len < 1 || var->vsync_len > 64)
626 printk(KERN_ERR "%s: invalid vsync_len %d\n",
627 fbi->fb.fix.id, var->vsync_len);
628 if (var->upper_margin < 0 || var->upper_margin > 255)
629 printk(KERN_ERR "%s: invalid upper_margin %d\n",
630 fbi->fb.fix.id, var->upper_margin);
631 if (var->lower_margin < 0 || var->lower_margin > 255)
632 printk(KERN_ERR "%s: invalid lower_margin %d\n",
633 fbi->fb.fix.id, var->lower_margin);
636 new_regs.lccr0 = fbi->lccr0 |
637 (LCCR0_LDM | LCCR0_SFM | LCCR0_IUM | LCCR0_EFM |
638 LCCR0_QDM | LCCR0_BM | LCCR0_OUM);
641 LCCR1_DisWdth(var->xres) +
642 LCCR1_HorSnchWdth(var->hsync_len) +
643 LCCR1_BegLnDel(var->left_margin) +
644 LCCR1_EndLnDel(var->right_margin);
647 * If we have a dual scan LCD, we need to halve
648 * the YRES parameter.
650 lines_per_panel = var->yres;
651 if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual)
652 lines_per_panel /= 2;
655 LCCR2_DisHght(lines_per_panel) +
656 LCCR2_VrtSnchWdth(var->vsync_len) +
657 LCCR2_BegFrmDel(var->upper_margin) +
658 LCCR2_EndFrmDel(var->lower_margin);
660 new_regs.lccr3 = fbi->lccr3 |
661 pxafb_bpp_to_lccr3(var) |
662 (var->sync & FB_SYNC_HOR_HIGH_ACT ?
663 LCCR3_HorSnchH : LCCR3_HorSnchL) |
664 (var->sync & FB_SYNC_VERT_HIGH_ACT ?
665 LCCR3_VrtSnchH : LCCR3_VrtSnchL);
668 new_regs.lccr3 |= LCCR3_PixClkDiv(pcd);
670 /* Update shadow copy atomically */
671 local_irq_save(flags);
673 nbytes = lines_per_panel * fbi->fb.fix.line_length;
675 if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual)
676 setup_frame_dma(fbi, DMA_LOWER, PAL_NONE, nbytes, nbytes);
678 if (var->bits_per_pixel >= 16)
679 setup_frame_dma(fbi, DMA_BASE, PAL_NONE, 0, nbytes);
681 setup_frame_dma(fbi, DMA_BASE, PAL_BASE, 0, nbytes);
683 fbi->reg_lccr0 = new_regs.lccr0;
684 fbi->reg_lccr1 = new_regs.lccr1;
685 fbi->reg_lccr2 = new_regs.lccr2;
686 fbi->reg_lccr3 = new_regs.lccr3;
687 fbi->reg_lccr4 = __raw_readl(fbi->mmio_base + LCCR4) &
688 (~LCCR4_PAL_FOR_MASK);
689 fbi->reg_lccr4 |= (fbi->lccr4 & LCCR4_PAL_FOR_MASK);
690 set_hsync_time(fbi, pcd);
691 local_irq_restore(flags);
694 * Only update the registers if the controller is enabled
695 * and something has changed.
697 if ((__raw_readl(fbi->mmio_base + LCCR0) != fbi->reg_lccr0) ||
698 (__raw_readl(fbi->mmio_base + LCCR1) != fbi->reg_lccr1) ||
699 (__raw_readl(fbi->mmio_base + LCCR2) != fbi->reg_lccr2) ||
700 (__raw_readl(fbi->mmio_base + LCCR3) != fbi->reg_lccr3) ||
701 (__raw_readl(fbi->mmio_base + FDADR0) != fbi->fdadr[0]) ||
702 (__raw_readl(fbi->mmio_base + FDADR1) != fbi->fdadr[1]))
703 pxafb_schedule_work(fbi, C_REENABLE);
709 * NOTE! The following functions are purely helpers for set_ctrlr_state.
710 * Do not call them directly; set_ctrlr_state does the correct serialisation
711 * to ensure that things happen in the right way 100% of time time.
714 static inline void __pxafb_backlight_power(struct pxafb_info *fbi, int on)
716 pr_debug("pxafb: backlight o%s\n", on ? "n" : "ff");
718 if (pxafb_backlight_power)
719 pxafb_backlight_power(on);
722 static inline void __pxafb_lcd_power(struct pxafb_info *fbi, int on)
724 pr_debug("pxafb: LCD power o%s\n", on ? "n" : "ff");
727 pxafb_lcd_power(on, &fbi->fb.var);
730 static void pxafb_setup_gpio(struct pxafb_info *fbi)
733 unsigned int lccr0 = fbi->lccr0;
736 * setup is based on type of panel supported
739 /* 4 bit interface */
740 if ((lccr0 & LCCR0_CMS) == LCCR0_Mono &&
741 (lccr0 & LCCR0_SDS) == LCCR0_Sngl &&
742 (lccr0 & LCCR0_DPD) == LCCR0_4PixMono)
745 /* 8 bit interface */
746 else if (((lccr0 & LCCR0_CMS) == LCCR0_Mono &&
747 ((lccr0 & LCCR0_SDS) == LCCR0_Dual ||
748 (lccr0 & LCCR0_DPD) == LCCR0_8PixMono)) ||
749 ((lccr0 & LCCR0_CMS) == LCCR0_Color &&
750 (lccr0 & LCCR0_PAS) == LCCR0_Pas &&
751 (lccr0 & LCCR0_SDS) == LCCR0_Sngl))
754 /* 16 bit interface */
755 else if ((lccr0 & LCCR0_CMS) == LCCR0_Color &&
756 ((lccr0 & LCCR0_SDS) == LCCR0_Dual ||
757 (lccr0 & LCCR0_PAS) == LCCR0_Act))
761 printk(KERN_ERR "pxafb_setup_gpio: unable to determine "
766 for (gpio = 58; ldd_bits; gpio++, ldd_bits--)
767 pxa_gpio_mode(gpio | GPIO_ALT_FN_2_OUT);
768 pxa_gpio_mode(GPIO74_LCD_FCLK_MD);
769 pxa_gpio_mode(GPIO75_LCD_LCLK_MD);
770 pxa_gpio_mode(GPIO76_LCD_PCLK_MD);
771 pxa_gpio_mode(GPIO77_LCD_ACBIAS_MD);
774 static void pxafb_enable_controller(struct pxafb_info *fbi)
776 pr_debug("pxafb: Enabling LCD controller\n");
777 pr_debug("fdadr0 0x%08x\n", (unsigned int) fbi->fdadr[0]);
778 pr_debug("fdadr1 0x%08x\n", (unsigned int) fbi->fdadr[1]);
779 pr_debug("reg_lccr0 0x%08x\n", (unsigned int) fbi->reg_lccr0);
780 pr_debug("reg_lccr1 0x%08x\n", (unsigned int) fbi->reg_lccr1);
781 pr_debug("reg_lccr2 0x%08x\n", (unsigned int) fbi->reg_lccr2);
782 pr_debug("reg_lccr3 0x%08x\n", (unsigned int) fbi->reg_lccr3);
784 /* enable LCD controller clock */
785 clk_enable(fbi->clk);
787 /* Sequence from 11.7.10 */
788 __raw_writel(fbi->reg_lccr3, fbi->mmio_base + LCCR3);
789 __raw_writel(fbi->reg_lccr2, fbi->mmio_base + LCCR2);
790 __raw_writel(fbi->reg_lccr1, fbi->mmio_base + LCCR1);
791 __raw_writel(fbi->reg_lccr0 & ~LCCR0_ENB, fbi->mmio_base + LCCR0);
793 __raw_writel(fbi->fdadr[0], fbi->mmio_base + FDADR0);
794 __raw_writel(fbi->fdadr[1], fbi->mmio_base + FDADR1);
795 __raw_writel(fbi->reg_lccr0 | LCCR0_ENB, fbi->mmio_base + LCCR0);
798 static void pxafb_disable_controller(struct pxafb_info *fbi)
802 DECLARE_WAITQUEUE(wait, current);
804 set_current_state(TASK_UNINTERRUPTIBLE);
805 add_wait_queue(&fbi->ctrlr_wait, &wait);
807 /* Clear LCD Status Register */
808 __raw_writel(0xffffffff, fbi->mmio_base + LCSR);
810 lccr0 = __raw_readl(fbi->mmio_base + LCCR0) & ~LCCR0_LDM;
811 __raw_writel(lccr0, fbi->mmio_base + LCCR0);
812 __raw_writel(lccr0 | LCCR0_DIS, fbi->mmio_base + LCCR0);
814 schedule_timeout(200 * HZ / 1000);
815 remove_wait_queue(&fbi->ctrlr_wait, &wait);
817 /* disable LCD controller clock */
818 clk_disable(fbi->clk);
822 * pxafb_handle_irq: Handle 'LCD DONE' interrupts.
824 static irqreturn_t pxafb_handle_irq(int irq, void *dev_id)
826 struct pxafb_info *fbi = dev_id;
827 unsigned int lccr0, lcsr = __raw_readl(fbi->mmio_base + LCSR);
829 if (lcsr & LCSR_LDD) {
830 lccr0 = __raw_readl(fbi->mmio_base + LCCR0) | LCCR0_LDM;
831 __raw_writel(lccr0, fbi->mmio_base + LCCR0);
832 wake_up(&fbi->ctrlr_wait);
835 __raw_writel(lcsr, fbi->mmio_base + LCSR);
840 * This function must be called from task context only, since it will
841 * sleep when disabling the LCD controller, or if we get two contending
842 * processes trying to alter state.
844 static void set_ctrlr_state(struct pxafb_info *fbi, u_int state)
848 down(&fbi->ctrlr_sem);
850 old_state = fbi->state;
853 * Hack around fbcon initialisation.
855 if (old_state == C_STARTUP && state == C_REENABLE)
859 case C_DISABLE_CLKCHANGE:
861 * Disable controller for clock change. If the
862 * controller is already disabled, then do nothing.
864 if (old_state != C_DISABLE && old_state != C_DISABLE_PM) {
866 /* TODO __pxafb_lcd_power(fbi, 0); */
867 pxafb_disable_controller(fbi);
876 if (old_state != C_DISABLE) {
878 __pxafb_backlight_power(fbi, 0);
879 __pxafb_lcd_power(fbi, 0);
880 if (old_state != C_DISABLE_CLKCHANGE)
881 pxafb_disable_controller(fbi);
885 case C_ENABLE_CLKCHANGE:
887 * Enable the controller after clock change. Only
888 * do this if we were disabled for the clock change.
890 if (old_state == C_DISABLE_CLKCHANGE) {
891 fbi->state = C_ENABLE;
892 pxafb_enable_controller(fbi);
893 /* TODO __pxafb_lcd_power(fbi, 1); */
899 * Re-enable the controller only if it was already
900 * enabled. This is so we reprogram the control
903 if (old_state == C_ENABLE) {
904 __pxafb_lcd_power(fbi, 0);
905 pxafb_disable_controller(fbi);
906 pxafb_setup_gpio(fbi);
907 pxafb_enable_controller(fbi);
908 __pxafb_lcd_power(fbi, 1);
914 * Re-enable the controller after PM. This is not
915 * perfect - think about the case where we were doing
916 * a clock change, and we suspended half-way through.
918 if (old_state != C_DISABLE_PM)
924 * Power up the LCD screen, enable controller, and
925 * turn on the backlight.
927 if (old_state != C_ENABLE) {
928 fbi->state = C_ENABLE;
929 pxafb_setup_gpio(fbi);
930 pxafb_enable_controller(fbi);
931 __pxafb_lcd_power(fbi, 1);
932 __pxafb_backlight_power(fbi, 1);
940 * Our LCD controller task (which is called when we blank or unblank)
943 static void pxafb_task(struct work_struct *work)
945 struct pxafb_info *fbi =
946 container_of(work, struct pxafb_info, task);
947 u_int state = xchg(&fbi->task_state, -1);
949 set_ctrlr_state(fbi, state);
952 #ifdef CONFIG_CPU_FREQ
954 * CPU clock speed change handler. We need to adjust the LCD timing
955 * parameters when the CPU clock is adjusted by the power management
958 * TODO: Determine why f->new != 10*get_lclk_frequency_10khz()
961 pxafb_freq_transition(struct notifier_block *nb, unsigned long val, void *data)
963 struct pxafb_info *fbi = TO_INF(nb, freq_transition);
964 /* TODO struct cpufreq_freqs *f = data; */
968 case CPUFREQ_PRECHANGE:
969 set_ctrlr_state(fbi, C_DISABLE_CLKCHANGE);
972 case CPUFREQ_POSTCHANGE:
973 pcd = get_pcd(fbi, fbi->fb.var.pixclock);
974 set_hsync_time(fbi, pcd);
975 fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) |
976 LCCR3_PixClkDiv(pcd);
977 set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE);
984 pxafb_freq_policy(struct notifier_block *nb, unsigned long val, void *data)
986 struct pxafb_info *fbi = TO_INF(nb, freq_policy);
987 struct fb_var_screeninfo *var = &fbi->fb.var;
988 struct cpufreq_policy *policy = data;
992 case CPUFREQ_INCOMPATIBLE:
993 pr_debug("min dma period: %d ps, "
994 "new clock %d kHz\n", pxafb_display_dma_period(var),
996 /* TODO: fill in min/max values */
1005 * Power management hooks. Note that we won't be called from IRQ context,
1006 * unlike the blank functions above, so we may sleep.
1008 static int pxafb_suspend(struct platform_device *dev, pm_message_t state)
1010 struct pxafb_info *fbi = platform_get_drvdata(dev);
1012 set_ctrlr_state(fbi, C_DISABLE_PM);
1016 static int pxafb_resume(struct platform_device *dev)
1018 struct pxafb_info *fbi = platform_get_drvdata(dev);
1020 set_ctrlr_state(fbi, C_ENABLE_PM);
1024 #define pxafb_suspend NULL
1025 #define pxafb_resume NULL
1029 * pxafb_map_video_memory():
1030 * Allocates the DRAM memory for the frame buffer. This buffer is
1031 * remapped into a non-cached, non-buffered, memory region to
1032 * allow palette and pixel writes to occur without flushing the
1033 * cache. Once this area is remapped, all virtual memory
1034 * access to the video memory should occur at the new region.
1036 static int __init pxafb_map_video_memory(struct pxafb_info *fbi)
1039 * We reserve one page for the palette, plus the size
1040 * of the framebuffer.
1042 fbi->map_size = PAGE_ALIGN(fbi->fb.fix.smem_len + PAGE_SIZE);
1043 fbi->map_cpu = dma_alloc_writecombine(fbi->dev, fbi->map_size,
1044 &fbi->map_dma, GFP_KERNEL);
1047 /* prevent initial garbage on screen */
1048 memset(fbi->map_cpu, 0, fbi->map_size);
1049 fbi->fb.screen_base = fbi->map_cpu + PAGE_SIZE;
1050 fbi->screen_dma = fbi->map_dma + PAGE_SIZE;
1052 * FIXME: this is actually the wrong thing to place in
1053 * smem_start. But fbdev suffers from the problem that
1054 * it needs an API which doesn't exist (in this case,
1055 * dma_writecombine_mmap)
1057 fbi->fb.fix.smem_start = fbi->screen_dma;
1058 fbi->palette_size = fbi->fb.var.bits_per_pixel == 8 ? 256 : 16;
1060 fbi->dma_buff = (void *)fbi->map_cpu;
1061 fbi->dma_buff_phys = fbi->map_dma;
1062 fbi->palette_cpu = (u16 *)&fbi->dma_buff->palette[0];
1065 return fbi->map_cpu ? 0 : -ENOMEM;
1068 static void pxafb_decode_mode_info(struct pxafb_info *fbi,
1069 struct pxafb_mode_info *modes,
1070 unsigned int num_modes)
1072 unsigned int i, smemlen;
1074 pxafb_setmode(&fbi->fb.var, &modes[0]);
1076 for (i = 0; i < num_modes; i++) {
1077 smemlen = modes[i].xres * modes[i].yres * modes[i].bpp / 8;
1078 if (smemlen > fbi->fb.fix.smem_len)
1079 fbi->fb.fix.smem_len = smemlen;
1083 static int pxafb_decode_mach_info(struct pxafb_info *fbi,
1084 struct pxafb_mach_info *inf)
1086 unsigned int lcd_conn = inf->lcd_conn;
1088 fbi->cmap_inverse = inf->cmap_inverse;
1089 fbi->cmap_static = inf->cmap_static;
1091 switch (lcd_conn & 0xf) {
1092 case LCD_TYPE_MONO_STN:
1093 fbi->lccr0 = LCCR0_CMS;
1095 case LCD_TYPE_MONO_DSTN:
1096 fbi->lccr0 = LCCR0_CMS | LCCR0_SDS;
1098 case LCD_TYPE_COLOR_STN:
1101 case LCD_TYPE_COLOR_DSTN:
1102 fbi->lccr0 = LCCR0_SDS;
1104 case LCD_TYPE_COLOR_TFT:
1105 fbi->lccr0 = LCCR0_PAS;
1107 case LCD_TYPE_SMART_PANEL:
1108 fbi->lccr0 = LCCR0_LCDT | LCCR0_PAS;
1111 /* fall back to backward compatibility way */
1112 fbi->lccr0 = inf->lccr0;
1113 fbi->lccr3 = inf->lccr3;
1114 fbi->lccr4 = inf->lccr4;
1118 if (lcd_conn == LCD_MONO_STN_8BPP)
1119 fbi->lccr0 |= LCCR0_DPD;
1121 fbi->lccr3 = LCCR3_Acb((inf->lcd_conn >> 10) & 0xff);
1122 fbi->lccr3 |= (lcd_conn & LCD_BIAS_ACTIVE_LOW) ? LCCR3_OEP : 0;
1123 fbi->lccr3 |= (lcd_conn & LCD_PCLK_EDGE_FALL) ? LCCR3_PCP : 0;
1125 pxafb_decode_mode_info(fbi, inf->modes, inf->num_modes);
1129 static struct pxafb_info * __init pxafb_init_fbinfo(struct device *dev)
1131 struct pxafb_info *fbi;
1133 struct pxafb_mach_info *inf = dev->platform_data;
1134 struct pxafb_mode_info *mode = inf->modes;
1136 /* Alloc the pxafb_info and pseudo_palette in one step */
1137 fbi = kmalloc(sizeof(struct pxafb_info) + sizeof(u32) * 16, GFP_KERNEL);
1141 memset(fbi, 0, sizeof(struct pxafb_info));
1144 fbi->clk = clk_get(dev, "LCDCLK");
1145 if (IS_ERR(fbi->clk)) {
1150 strcpy(fbi->fb.fix.id, PXA_NAME);
1152 fbi->fb.fix.type = FB_TYPE_PACKED_PIXELS;
1153 fbi->fb.fix.type_aux = 0;
1154 fbi->fb.fix.xpanstep = 0;
1155 fbi->fb.fix.ypanstep = 0;
1156 fbi->fb.fix.ywrapstep = 0;
1157 fbi->fb.fix.accel = FB_ACCEL_NONE;
1159 fbi->fb.var.nonstd = 0;
1160 fbi->fb.var.activate = FB_ACTIVATE_NOW;
1161 fbi->fb.var.height = -1;
1162 fbi->fb.var.width = -1;
1163 fbi->fb.var.accel_flags = 0;
1164 fbi->fb.var.vmode = FB_VMODE_NONINTERLACED;
1166 fbi->fb.fbops = &pxafb_ops;
1167 fbi->fb.flags = FBINFO_DEFAULT;
1171 addr = addr + sizeof(struct pxafb_info);
1172 fbi->fb.pseudo_palette = addr;
1174 fbi->state = C_STARTUP;
1175 fbi->task_state = (u_char)-1;
1177 pxafb_decode_mach_info(fbi, inf);
1179 init_waitqueue_head(&fbi->ctrlr_wait);
1180 INIT_WORK(&fbi->task, pxafb_task);
1181 init_MUTEX(&fbi->ctrlr_sem);
1186 #ifdef CONFIG_FB_PXA_PARAMETERS
1187 static int __init parse_opt_mode(struct device *dev, const char *this_opt)
1189 struct pxafb_mach_info *inf = dev->platform_data;
1191 const char *name = this_opt+5;
1192 unsigned int namelen = strlen(name);
1193 int res_specified = 0, bpp_specified = 0;
1194 unsigned int xres = 0, yres = 0, bpp = 0;
1195 int yres_specified = 0;
1197 for (i = namelen-1; i >= 0; i--) {
1201 if (!bpp_specified && !yres_specified) {
1202 bpp = simple_strtoul(&name[i+1], NULL, 0);
1208 if (!yres_specified) {
1209 yres = simple_strtoul(&name[i+1], NULL, 0);
1220 if (i < 0 && yres_specified) {
1221 xres = simple_strtoul(name, NULL, 0);
1225 if (res_specified) {
1226 dev_info(dev, "overriding resolution: %dx%d\n", xres, yres);
1227 inf->modes[0].xres = xres; inf->modes[0].yres = yres;
1236 inf->modes[0].bpp = bpp;
1237 dev_info(dev, "overriding bit depth: %d\n", bpp);
1240 dev_err(dev, "Depth %d is not valid\n", bpp);
1246 static int __init parse_opt(struct device *dev, char *this_opt)
1248 struct pxafb_mach_info *inf = dev->platform_data;
1249 struct pxafb_mode_info *mode = &inf->modes[0];
1254 if (!strncmp(this_opt, "mode:", 5)) {
1255 return parse_opt_mode(dev, this_opt);
1256 } else if (!strncmp(this_opt, "pixclock:", 9)) {
1257 mode->pixclock = simple_strtoul(this_opt+9, NULL, 0);
1258 sprintf(s, "pixclock: %ld\n", mode->pixclock);
1259 } else if (!strncmp(this_opt, "left:", 5)) {
1260 mode->left_margin = simple_strtoul(this_opt+5, NULL, 0);
1261 sprintf(s, "left: %u\n", mode->left_margin);
1262 } else if (!strncmp(this_opt, "right:", 6)) {
1263 mode->right_margin = simple_strtoul(this_opt+6, NULL, 0);
1264 sprintf(s, "right: %u\n", mode->right_margin);
1265 } else if (!strncmp(this_opt, "upper:", 6)) {
1266 mode->upper_margin = simple_strtoul(this_opt+6, NULL, 0);
1267 sprintf(s, "upper: %u\n", mode->upper_margin);
1268 } else if (!strncmp(this_opt, "lower:", 6)) {
1269 mode->lower_margin = simple_strtoul(this_opt+6, NULL, 0);
1270 sprintf(s, "lower: %u\n", mode->lower_margin);
1271 } else if (!strncmp(this_opt, "hsynclen:", 9)) {
1272 mode->hsync_len = simple_strtoul(this_opt+9, NULL, 0);
1273 sprintf(s, "hsynclen: %u\n", mode->hsync_len);
1274 } else if (!strncmp(this_opt, "vsynclen:", 9)) {
1275 mode->vsync_len = simple_strtoul(this_opt+9, NULL, 0);
1276 sprintf(s, "vsynclen: %u\n", mode->vsync_len);
1277 } else if (!strncmp(this_opt, "hsync:", 6)) {
1278 if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1279 sprintf(s, "hsync: Active Low\n");
1280 mode->sync &= ~FB_SYNC_HOR_HIGH_ACT;
1282 sprintf(s, "hsync: Active High\n");
1283 mode->sync |= FB_SYNC_HOR_HIGH_ACT;
1285 } else if (!strncmp(this_opt, "vsync:", 6)) {
1286 if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1287 sprintf(s, "vsync: Active Low\n");
1288 mode->sync &= ~FB_SYNC_VERT_HIGH_ACT;
1290 sprintf(s, "vsync: Active High\n");
1291 mode->sync |= FB_SYNC_VERT_HIGH_ACT;
1293 } else if (!strncmp(this_opt, "dpc:", 4)) {
1294 if (simple_strtoul(this_opt+4, NULL, 0) == 0) {
1295 sprintf(s, "double pixel clock: false\n");
1296 inf->lccr3 &= ~LCCR3_DPC;
1298 sprintf(s, "double pixel clock: true\n");
1299 inf->lccr3 |= LCCR3_DPC;
1301 } else if (!strncmp(this_opt, "outputen:", 9)) {
1302 if (simple_strtoul(this_opt+9, NULL, 0) == 0) {
1303 sprintf(s, "output enable: active low\n");
1304 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnL;
1306 sprintf(s, "output enable: active high\n");
1307 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnH;
1309 } else if (!strncmp(this_opt, "pixclockpol:", 12)) {
1310 if (simple_strtoul(this_opt+12, NULL, 0) == 0) {
1311 sprintf(s, "pixel clock polarity: falling edge\n");
1312 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixFlEdg;
1314 sprintf(s, "pixel clock polarity: rising edge\n");
1315 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixRsEdg;
1317 } else if (!strncmp(this_opt, "color", 5)) {
1318 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Color;
1319 } else if (!strncmp(this_opt, "mono", 4)) {
1320 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Mono;
1321 } else if (!strncmp(this_opt, "active", 6)) {
1322 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Act;
1323 } else if (!strncmp(this_opt, "passive", 7)) {
1324 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Pas;
1325 } else if (!strncmp(this_opt, "single", 6)) {
1326 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Sngl;
1327 } else if (!strncmp(this_opt, "dual", 4)) {
1328 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Dual;
1329 } else if (!strncmp(this_opt, "4pix", 4)) {
1330 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_4PixMono;
1331 } else if (!strncmp(this_opt, "8pix", 4)) {
1332 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_8PixMono;
1334 dev_err(dev, "unknown option: %s\n", this_opt);
1339 dev_info(dev, "override %s", s);
1344 static int __init pxafb_parse_options(struct device *dev, char *options)
1349 if (!options || !*options)
1352 dev_dbg(dev, "options are \"%s\"\n", options ? options : "null");
1354 /* could be made table driven or similar?... */
1355 while ((this_opt = strsep(&options, ",")) != NULL) {
1356 ret = parse_opt(dev, this_opt);
1363 static char g_options[256] __devinitdata = "";
1365 #ifndef CONFIG_MODULES
1366 static int __devinit pxafb_setup_options(void)
1368 char *options = NULL;
1370 if (fb_get_options("pxafb", &options))
1374 strlcpy(g_options, options, sizeof(g_options));
1379 #define pxafb_setup_options() (0)
1381 module_param_string(options, g_options, sizeof(g_options), 0);
1382 MODULE_PARM_DESC(options, "LCD parameters (see Documentation/fb/pxafb.txt)");
1386 #define pxafb_parse_options(...) (0)
1387 #define pxafb_setup_options() (0)
1390 static int __init pxafb_probe(struct platform_device *dev)
1392 struct pxafb_info *fbi;
1393 struct pxafb_mach_info *inf;
1397 dev_dbg(&dev->dev, "pxafb_probe\n");
1399 inf = dev->dev.platform_data;
1405 ret = pxafb_parse_options(&dev->dev, g_options);
1410 /* Check for various illegal bit-combinations. Currently only
1411 * a warning is given. */
1413 if (inf->lccr0 & LCCR0_INVALID_CONFIG_MASK)
1414 dev_warn(&dev->dev, "machine LCCR0 setting contains "
1415 "illegal bits: %08x\n",
1416 inf->lccr0 & LCCR0_INVALID_CONFIG_MASK);
1417 if (inf->lccr3 & LCCR3_INVALID_CONFIG_MASK)
1418 dev_warn(&dev->dev, "machine LCCR3 setting contains "
1419 "illegal bits: %08x\n",
1420 inf->lccr3 & LCCR3_INVALID_CONFIG_MASK);
1421 if (inf->lccr0 & LCCR0_DPD &&
1422 ((inf->lccr0 & LCCR0_PAS) != LCCR0_Pas ||
1423 (inf->lccr0 & LCCR0_SDS) != LCCR0_Sngl ||
1424 (inf->lccr0 & LCCR0_CMS) != LCCR0_Mono))
1425 dev_warn(&dev->dev, "Double Pixel Data (DPD) mode is "
1426 "only valid in passive mono"
1427 " single panel mode\n");
1428 if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Act &&
1429 (inf->lccr0 & LCCR0_SDS) == LCCR0_Dual)
1430 dev_warn(&dev->dev, "Dual panel only valid in passive mode\n");
1431 if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Pas &&
1432 (inf->modes->upper_margin || inf->modes->lower_margin))
1433 dev_warn(&dev->dev, "Upper and lower margins must be 0 in "
1437 dev_dbg(&dev->dev, "got a %dx%dx%d LCD\n",
1441 if (inf->modes->xres == 0 ||
1442 inf->modes->yres == 0 ||
1443 inf->modes->bpp == 0) {
1444 dev_err(&dev->dev, "Invalid resolution or bit depth\n");
1448 pxafb_backlight_power = inf->pxafb_backlight_power;
1449 pxafb_lcd_power = inf->pxafb_lcd_power;
1450 fbi = pxafb_init_fbinfo(&dev->dev);
1452 /* only reason for pxafb_init_fbinfo to fail is kmalloc */
1453 dev_err(&dev->dev, "Failed to initialize framebuffer device\n");
1458 r = platform_get_resource(dev, IORESOURCE_MEM, 0);
1460 dev_err(&dev->dev, "no I/O memory resource defined\n");
1465 r = request_mem_region(r->start, r->end - r->start + 1, dev->name);
1467 dev_err(&dev->dev, "failed to request I/O memory\n");
1472 fbi->mmio_base = ioremap(r->start, r->end - r->start + 1);
1473 if (fbi->mmio_base == NULL) {
1474 dev_err(&dev->dev, "failed to map I/O memory\n");
1476 goto failed_free_res;
1479 /* Initialize video memory */
1480 ret = pxafb_map_video_memory(fbi);
1482 dev_err(&dev->dev, "Failed to allocate video RAM: %d\n", ret);
1484 goto failed_free_io;
1487 irq = platform_get_irq(dev, 0);
1489 dev_err(&dev->dev, "no IRQ defined\n");
1491 goto failed_free_mem;
1494 ret = request_irq(irq, pxafb_handle_irq, IRQF_DISABLED, "LCD", fbi);
1496 dev_err(&dev->dev, "request_irq failed: %d\n", ret);
1498 goto failed_free_mem;
1502 * This makes sure that our colour bitfield
1503 * descriptors are correctly initialised.
1505 pxafb_check_var(&fbi->fb.var, &fbi->fb);
1506 pxafb_set_par(&fbi->fb);
1508 platform_set_drvdata(dev, fbi);
1510 ret = register_framebuffer(&fbi->fb);
1513 "Failed to register framebuffer device: %d\n", ret);
1514 goto failed_free_irq;
1517 #ifdef CONFIG_CPU_FREQ
1518 fbi->freq_transition.notifier_call = pxafb_freq_transition;
1519 fbi->freq_policy.notifier_call = pxafb_freq_policy;
1520 cpufreq_register_notifier(&fbi->freq_transition,
1521 CPUFREQ_TRANSITION_NOTIFIER);
1522 cpufreq_register_notifier(&fbi->freq_policy,
1523 CPUFREQ_POLICY_NOTIFIER);
1527 * Ok, now enable the LCD controller
1529 set_ctrlr_state(fbi, C_ENABLE);
1536 release_mem_region(r->start, r->end - r->start + 1);
1538 iounmap(fbi->mmio_base);
1540 dma_free_writecombine(&dev->dev, fbi->map_size,
1541 fbi->map_cpu, fbi->map_dma);
1543 platform_set_drvdata(dev, NULL);
1548 static struct platform_driver pxafb_driver = {
1549 .probe = pxafb_probe,
1550 .suspend = pxafb_suspend,
1551 .resume = pxafb_resume,
1553 .name = "pxa2xx-fb",
1557 static int __devinit pxafb_init(void)
1559 if (pxafb_setup_options())
1562 return platform_driver_register(&pxafb_driver);
1565 module_init(pxafb_init);
1567 MODULE_DESCRIPTION("loadable framebuffer driver for PXA");
1568 MODULE_LICENSE("GPL");