2 * linux/drivers/video/pm3fb.c -- 3DLabs Permedia3 frame buffer device
4 * Copyright (C) 2001 Romain Dolbeau <romain@dolbeau.org>.
6 * Ported to 2.6 kernel on 1 May 2007 by Krzysztof Helt <krzysztof.h1@wp.pl>
9 * Based on code written by:
10 * Sven Luther, <luther@dpt-info.u-strasbg.fr>
11 * Alan Hourihane, <alanh@fairlite.demon.co.uk>
12 * Russell King, <rmk@arm.linux.org.uk>
13 * Based on linux/drivers/video/skeletonfb.c:
14 * Copyright (C) 1997 Geert Uytterhoeven
15 * Based on linux/driver/video/pm2fb.c:
16 * Copyright (C) 1998-1999 Ilario Nardinocchi (nardinoc@CS.UniBO.IT)
17 * Copyright (C) 1999 Jakub Jelinek (jakub@redhat.com)
19 * This file is subject to the terms and conditions of the GNU General Public
20 * License. See the file COPYING in the main directory of this archive for
25 #include <linux/module.h>
26 #include <linux/kernel.h>
27 #include <linux/errno.h>
28 #include <linux/string.h>
30 #include <linux/slab.h>
31 #include <linux/delay.h>
33 #include <linux/init.h>
34 #include <linux/pci.h>
39 #include <video/pm3fb.h>
41 #if !defined(CONFIG_PCI)
42 #error "Only generic PCI cards supported."
45 #undef PM3FB_MASTER_DEBUG
46 #ifdef PM3FB_MASTER_DEBUG
47 #define DPRINTK(a, b...) \
48 printk(KERN_DEBUG "pm3fb: %s: " a, __FUNCTION__ , ## b)
50 #define DPRINTK(a, b...)
53 #define PM3_PIXMAP_SIZE (2048 * 4)
58 static char *mode_option __devinitdata;
59 static int noaccel __devinitdata;
63 static int nomtrr __devinitdata;
67 * This structure defines the hardware state of the graphics card. Normally
68 * you place this in a header file in linux/include/video. This file usually
69 * also includes register information. That allows other driver subsystems
70 * and userland applications the ability to use the same header file to
71 * avoid duplicate work and easy porting of software.
74 unsigned char __iomem *v_regs;/* virtual address of p_regs */
75 u32 video; /* video flags before blanking */
76 u32 base; /* screen base in 128 bits unit */
82 * Here we define the default structs fb_fix_screeninfo and fb_var_screeninfo
83 * if we don't use modedb. If we do use modedb see pm3fb_init how to use it
84 * to get a fb_var_screeninfo. Otherwise define a default var as well.
86 static struct fb_fix_screeninfo pm3fb_fix __devinitdata = {
88 .type = FB_TYPE_PACKED_PIXELS,
89 .visual = FB_VISUAL_PSEUDOCOLOR,
93 .accel = FB_ACCEL_3DLABS_PERMEDIA3,
100 static inline u32 PM3_READ_REG(struct pm3_par *par, s32 off)
102 return fb_readl(par->v_regs + off);
105 static inline void PM3_WRITE_REG(struct pm3_par *par, s32 off, u32 v)
107 fb_writel(v, par->v_regs + off);
110 static inline void PM3_WAIT(struct pm3_par *par, u32 n)
112 while (PM3_READ_REG(par, PM3InFIFOSpace) < n);
115 static inline void PM3_WRITE_DAC_REG(struct pm3_par *par, unsigned r, u8 v)
118 PM3_WRITE_REG(par, PM3RD_IndexHigh, (r >> 8) & 0xff);
119 PM3_WRITE_REG(par, PM3RD_IndexLow, r & 0xff);
121 PM3_WRITE_REG(par, PM3RD_IndexedData, v);
125 static inline void pm3fb_set_color(struct pm3_par *par, unsigned char regno,
126 unsigned char r, unsigned char g, unsigned char b)
129 PM3_WRITE_REG(par, PM3RD_PaletteWriteAddress, regno);
131 PM3_WRITE_REG(par, PM3RD_PaletteData, r);
133 PM3_WRITE_REG(par, PM3RD_PaletteData, g);
135 PM3_WRITE_REG(par, PM3RD_PaletteData, b);
139 static void pm3fb_clear_colormap(struct pm3_par *par,
140 unsigned char r, unsigned char g, unsigned char b)
144 for (i = 0; i < 256 ; i++)
145 pm3fb_set_color(par, i, r, g, b);
149 /* Calculating various clock parameters */
150 static void pm3fb_calculate_clock(unsigned long reqclock,
151 unsigned char *prescale,
152 unsigned char *feedback,
153 unsigned char *postscale)
160 for (f = 1; f < 256; f++) {
161 for (pre = 1; pre < 256; pre++) {
162 for (post = 0; post < 5; post++) {
163 freq = ((2*PM3_REF_CLOCK * f) >> post) / pre;
164 currerr = (reqclock > freq)
167 if (currerr < freqerr) {
178 static inline int pm3fb_depth(const struct fb_var_screeninfo *var)
180 if (var->bits_per_pixel == 16)
181 return var->red.length + var->green.length
184 return var->bits_per_pixel;
187 static inline int pm3fb_shift_bpp(unsigned bpp, int v)
197 DPRINTK("Unsupported depth %u\n", bpp);
202 static int pm3fb_sync(struct fb_info *info)
204 struct pm3_par *par = info->par;
207 PM3_WRITE_REG(par, PM3FilterMode, PM3FilterModeSync);
208 PM3_WRITE_REG(par, PM3Sync, 0);
211 while ((PM3_READ_REG(par, PM3OutFIFOWords)) == 0);
213 } while ((PM3_READ_REG(par, PM3OutputFifo)) != PM3Sync_Tag);
218 static void pm3fb_init_engine(struct fb_info *info)
220 struct pm3_par *par = info->par;
221 const u32 width = (info->var.xres_virtual + 7) & ~7;
224 PM3_WRITE_REG(par, PM3FilterMode, PM3FilterModeSync);
225 PM3_WRITE_REG(par, PM3StatisticMode, 0x0);
226 PM3_WRITE_REG(par, PM3DeltaMode, 0x0);
227 PM3_WRITE_REG(par, PM3RasterizerMode, 0x0);
228 PM3_WRITE_REG(par, PM3ScissorMode, 0x0);
229 PM3_WRITE_REG(par, PM3LineStippleMode, 0x0);
230 PM3_WRITE_REG(par, PM3AreaStippleMode, 0x0);
231 PM3_WRITE_REG(par, PM3GIDMode, 0x0);
232 PM3_WRITE_REG(par, PM3DepthMode, 0x0);
233 PM3_WRITE_REG(par, PM3StencilMode, 0x0);
234 PM3_WRITE_REG(par, PM3StencilData, 0x0);
235 PM3_WRITE_REG(par, PM3ColorDDAMode, 0x0);
236 PM3_WRITE_REG(par, PM3TextureCoordMode, 0x0);
237 PM3_WRITE_REG(par, PM3TextureIndexMode0, 0x0);
238 PM3_WRITE_REG(par, PM3TextureIndexMode1, 0x0);
239 PM3_WRITE_REG(par, PM3TextureReadMode, 0x0);
240 PM3_WRITE_REG(par, PM3LUTMode, 0x0);
241 PM3_WRITE_REG(par, PM3TextureFilterMode, 0x0);
242 PM3_WRITE_REG(par, PM3TextureCompositeMode, 0x0);
243 PM3_WRITE_REG(par, PM3TextureApplicationMode, 0x0);
244 PM3_WRITE_REG(par, PM3TextureCompositeColorMode1, 0x0);
245 PM3_WRITE_REG(par, PM3TextureCompositeAlphaMode1, 0x0);
246 PM3_WRITE_REG(par, PM3TextureCompositeColorMode0, 0x0);
247 PM3_WRITE_REG(par, PM3TextureCompositeAlphaMode0, 0x0);
248 PM3_WRITE_REG(par, PM3FogMode, 0x0);
249 PM3_WRITE_REG(par, PM3ChromaTestMode, 0x0);
250 PM3_WRITE_REG(par, PM3AlphaTestMode, 0x0);
251 PM3_WRITE_REG(par, PM3AntialiasMode, 0x0);
252 PM3_WRITE_REG(par, PM3YUVMode, 0x0);
253 PM3_WRITE_REG(par, PM3AlphaBlendColorMode, 0x0);
254 PM3_WRITE_REG(par, PM3AlphaBlendAlphaMode, 0x0);
255 PM3_WRITE_REG(par, PM3DitherMode, 0x0);
256 PM3_WRITE_REG(par, PM3LogicalOpMode, 0x0);
257 PM3_WRITE_REG(par, PM3RouterMode, 0x0);
258 PM3_WRITE_REG(par, PM3Window, 0x0);
260 PM3_WRITE_REG(par, PM3Config2D, 0x0);
262 PM3_WRITE_REG(par, PM3SpanColorMask, 0xffffffff);
264 PM3_WRITE_REG(par, PM3XBias, 0x0);
265 PM3_WRITE_REG(par, PM3YBias, 0x0);
266 PM3_WRITE_REG(par, PM3DeltaControl, 0x0);
268 PM3_WRITE_REG(par, PM3BitMaskPattern, 0xffffffff);
270 PM3_WRITE_REG(par, PM3FBDestReadEnables,
271 PM3FBDestReadEnables_E(0xff) |
272 PM3FBDestReadEnables_R(0xff) |
273 PM3FBDestReadEnables_ReferenceAlpha(0xff));
274 PM3_WRITE_REG(par, PM3FBDestReadBufferAddr0, 0x0);
275 PM3_WRITE_REG(par, PM3FBDestReadBufferOffset0, 0x0);
276 PM3_WRITE_REG(par, PM3FBDestReadBufferWidth0,
277 PM3FBDestReadBufferWidth_Width(width));
279 PM3_WRITE_REG(par, PM3FBDestReadMode,
280 PM3FBDestReadMode_ReadEnable |
281 PM3FBDestReadMode_Enable0);
282 PM3_WRITE_REG(par, PM3FBSourceReadBufferAddr, 0x0);
283 PM3_WRITE_REG(par, PM3FBSourceReadBufferOffset, 0x0);
284 PM3_WRITE_REG(par, PM3FBSourceReadBufferWidth,
285 PM3FBSourceReadBufferWidth_Width(width));
286 PM3_WRITE_REG(par, PM3FBSourceReadMode,
287 PM3FBSourceReadMode_Blocking |
288 PM3FBSourceReadMode_ReadEnable);
292 /* invert bits in bitmask */
293 unsigned long rm = 1 | (3 << 7);
294 switch (info->var.bits_per_pixel) {
296 PM3_WRITE_REG(par, PM3PixelSize,
297 PM3PixelSize_GLOBAL_8BIT);
303 PM3_WRITE_REG(par, PM3PixelSize,
304 PM3PixelSize_GLOBAL_16BIT);
310 PM3_WRITE_REG(par, PM3PixelSize,
311 PM3PixelSize_GLOBAL_32BIT);
314 DPRINTK(1, "Unsupported depth %d\n",
315 info->var.bits_per_pixel);
318 PM3_WRITE_REG(par, PM3RasterizerMode, rm);
322 PM3_WRITE_REG(par, PM3FBSoftwareWriteMask, 0xffffffff);
323 PM3_WRITE_REG(par, PM3FBHardwareWriteMask, 0xffffffff);
324 PM3_WRITE_REG(par, PM3FBWriteMode,
325 PM3FBWriteMode_WriteEnable |
326 PM3FBWriteMode_OpaqueSpan |
327 PM3FBWriteMode_Enable0);
328 PM3_WRITE_REG(par, PM3FBWriteBufferAddr0, 0x0);
329 PM3_WRITE_REG(par, PM3FBWriteBufferOffset0, 0x0);
330 PM3_WRITE_REG(par, PM3FBWriteBufferWidth0,
331 PM3FBWriteBufferWidth_Width(width));
333 PM3_WRITE_REG(par, PM3SizeOfFramebuffer, 0x0);
335 /* size in lines of FB */
336 unsigned long sofb = info->screen_size /
337 info->fix.line_length;
339 PM3_WRITE_REG(par, PM3SizeOfFramebuffer, 4095);
341 PM3_WRITE_REG(par, PM3SizeOfFramebuffer, sofb);
343 switch (info->var.bits_per_pixel) {
345 PM3_WRITE_REG(par, PM3DitherMode,
346 (1 << 10) | (2 << 3));
349 PM3_WRITE_REG(par, PM3DitherMode,
350 (1 << 10) | (1 << 3));
353 PM3_WRITE_REG(par, PM3DitherMode,
354 (1 << 10) | (0 << 3));
357 DPRINTK(1, "Unsupported depth %d\n",
358 info->current_par->depth);
363 PM3_WRITE_REG(par, PM3dXDom, 0x0);
364 PM3_WRITE_REG(par, PM3dXSub, 0x0);
365 PM3_WRITE_REG(par, PM3dY, 1 << 16);
366 PM3_WRITE_REG(par, PM3StartXDom, 0x0);
367 PM3_WRITE_REG(par, PM3StartXSub, 0x0);
368 PM3_WRITE_REG(par, PM3StartY, 0x0);
369 PM3_WRITE_REG(par, PM3Count, 0x0);
371 /* Disable LocalBuffer. better safe than sorry */
372 PM3_WRITE_REG(par, PM3LBDestReadMode, 0x0);
373 PM3_WRITE_REG(par, PM3LBDestReadEnables, 0x0);
374 PM3_WRITE_REG(par, PM3LBSourceReadMode, 0x0);
375 PM3_WRITE_REG(par, PM3LBWriteMode, 0x0);
380 static void pm3fb_fillrect(struct fb_info *info,
381 const struct fb_fillrect *region)
383 struct pm3_par *par = info->par;
384 struct fb_fillrect modded;
387 u32 color = (info->fix.visual == FB_VISUAL_TRUECOLOR) ?
388 ((u32 *)info->pseudo_palette)[region->color] : region->color;
390 if (info->state != FBINFO_STATE_RUNNING)
392 if (info->flags & FBINFO_HWACCEL_DISABLED) {
393 cfb_fillrect(info, region);
396 if (region->rop == ROP_COPY )
397 rop = PM3Config2D_ForegroundROP(0x3); /* GXcopy */
399 rop = PM3Config2D_ForegroundROP(0x6) | /* GXxor */
400 PM3Config2D_FBDestReadEnable;
402 vxres = info->var.xres_virtual;
403 vyres = info->var.yres_virtual;
405 memcpy(&modded, region, sizeof(struct fb_fillrect));
407 if (!modded.width || !modded.height ||
408 modded.dx >= vxres || modded.dy >= vyres)
411 if (modded.dx + modded.width > vxres)
412 modded.width = vxres - modded.dx;
413 if (modded.dy + modded.height > vyres)
414 modded.height = vyres - modded.dy;
416 if (info->var.bits_per_pixel == 8)
418 if (info->var.bits_per_pixel <= 16)
419 color |= color << 16;
422 /* ROP Ox3 is GXcopy */
423 PM3_WRITE_REG(par, PM3Config2D,
424 PM3Config2D_UseConstantSource |
425 PM3Config2D_ForegroundROPEnable |
427 PM3Config2D_FBWriteEnable);
429 PM3_WRITE_REG(par, PM3ForegroundColor, color);
431 PM3_WRITE_REG(par, PM3RectanglePosition,
432 PM3RectanglePosition_XOffset(modded.dx) |
433 PM3RectanglePosition_YOffset(modded.dy));
435 PM3_WRITE_REG(par, PM3Render2D,
436 PM3Render2D_XPositive |
437 PM3Render2D_YPositive |
438 PM3Render2D_Operation_Normal |
439 PM3Render2D_SpanOperation |
440 PM3Render2D_Width(modded.width) |
441 PM3Render2D_Height(modded.height));
444 static void pm3fb_copyarea(struct fb_info *info,
445 const struct fb_copyarea *area)
447 struct pm3_par *par = info->par;
448 struct fb_copyarea modded;
450 int x_align, o_x, o_y;
452 if (info->state != FBINFO_STATE_RUNNING)
454 if (info->flags & FBINFO_HWACCEL_DISABLED) {
455 cfb_copyarea(info, area);
459 memcpy(&modded, area, sizeof(struct fb_copyarea));
461 vxres = info->var.xres_virtual;
462 vyres = info->var.yres_virtual;
464 if (!modded.width || !modded.height ||
465 modded.sx >= vxres || modded.sy >= vyres ||
466 modded.dx >= vxres || modded.dy >= vyres)
469 if (modded.sx + modded.width > vxres)
470 modded.width = vxres - modded.sx;
471 if (modded.dx + modded.width > vxres)
472 modded.width = vxres - modded.dx;
473 if (modded.sy + modded.height > vyres)
474 modded.height = vyres - modded.sy;
475 if (modded.dy + modded.height > vyres)
476 modded.height = vyres - modded.dy;
478 o_x = modded.sx - modded.dx; /*(sx > dx ) ? (sx - dx) : (dx - sx); */
479 o_y = modded.sy - modded.dy; /*(sy > dy ) ? (sy - dy) : (dy - sy); */
481 x_align = (modded.sx & 0x1f);
485 PM3_WRITE_REG(par, PM3Config2D,
486 PM3Config2D_UserScissorEnable |
487 PM3Config2D_ForegroundROPEnable |
488 PM3Config2D_Blocking |
489 PM3Config2D_ForegroundROP(0x3) | /* Ox3 is GXcopy */
490 PM3Config2D_FBWriteEnable);
492 PM3_WRITE_REG(par, PM3ScissorMinXY,
493 ((modded.dy & 0x0fff) << 16) | (modded.dx & 0x0fff));
494 PM3_WRITE_REG(par, PM3ScissorMaxXY,
495 (((modded.dy + modded.height) & 0x0fff) << 16) |
496 ((modded.dx + modded.width) & 0x0fff));
498 PM3_WRITE_REG(par, PM3FBSourceReadBufferOffset,
499 PM3FBSourceReadBufferOffset_XOffset(o_x) |
500 PM3FBSourceReadBufferOffset_YOffset(o_y));
502 PM3_WRITE_REG(par, PM3RectanglePosition,
503 PM3RectanglePosition_XOffset(modded.dx - x_align) |
504 PM3RectanglePosition_YOffset(modded.dy));
506 PM3_WRITE_REG(par, PM3Render2D,
507 ((modded.sx > modded.dx) ? PM3Render2D_XPositive : 0) |
508 ((modded.sy > modded.dy) ? PM3Render2D_YPositive : 0) |
509 PM3Render2D_Operation_Normal |
510 PM3Render2D_SpanOperation |
511 PM3Render2D_FBSourceReadEnable |
512 PM3Render2D_Width(modded.width + x_align) |
513 PM3Render2D_Height(modded.height));
516 static void pm3fb_imageblit(struct fb_info *info, const struct fb_image *image)
518 struct pm3_par *par = info->par;
519 u32 height = image->height;
521 const u32 *src = (const u32 *)image->data;
523 if (info->state != FBINFO_STATE_RUNNING)
525 if (info->flags & FBINFO_HWACCEL_DISABLED) {
526 cfb_imageblit(info, image);
529 switch (info->fix.visual) {
530 case FB_VISUAL_PSEUDOCOLOR:
531 fgx = image->fg_color;
532 bgx = image->bg_color;
534 case FB_VISUAL_TRUECOLOR:
536 fgx = par->palette[image->fg_color];
537 bgx = par->palette[image->bg_color];
540 if (image->depth != 1)
541 return cfb_imageblit(info, image);
543 if (info->var.bits_per_pixel == 8) {
547 if (info->var.bits_per_pixel <= 16) {
554 PM3_WRITE_REG(par, PM3ForegroundColor, fgx);
555 PM3_WRITE_REG(par, PM3BackgroundColor, bgx);
557 /* ROP Ox3 is GXcopy */
558 PM3_WRITE_REG(par, PM3Config2D,
559 PM3Config2D_UserScissorEnable |
560 PM3Config2D_UseConstantSource |
561 PM3Config2D_ForegroundROPEnable |
562 PM3Config2D_ForegroundROP(0x3) |
563 PM3Config2D_OpaqueSpan |
564 PM3Config2D_FBWriteEnable);
565 PM3_WRITE_REG(par, PM3ScissorMinXY,
566 ((image->dy & 0x0fff) << 16) | (image->dx & 0x0fff));
567 PM3_WRITE_REG(par, PM3ScissorMaxXY,
568 (((image->dy + image->height) & 0x0fff) << 16) |
569 ((image->dx + image->width) & 0x0fff));
570 PM3_WRITE_REG(par, PM3RectanglePosition,
571 PM3RectanglePosition_XOffset(image->dx) |
572 PM3RectanglePosition_YOffset(image->dy));
573 PM3_WRITE_REG(par, PM3Render2D,
574 PM3Render2D_XPositive |
575 PM3Render2D_YPositive |
576 PM3Render2D_Operation_SyncOnBitMask |
577 PM3Render2D_SpanOperation |
578 PM3Render2D_Width(image->width) |
579 PM3Render2D_Height(image->height));
583 int width = ((image->width + 7) >> 3)
584 + info->pixmap.scan_align - 1;
587 while (width >= PM3_FIFO_SIZE) {
588 int i = PM3_FIFO_SIZE - 1;
590 PM3_WAIT(par, PM3_FIFO_SIZE);
592 PM3_WRITE_REG(par, PM3BitMaskPattern, *src);
595 width -= PM3_FIFO_SIZE - 1;
598 PM3_WAIT(par, width + 1);
600 PM3_WRITE_REG(par, PM3BitMaskPattern, *src);
605 /* end of acceleration functions */
607 /* write the mode to registers */
608 static void pm3fb_write_mode(struct fb_info *info)
610 struct pm3_par *par = info->par;
611 char tempsync = 0x00;
612 char tempmisc = 0x00;
613 const u32 hsstart = info->var.right_margin;
614 const u32 hsend = hsstart + info->var.hsync_len;
615 const u32 hbend = hsend + info->var.left_margin;
616 const u32 xres = (info->var.xres + 31) & ~31;
617 const u32 htotal = xres + hbend;
618 const u32 vsstart = info->var.lower_margin;
619 const u32 vsend = vsstart + info->var.vsync_len;
620 const u32 vbend = vsend + info->var.upper_margin;
621 const u32 vtotal = info->var.yres + vbend;
622 const u32 width = (info->var.xres_virtual + 7) & ~7;
623 const unsigned bpp = info->var.bits_per_pixel;
626 PM3_WRITE_REG(par, PM3MemBypassWriteMask, 0xffffffff);
627 PM3_WRITE_REG(par, PM3Aperture0, 0x00000000);
628 PM3_WRITE_REG(par, PM3Aperture1, 0x00000000);
629 PM3_WRITE_REG(par, PM3FIFODis, 0x00000007);
631 PM3_WRITE_REG(par, PM3HTotal,
632 pm3fb_shift_bpp(bpp, htotal - 1));
633 PM3_WRITE_REG(par, PM3HsEnd,
634 pm3fb_shift_bpp(bpp, hsend));
635 PM3_WRITE_REG(par, PM3HsStart,
636 pm3fb_shift_bpp(bpp, hsstart));
637 PM3_WRITE_REG(par, PM3HbEnd,
638 pm3fb_shift_bpp(bpp, hbend));
639 PM3_WRITE_REG(par, PM3HgEnd,
640 pm3fb_shift_bpp(bpp, hbend));
641 PM3_WRITE_REG(par, PM3ScreenStride,
642 pm3fb_shift_bpp(bpp, width));
643 PM3_WRITE_REG(par, PM3VTotal, vtotal - 1);
644 PM3_WRITE_REG(par, PM3VsEnd, vsend - 1);
645 PM3_WRITE_REG(par, PM3VsStart, vsstart - 1);
646 PM3_WRITE_REG(par, PM3VbEnd, vbend);
650 PM3_WRITE_REG(par, PM3ByAperture1Mode,
651 PM3ByApertureMode_PIXELSIZE_8BIT);
652 PM3_WRITE_REG(par, PM3ByAperture2Mode,
653 PM3ByApertureMode_PIXELSIZE_8BIT);
658 PM3_WRITE_REG(par, PM3ByAperture1Mode,
659 PM3ByApertureMode_PIXELSIZE_16BIT);
660 PM3_WRITE_REG(par, PM3ByAperture2Mode,
661 PM3ByApertureMode_PIXELSIZE_16BIT);
663 PM3_WRITE_REG(par, PM3ByAperture1Mode,
664 PM3ByApertureMode_PIXELSIZE_16BIT |
665 PM3ByApertureMode_BYTESWAP_BADC);
666 PM3_WRITE_REG(par, PM3ByAperture2Mode,
667 PM3ByApertureMode_PIXELSIZE_16BIT |
668 PM3ByApertureMode_BYTESWAP_BADC);
669 #endif /* ! __BIG_ENDIAN */
674 PM3_WRITE_REG(par, PM3ByAperture1Mode,
675 PM3ByApertureMode_PIXELSIZE_32BIT);
676 PM3_WRITE_REG(par, PM3ByAperture2Mode,
677 PM3ByApertureMode_PIXELSIZE_32BIT);
679 PM3_WRITE_REG(par, PM3ByAperture1Mode,
680 PM3ByApertureMode_PIXELSIZE_32BIT |
681 PM3ByApertureMode_BYTESWAP_DCBA);
682 PM3_WRITE_REG(par, PM3ByAperture2Mode,
683 PM3ByApertureMode_PIXELSIZE_32BIT |
684 PM3ByApertureMode_BYTESWAP_DCBA);
685 #endif /* ! __BIG_ENDIAN */
689 DPRINTK("Unsupported depth %d\n", bpp);
694 * Oxygen VX1 - it appears that setting PM3VideoControl and
695 * then PM3RD_SyncControl to the same SYNC settings undoes
696 * any net change - they seem to xor together. Only set the
697 * sync options in PM3RD_SyncControl. --rmk
700 unsigned int video = par->video;
702 video &= ~(PM3VideoControl_HSYNC_MASK |
703 PM3VideoControl_VSYNC_MASK);
704 video |= PM3VideoControl_HSYNC_ACTIVE_HIGH |
705 PM3VideoControl_VSYNC_ACTIVE_HIGH;
706 PM3_WRITE_REG(par, PM3VideoControl, video);
708 PM3_WRITE_REG(par, PM3VClkCtl,
709 (PM3_READ_REG(par, PM3VClkCtl) & 0xFFFFFFFC));
710 PM3_WRITE_REG(par, PM3ScreenBase, par->base);
711 PM3_WRITE_REG(par, PM3ChipConfig,
712 (PM3_READ_REG(par, PM3ChipConfig) & 0xFFFFFFFD));
716 unsigned char uninitialized_var(m); /* ClkPreScale */
717 unsigned char uninitialized_var(n); /* ClkFeedBackScale */
718 unsigned char uninitialized_var(p); /* ClkPostScale */
719 unsigned long pixclock = PICOS2KHZ(info->var.pixclock);
721 (void)pm3fb_calculate_clock(pixclock, &m, &n, &p);
723 DPRINTK("Pixclock: %ld, Pre: %d, Feedback: %d, Post: %d\n",
724 pixclock, (int) m, (int) n, (int) p);
726 PM3_WRITE_DAC_REG(par, PM3RD_DClk0PreScale, m);
727 PM3_WRITE_DAC_REG(par, PM3RD_DClk0FeedbackScale, n);
728 PM3_WRITE_DAC_REG(par, PM3RD_DClk0PostScale, p);
731 PM3_WRITE_DAC_REG(par, PM3RD_IndexControl, 0x00);
734 PM3_SLOW_WRITE_REG(par, PM3RD_IndexControl, 0x00);
736 if ((par->video & PM3VideoControl_HSYNC_MASK) ==
737 PM3VideoControl_HSYNC_ACTIVE_HIGH)
738 tempsync |= PM3RD_SyncControl_HSYNC_ACTIVE_HIGH;
739 if ((par->video & PM3VideoControl_VSYNC_MASK) ==
740 PM3VideoControl_VSYNC_ACTIVE_HIGH)
741 tempsync |= PM3RD_SyncControl_VSYNC_ACTIVE_HIGH;
743 PM3_WRITE_DAC_REG(par, PM3RD_SyncControl, tempsync);
744 DPRINTK("PM3RD_SyncControl: %d\n", tempsync);
746 PM3_WRITE_DAC_REG(par, PM3RD_DACControl, 0x00);
748 switch (pm3fb_depth(&info->var)) {
750 PM3_WRITE_DAC_REG(par, PM3RD_PixelSize,
751 PM3RD_PixelSize_8_BIT_PIXELS);
752 PM3_WRITE_DAC_REG(par, PM3RD_ColorFormat,
753 PM3RD_ColorFormat_CI8_COLOR |
754 PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW);
755 tempmisc |= PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE;
758 PM3_WRITE_DAC_REG(par, PM3RD_PixelSize,
759 PM3RD_PixelSize_16_BIT_PIXELS);
760 PM3_WRITE_DAC_REG(par, PM3RD_ColorFormat,
761 PM3RD_ColorFormat_4444_COLOR |
762 PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW |
763 PM3RD_ColorFormat_LINEAR_COLOR_EXT_ENABLE);
764 tempmisc |= PM3RD_MiscControl_DIRECTCOLOR_ENABLE |
765 PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE;
768 PM3_WRITE_DAC_REG(par, PM3RD_PixelSize,
769 PM3RD_PixelSize_16_BIT_PIXELS);
770 PM3_WRITE_DAC_REG(par, PM3RD_ColorFormat,
771 PM3RD_ColorFormat_5551_FRONT_COLOR |
772 PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW |
773 PM3RD_ColorFormat_LINEAR_COLOR_EXT_ENABLE);
774 tempmisc |= PM3RD_MiscControl_DIRECTCOLOR_ENABLE |
775 PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE;
778 PM3_WRITE_DAC_REG(par, PM3RD_PixelSize,
779 PM3RD_PixelSize_16_BIT_PIXELS);
780 PM3_WRITE_DAC_REG(par, PM3RD_ColorFormat,
781 PM3RD_ColorFormat_565_FRONT_COLOR |
782 PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW |
783 PM3RD_ColorFormat_LINEAR_COLOR_EXT_ENABLE);
784 tempmisc |= PM3RD_MiscControl_DIRECTCOLOR_ENABLE |
785 PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE;
788 PM3_WRITE_DAC_REG(par, PM3RD_PixelSize,
789 PM3RD_PixelSize_32_BIT_PIXELS);
790 PM3_WRITE_DAC_REG(par, PM3RD_ColorFormat,
791 PM3RD_ColorFormat_8888_COLOR |
792 PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW);
793 tempmisc |= PM3RD_MiscControl_DIRECTCOLOR_ENABLE |
794 PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE;
797 PM3_WRITE_DAC_REG(par, PM3RD_MiscControl, tempmisc);
801 * hardware independent functions
803 static int pm3fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
806 unsigned bpp = var->red.length + var->green.length
807 + var->blue.length + var->transp.length;
809 if (bpp != var->bits_per_pixel) {
810 /* set predefined mode for bits_per_pixel settings */
812 switch (var->bits_per_pixel) {
815 var->green.length = 8;
816 var->blue.length = 8;
818 var->green.offset = 0;
819 var->blue.offset = 0;
820 var->transp.offset = 0;
821 var->transp.length = 0;
825 var->blue.length = 5;
826 var->green.length = 6;
827 var->transp.length = 0;
831 var->green.length = 8;
832 var->blue.length = 8;
833 var->transp.length = 8;
836 DPRINTK("depth not supported: %u\n",
837 var->bits_per_pixel);
841 /* it is assumed BGRA order */
842 if (var->bits_per_pixel > 8 ) {
843 var->blue.offset = 0;
844 var->green.offset = var->blue.length;
845 var->red.offset = var->green.offset + var->green.length;
846 var->transp.offset = var->red.offset + var->red.length;
851 if (var->xres != var->xres_virtual) {
852 DPRINTK("virtual x resolution != "
853 "physical x resolution not supported\n");
857 if (var->yres > var->yres_virtual) {
858 DPRINTK("virtual y resolution < "
859 "physical y resolution not possible\n");
864 DPRINTK("xoffset not supported\n");
868 if ((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
869 DPRINTK("interlace not supported\n");
873 var->xres = (var->xres + 31) & ~31; /* could sometimes be 8 */
874 lpitch = var->xres * ((var->bits_per_pixel + 7) >> 3);
876 if (var->xres < 200 || var->xres > 2048) {
877 DPRINTK("width not supported: %u\n", var->xres);
881 if (var->yres < 200 || var->yres > 4095) {
882 DPRINTK("height not supported: %u\n", var->yres);
886 if (lpitch * var->yres_virtual > info->fix.smem_len) {
887 DPRINTK("no memory for screen (%ux%ux%u)\n",
888 var->xres, var->yres_virtual, var->bits_per_pixel);
892 if (PICOS2KHZ(var->pixclock) > PM3_MAX_PIXCLOCK) {
893 DPRINTK("pixclock too high (%ldKHz)\n",
894 PICOS2KHZ(var->pixclock));
898 var->accel_flags = 0; /* Can't mmap if this is on */
900 DPRINTK("Checking graphics mode at %dx%d depth %d\n",
901 var->xres, var->yres, var->bits_per_pixel);
905 static int pm3fb_set_par(struct fb_info *info)
907 struct pm3_par *par = info->par;
908 const u32 xres = (info->var.xres + 31) & ~31;
909 const unsigned bpp = info->var.bits_per_pixel;
911 par->base = pm3fb_shift_bpp(bpp, (info->var.yoffset * xres)
912 + info->var.xoffset);
915 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
916 par->video |= PM3VideoControl_HSYNC_ACTIVE_HIGH;
918 par->video |= PM3VideoControl_HSYNC_ACTIVE_LOW;
920 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
921 par->video |= PM3VideoControl_VSYNC_ACTIVE_HIGH;
923 par->video |= PM3VideoControl_VSYNC_ACTIVE_LOW;
925 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_DOUBLE)
926 par->video |= PM3VideoControl_LINE_DOUBLE_ON;
928 if ((info->var.activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW)
929 par->video |= PM3VideoControl_ENABLE;
931 DPRINTK("PM3Video disabled\n");
935 par->video |= PM3VideoControl_PIXELSIZE_8BIT;
938 par->video |= PM3VideoControl_PIXELSIZE_16BIT;
941 par->video |= PM3VideoControl_PIXELSIZE_32BIT;
944 DPRINTK("Unsupported depth\n");
949 (bpp == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
950 info->fix.line_length = ((info->var.xres_virtual + 7) >> 3) * bpp;
952 /* pm3fb_clear_memory(info, 0);*/
953 pm3fb_clear_colormap(par, 0, 0, 0);
954 PM3_WRITE_DAC_REG(par, PM3RD_CursorMode, 0);
955 pm3fb_init_engine(info);
956 pm3fb_write_mode(info);
960 static int pm3fb_setcolreg(unsigned regno, unsigned red, unsigned green,
961 unsigned blue, unsigned transp,
962 struct fb_info *info)
964 struct pm3_par *par = info->par;
966 if (regno >= 256) /* no. of hw registers */
969 /* grayscale works only partially under directcolor */
970 /* grayscale = 0.30*R + 0.59*G + 0.11*B */
971 if (info->var.grayscale)
972 red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
975 * var->{color}.offset contains start of bitfield
976 * var->{color}.length contains length of bitfield
977 * {hardwarespecific} contains width of DAC
978 * pseudo_palette[X] is programmed to (X << red.offset) |
979 * (X << green.offset) |
981 * RAMDAC[X] is programmed to (red, green, blue)
982 * color depth = SUM(var->{color}.length)
985 * var->{color}.offset is 0
986 * var->{color}.length contains width of DAC or the number
987 * of unique colors available (color depth)
988 * pseudo_palette is not used
989 * RAMDAC[X] is programmed to (red, green, blue)
990 * color depth = var->{color}.length
994 * This is the point where the color is converted to something that
995 * is acceptable by the hardware.
997 #define CNVT_TOHW(val, width) ((((val) << (width)) + 0x7FFF - (val)) >> 16)
998 red = CNVT_TOHW(red, info->var.red.length);
999 green = CNVT_TOHW(green, info->var.green.length);
1000 blue = CNVT_TOHW(blue, info->var.blue.length);
1001 transp = CNVT_TOHW(transp, info->var.transp.length);
1004 if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
1005 info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
1011 v = (red << info->var.red.offset) |
1012 (green << info->var.green.offset) |
1013 (blue << info->var.blue.offset) |
1014 (transp << info->var.transp.offset);
1016 switch (info->var.bits_per_pixel) {
1021 ((u32 *)(info->pseudo_palette))[regno] = v;
1025 } else if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR)
1026 pm3fb_set_color(par, regno, red, green, blue);
1031 static int pm3fb_pan_display(struct fb_var_screeninfo *var,
1032 struct fb_info *info)
1034 struct pm3_par *par = info->par;
1035 const u32 xres = (var->xres + 31) & ~31;
1037 par->base = pm3fb_shift_bpp(var->bits_per_pixel,
1038 (var->yoffset * xres)
1041 PM3_WRITE_REG(par, PM3ScreenBase, par->base);
1045 static int pm3fb_blank(int blank_mode, struct fb_info *info)
1047 struct pm3_par *par = info->par;
1048 u32 video = par->video;
1051 * Oxygen VX1 - it appears that setting PM3VideoControl and
1052 * then PM3RD_SyncControl to the same SYNC settings undoes
1053 * any net change - they seem to xor together. Only set the
1054 * sync options in PM3RD_SyncControl. --rmk
1056 video &= ~(PM3VideoControl_HSYNC_MASK |
1057 PM3VideoControl_VSYNC_MASK);
1058 video |= PM3VideoControl_HSYNC_ACTIVE_HIGH |
1059 PM3VideoControl_VSYNC_ACTIVE_HIGH;
1061 switch (blank_mode) {
1062 case FB_BLANK_UNBLANK:
1063 video |= PM3VideoControl_ENABLE;
1065 case FB_BLANK_NORMAL:
1066 video &= ~PM3VideoControl_ENABLE;
1068 case FB_BLANK_HSYNC_SUSPEND:
1069 video &= ~(PM3VideoControl_HSYNC_MASK |
1070 PM3VideoControl_BLANK_ACTIVE_LOW);
1072 case FB_BLANK_VSYNC_SUSPEND:
1073 video &= ~(PM3VideoControl_VSYNC_MASK |
1074 PM3VideoControl_BLANK_ACTIVE_LOW);
1076 case FB_BLANK_POWERDOWN:
1077 video &= ~(PM3VideoControl_HSYNC_MASK |
1078 PM3VideoControl_VSYNC_MASK |
1079 PM3VideoControl_BLANK_ACTIVE_LOW);
1082 DPRINTK("Unsupported blanking %d\n", blank_mode);
1087 PM3_WRITE_REG(par, PM3VideoControl, video);
1092 * Frame buffer operations
1095 static struct fb_ops pm3fb_ops = {
1096 .owner = THIS_MODULE,
1097 .fb_check_var = pm3fb_check_var,
1098 .fb_set_par = pm3fb_set_par,
1099 .fb_setcolreg = pm3fb_setcolreg,
1100 .fb_pan_display = pm3fb_pan_display,
1101 .fb_fillrect = pm3fb_fillrect,
1102 .fb_copyarea = pm3fb_copyarea,
1103 .fb_imageblit = pm3fb_imageblit,
1104 .fb_blank = pm3fb_blank,
1105 .fb_sync = pm3fb_sync,
1108 /* ------------------------------------------------------------------------- */
1114 /* mmio register are already mapped when this function is called */
1115 /* the pm3fb_fix.smem_start is also set */
1116 static unsigned long pm3fb_size_memory(struct pm3_par *par)
1118 unsigned long memsize = 0;
1119 unsigned long tempBypass, i, temp1, temp2;
1120 unsigned char __iomem *screen_mem;
1122 pm3fb_fix.smem_len = 64 * 1024l * 1024; /* request full aperture size */
1123 /* Linear frame buffer - request region and map it. */
1124 if (!request_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len,
1126 printk(KERN_WARNING "pm3fb: Can't reserve smem.\n");
1130 ioremap_nocache(pm3fb_fix.smem_start, pm3fb_fix.smem_len);
1132 printk(KERN_WARNING "pm3fb: Can't ioremap smem area.\n");
1133 release_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len);
1137 /* TODO: card-specific stuff, *before* accessing *any* FB memory */
1138 /* For Appian Jeronimo 2000 board second head */
1140 tempBypass = PM3_READ_REG(par, PM3MemBypassWriteMask);
1142 DPRINTK("PM3MemBypassWriteMask was: 0x%08lx\n", tempBypass);
1145 PM3_WRITE_REG(par, PM3MemBypassWriteMask, 0xFFFFFFFF);
1147 /* pm3 split up memory, replicates, and do a lot of
1148 * nasty stuff IMHO ;-)
1150 for (i = 0; i < 32; i++) {
1151 fb_writel(i * 0x00345678,
1152 (screen_mem + (i * 1048576)));
1154 temp1 = fb_readl((screen_mem + (i * 1048576)));
1156 /* Let's check for wrapover, write will fail at 16MB boundary */
1157 if (temp1 == (i * 0x00345678))
1163 DPRINTK("First detect pass already got %ld MB\n", memsize + 1);
1165 if (memsize + 1 == i) {
1166 for (i = 0; i < 32; i++) {
1167 /* Clear first 32MB ; 0 is 0, no need to byteswap */
1168 writel(0x0000000, (screen_mem + (i * 1048576)));
1172 for (i = 32; i < 64; i++) {
1173 fb_writel(i * 0x00345678,
1174 (screen_mem + (i * 1048576)));
1177 fb_readl((screen_mem + (i * 1048576)));
1179 fb_readl((screen_mem + ((i - 32) * 1048576)));
1180 /* different value, different RAM... */
1181 if ((temp1 == (i * 0x00345678)) && (temp2 == 0))
1187 DPRINTK("Second detect pass got %ld MB\n", memsize + 1);
1190 PM3_WRITE_REG(par, PM3MemBypassWriteMask, tempBypass);
1192 iounmap(screen_mem);
1193 release_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len);
1194 memsize = 1048576 * (memsize + 1);
1196 DPRINTK("Returning 0x%08lx bytes\n", memsize);
1201 static int __devinit pm3fb_probe(struct pci_dev *dev,
1202 const struct pci_device_id *ent)
1204 struct fb_info *info;
1205 struct pm3_par *par;
1206 struct device *device = &dev->dev; /* for pci drivers */
1208 int retval = -ENXIO;
1210 err = pci_enable_device(dev);
1212 printk(KERN_WARNING "pm3fb: Can't enable PCI dev: %d\n", err);
1216 * Dynamically allocate info and par
1218 info = framebuffer_alloc(sizeof(struct pm3_par), device);
1225 * Here we set the screen_base to the virtual memory address
1226 * for the framebuffer.
1228 pm3fb_fix.mmio_start = pci_resource_start(dev, 0);
1229 pm3fb_fix.mmio_len = PM3_REGS_SIZE;
1230 #if defined(__BIG_ENDIAN)
1231 pm3fb_fix.mmio_start += PM3_REGS_SIZE;
1232 DPRINTK("Adjusting register base for big-endian.\n");
1235 /* Registers - request region and map it. */
1236 if (!request_mem_region(pm3fb_fix.mmio_start, pm3fb_fix.mmio_len,
1238 printk(KERN_WARNING "pm3fb: Can't reserve regbase.\n");
1239 goto err_exit_neither;
1242 ioremap_nocache(pm3fb_fix.mmio_start, pm3fb_fix.mmio_len);
1244 printk(KERN_WARNING "pm3fb: Can't remap %s register area.\n",
1246 release_mem_region(pm3fb_fix.mmio_start, pm3fb_fix.mmio_len);
1247 goto err_exit_neither;
1250 /* Linear frame buffer - request region and map it. */
1251 pm3fb_fix.smem_start = pci_resource_start(dev, 1);
1252 pm3fb_fix.smem_len = pm3fb_size_memory(par);
1253 if (!pm3fb_fix.smem_len) {
1254 printk(KERN_WARNING "pm3fb: Can't find memory on board.\n");
1257 if (!request_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len,
1259 printk(KERN_WARNING "pm3fb: Can't reserve smem.\n");
1263 ioremap_nocache(pm3fb_fix.smem_start, pm3fb_fix.smem_len);
1264 if (!info->screen_base) {
1265 printk(KERN_WARNING "pm3fb: Can't ioremap smem area.\n");
1266 release_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len);
1269 info->screen_size = pm3fb_fix.smem_len;
1273 par->mtrr_handle = mtrr_add(pm3fb_fix.smem_start,
1275 MTRR_TYPE_WRCOMB, 1);
1277 info->fbops = &pm3fb_ops;
1279 par->video = PM3_READ_REG(par, PM3VideoControl);
1281 info->fix = pm3fb_fix;
1282 info->pseudo_palette = par->palette;
1283 info->flags = FBINFO_DEFAULT |
1284 FBINFO_HWACCEL_XPAN |
1285 FBINFO_HWACCEL_YPAN |
1286 FBINFO_HWACCEL_COPYAREA |
1287 FBINFO_HWACCEL_IMAGEBLIT |
1288 FBINFO_HWACCEL_FILLRECT;
1291 printk(KERN_DEBUG "disabling acceleration\n");
1292 info->flags |= FBINFO_HWACCEL_DISABLED;
1294 info->pixmap.addr = kmalloc(PM3_PIXMAP_SIZE, GFP_KERNEL);
1295 if (!info->pixmap.addr) {
1297 goto err_exit_pixmap;
1299 info->pixmap.size = PM3_PIXMAP_SIZE;
1300 info->pixmap.buf_align = 4;
1301 info->pixmap.scan_align = 4;
1302 info->pixmap.access_align = 32;
1303 info->pixmap.flags = FB_PIXMAP_SYSTEM;
1306 * This should give a reasonable default video mode. The following is
1307 * done when we can set a video mode.
1310 mode_option = "640x480@60";
1312 retval = fb_find_mode(&info->var, info, mode_option, NULL, 0, NULL, 8);
1314 if (!retval || retval == 4) {
1319 if (fb_alloc_cmap(&info->cmap, 256, 0) < 0) {
1325 * For drivers that can...
1327 pm3fb_check_var(&info->var, info);
1329 if (register_framebuffer(info) < 0) {
1333 printk(KERN_INFO "fb%d: %s frame buffer device\n", info->node,
1335 pci_set_drvdata(dev, info);
1339 fb_dealloc_cmap(&info->cmap);
1341 kfree(info->pixmap.addr);
1343 iounmap(info->screen_base);
1344 release_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len);
1346 iounmap(par->v_regs);
1347 release_mem_region(pm3fb_fix.mmio_start, pm3fb_fix.mmio_len);
1349 framebuffer_release(info);
1356 static void __devexit pm3fb_remove(struct pci_dev *dev)
1358 struct fb_info *info = pci_get_drvdata(dev);
1361 struct fb_fix_screeninfo *fix = &info->fix;
1362 struct pm3_par *par = info->par;
1364 unregister_framebuffer(info);
1365 fb_dealloc_cmap(&info->cmap);
1368 if (par->mtrr_handle >= 0)
1369 mtrr_del(par->mtrr_handle, info->fix.smem_start,
1370 info->fix.smem_len);
1371 #endif /* CONFIG_MTRR */
1372 iounmap(info->screen_base);
1373 release_mem_region(fix->smem_start, fix->smem_len);
1374 iounmap(par->v_regs);
1375 release_mem_region(fix->mmio_start, fix->mmio_len);
1377 pci_set_drvdata(dev, NULL);
1378 kfree(info->pixmap.addr);
1379 framebuffer_release(info);
1383 static struct pci_device_id pm3fb_id_table[] = {
1384 { PCI_VENDOR_ID_3DLABS, 0x0a,
1385 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
1389 /* For PCI drivers */
1390 static struct pci_driver pm3fb_driver = {
1392 .id_table = pm3fb_id_table,
1393 .probe = pm3fb_probe,
1394 .remove = __devexit_p(pm3fb_remove),
1397 MODULE_DEVICE_TABLE(pci, pm3fb_id_table);
1405 * Only necessary if your driver takes special options,
1406 * otherwise we fall back on the generic fb_setup().
1408 static int __init pm3fb_setup(char *options)
1412 /* Parse user speficied options (`video=pm3fb:') */
1413 if (!options || !*options)
1416 while ((this_opt = strsep(&options, ",")) != NULL) {
1419 else if (!strncmp(this_opt, "noaccel", 7))
1422 else if (!strncmp(this_opt, "nomtrr", 6))
1426 mode_option = this_opt;
1432 static int __init pm3fb_init(void)
1435 * For kernel boot options (in 'video=pm3fb:<options>' format)
1438 char *option = NULL;
1440 if (fb_get_options("pm3fb", &option))
1442 pm3fb_setup(option);
1445 return pci_register_driver(&pm3fb_driver);
1449 static void __exit pm3fb_exit(void)
1451 pci_unregister_driver(&pm3fb_driver);
1454 module_exit(pm3fb_exit);
1456 module_init(pm3fb_init);
1458 module_param(noaccel, bool, 0);
1459 MODULE_PARM_DESC(noaccel, "Disable acceleration");
1461 module_param(nomtrr, bool, 0);
1462 MODULE_PARM_DESC(nomtrr, "Disable MTRR support (0 or 1=disabled) (default=0)");
1465 MODULE_DESCRIPTION("Permedia3 framebuffer device driver");
1466 MODULE_LICENSE("GPL");