2 * linux/drivers/video/omap2/dss/rfbi.c
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 * Some code and ideas taken from drivers/video/omap/ driver
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
23 #define DSS_SUBSYS_NAME "RFBI"
25 #include <linux/kernel.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/vmalloc.h>
28 #include <linux/clk.h>
30 #include <linux/delay.h>
31 #include <linux/kfifo.h>
32 #include <linux/ktime.h>
33 #include <linux/hrtimer.h>
34 #include <linux/seq_file.h>
36 #include <plat/display.h>
39 struct rfbi_reg { u16 idx; };
41 #define RFBI_REG(idx) ((const struct rfbi_reg) { idx })
43 #define RFBI_REVISION RFBI_REG(0x0000)
44 #define RFBI_SYSCONFIG RFBI_REG(0x0010)
45 #define RFBI_SYSSTATUS RFBI_REG(0x0014)
46 #define RFBI_CONTROL RFBI_REG(0x0040)
47 #define RFBI_PIXEL_CNT RFBI_REG(0x0044)
48 #define RFBI_LINE_NUMBER RFBI_REG(0x0048)
49 #define RFBI_CMD RFBI_REG(0x004c)
50 #define RFBI_PARAM RFBI_REG(0x0050)
51 #define RFBI_DATA RFBI_REG(0x0054)
52 #define RFBI_READ RFBI_REG(0x0058)
53 #define RFBI_STATUS RFBI_REG(0x005c)
55 #define RFBI_CONFIG(n) RFBI_REG(0x0060 + (n)*0x18)
56 #define RFBI_ONOFF_TIME(n) RFBI_REG(0x0064 + (n)*0x18)
57 #define RFBI_CYCLE_TIME(n) RFBI_REG(0x0068 + (n)*0x18)
58 #define RFBI_DATA_CYCLE1(n) RFBI_REG(0x006c + (n)*0x18)
59 #define RFBI_DATA_CYCLE2(n) RFBI_REG(0x0070 + (n)*0x18)
60 #define RFBI_DATA_CYCLE3(n) RFBI_REG(0x0074 + (n)*0x18)
62 #define RFBI_VSYNC_WIDTH RFBI_REG(0x0090)
63 #define RFBI_HSYNC_WIDTH RFBI_REG(0x0094)
65 #define REG_FLD_MOD(idx, val, start, end) \
66 rfbi_write_reg(idx, FLD_MOD(rfbi_read_reg(idx), val, start, end))
68 /* To work around an RFBI transfer rate limitation */
69 #define OMAP_RFBI_RATE_LIMIT 1
71 enum omap_rfbi_cycleformat {
72 OMAP_DSS_RFBI_CYCLEFORMAT_1_1 = 0,
73 OMAP_DSS_RFBI_CYCLEFORMAT_2_1 = 1,
74 OMAP_DSS_RFBI_CYCLEFORMAT_3_1 = 2,
75 OMAP_DSS_RFBI_CYCLEFORMAT_3_2 = 3,
78 enum omap_rfbi_datatype {
79 OMAP_DSS_RFBI_DATATYPE_12 = 0,
80 OMAP_DSS_RFBI_DATATYPE_16 = 1,
81 OMAP_DSS_RFBI_DATATYPE_18 = 2,
82 OMAP_DSS_RFBI_DATATYPE_24 = 3,
85 enum omap_rfbi_parallelmode {
86 OMAP_DSS_RFBI_PARALLELMODE_8 = 0,
87 OMAP_DSS_RFBI_PARALLELMODE_9 = 1,
88 OMAP_DSS_RFBI_PARALLELMODE_12 = 2,
89 OMAP_DSS_RFBI_PARALLELMODE_16 = 3,
97 static int rfbi_convert_timings(struct rfbi_timings *t);
98 static void rfbi_get_clk_info(u32 *clk_period, u32 *max_clk_div);
101 struct platform_device *pdev;
104 unsigned long l4_khz;
106 enum omap_rfbi_datatype datatype;
107 enum omap_rfbi_parallelmode parallelmode;
109 enum omap_rfbi_te_mode te_mode;
112 void (*framedone_callback)(void *data);
113 void *framedone_callback_data;
115 struct omap_dss_device *dssdev[2];
117 struct kfifo cmd_fifo;
119 struct completion cmd_done;
120 atomic_t cmd_fifo_full;
121 atomic_t cmd_pending;
124 struct update_region {
131 static inline void rfbi_write_reg(const struct rfbi_reg idx, u32 val)
133 __raw_writel(val, rfbi.base + idx.idx);
136 static inline u32 rfbi_read_reg(const struct rfbi_reg idx)
138 return __raw_readl(rfbi.base + idx.idx);
141 static void rfbi_enable_clocks(bool enable)
144 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
146 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
149 void omap_rfbi_write_command(const void *buf, u32 len)
151 rfbi_enable_clocks(1);
152 switch (rfbi.parallelmode) {
153 case OMAP_DSS_RFBI_PARALLELMODE_8:
157 rfbi_write_reg(RFBI_CMD, *b++);
161 case OMAP_DSS_RFBI_PARALLELMODE_16:
165 for (; len; len -= 2)
166 rfbi_write_reg(RFBI_CMD, *w++);
170 case OMAP_DSS_RFBI_PARALLELMODE_9:
171 case OMAP_DSS_RFBI_PARALLELMODE_12:
175 rfbi_enable_clocks(0);
177 EXPORT_SYMBOL(omap_rfbi_write_command);
179 void omap_rfbi_read_data(void *buf, u32 len)
181 rfbi_enable_clocks(1);
182 switch (rfbi.parallelmode) {
183 case OMAP_DSS_RFBI_PARALLELMODE_8:
187 rfbi_write_reg(RFBI_READ, 0);
188 *b++ = rfbi_read_reg(RFBI_READ);
193 case OMAP_DSS_RFBI_PARALLELMODE_16:
197 for (; len; len -= 2) {
198 rfbi_write_reg(RFBI_READ, 0);
199 *w++ = rfbi_read_reg(RFBI_READ);
204 case OMAP_DSS_RFBI_PARALLELMODE_9:
205 case OMAP_DSS_RFBI_PARALLELMODE_12:
209 rfbi_enable_clocks(0);
211 EXPORT_SYMBOL(omap_rfbi_read_data);
213 void omap_rfbi_write_data(const void *buf, u32 len)
215 rfbi_enable_clocks(1);
216 switch (rfbi.parallelmode) {
217 case OMAP_DSS_RFBI_PARALLELMODE_8:
221 rfbi_write_reg(RFBI_PARAM, *b++);
225 case OMAP_DSS_RFBI_PARALLELMODE_16:
229 for (; len; len -= 2)
230 rfbi_write_reg(RFBI_PARAM, *w++);
234 case OMAP_DSS_RFBI_PARALLELMODE_9:
235 case OMAP_DSS_RFBI_PARALLELMODE_12:
240 rfbi_enable_clocks(0);
242 EXPORT_SYMBOL(omap_rfbi_write_data);
244 void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width,
248 int start_offset = scr_width * y + x;
249 int horiz_offset = scr_width - w;
252 rfbi_enable_clocks(1);
254 if (rfbi.datatype == OMAP_DSS_RFBI_DATATYPE_16 &&
255 rfbi.parallelmode == OMAP_DSS_RFBI_PARALLELMODE_8) {
256 const u16 __iomem *pd = buf;
260 for (i = 0; i < w; ++i) {
261 const u8 __iomem *b = (const u8 __iomem *)pd;
262 rfbi_write_reg(RFBI_PARAM, __raw_readb(b+1));
263 rfbi_write_reg(RFBI_PARAM, __raw_readb(b+0));
268 } else if (rfbi.datatype == OMAP_DSS_RFBI_DATATYPE_24 &&
269 rfbi.parallelmode == OMAP_DSS_RFBI_PARALLELMODE_8) {
270 const u32 __iomem *pd = buf;
274 for (i = 0; i < w; ++i) {
275 const u8 __iomem *b = (const u8 __iomem *)pd;
276 rfbi_write_reg(RFBI_PARAM, __raw_readb(b+2));
277 rfbi_write_reg(RFBI_PARAM, __raw_readb(b+1));
278 rfbi_write_reg(RFBI_PARAM, __raw_readb(b+0));
283 } else if (rfbi.datatype == OMAP_DSS_RFBI_DATATYPE_16 &&
284 rfbi.parallelmode == OMAP_DSS_RFBI_PARALLELMODE_16) {
285 const u16 __iomem *pd = buf;
289 for (i = 0; i < w; ++i) {
290 rfbi_write_reg(RFBI_PARAM, __raw_readw(pd));
299 rfbi_enable_clocks(0);
301 EXPORT_SYMBOL(omap_rfbi_write_pixels);
303 void rfbi_transfer_area(struct omap_dss_device *dssdev, u16 width,
304 u16 height, void (*callback)(void *data), void *data)
308 /*BUG_ON(callback == 0);*/
309 BUG_ON(rfbi.framedone_callback != NULL);
311 DSSDBG("rfbi_transfer_area %dx%d\n", width, height);
313 dispc_set_lcd_size(dssdev->manager->id, width, height);
315 dispc_enable_channel(dssdev->manager->id, true);
317 rfbi.framedone_callback = callback;
318 rfbi.framedone_callback_data = data;
320 rfbi_enable_clocks(1);
322 rfbi_write_reg(RFBI_PIXEL_CNT, width * height);
324 l = rfbi_read_reg(RFBI_CONTROL);
325 l = FLD_MOD(l, 1, 0, 0); /* enable */
326 if (!rfbi.te_enabled)
327 l = FLD_MOD(l, 1, 4, 4); /* ITE */
329 rfbi_write_reg(RFBI_CONTROL, l);
332 static void framedone_callback(void *data, u32 mask)
334 void (*callback)(void *data);
336 DSSDBG("FRAMEDONE\n");
338 REG_FLD_MOD(RFBI_CONTROL, 0, 0, 0);
340 rfbi_enable_clocks(0);
342 callback = rfbi.framedone_callback;
343 rfbi.framedone_callback = NULL;
345 if (callback != NULL)
346 callback(rfbi.framedone_callback_data);
348 atomic_set(&rfbi.cmd_pending, 0);
352 static void rfbi_print_timings(void)
357 l = rfbi_read_reg(RFBI_CONFIG(0));
358 time = 1000000000 / rfbi.l4_khz;
362 DSSDBG("Tick time %u ps\n", time);
363 l = rfbi_read_reg(RFBI_ONOFF_TIME(0));
364 DSSDBG("CSONTIME %d, CSOFFTIME %d, WEONTIME %d, WEOFFTIME %d, "
365 "REONTIME %d, REOFFTIME %d\n",
366 l & 0x0f, (l >> 4) & 0x3f, (l >> 10) & 0x0f, (l >> 14) & 0x3f,
367 (l >> 20) & 0x0f, (l >> 24) & 0x3f);
369 l = rfbi_read_reg(RFBI_CYCLE_TIME(0));
370 DSSDBG("WECYCLETIME %d, RECYCLETIME %d, CSPULSEWIDTH %d, "
372 (l & 0x3f), (l >> 6) & 0x3f, (l >> 12) & 0x3f,
376 static void rfbi_print_timings(void) {}
382 static u32 extif_clk_period;
384 static inline unsigned long round_to_extif_ticks(unsigned long ps, int div)
386 int bus_tick = extif_clk_period * div;
387 return (ps + bus_tick - 1) / bus_tick * bus_tick;
390 static int calc_reg_timing(struct rfbi_timings *t, int div)
394 t->cs_on_time = round_to_extif_ticks(t->cs_on_time, div);
396 t->we_on_time = round_to_extif_ticks(t->we_on_time, div);
397 t->we_off_time = round_to_extif_ticks(t->we_off_time, div);
398 t->we_cycle_time = round_to_extif_ticks(t->we_cycle_time, div);
400 t->re_on_time = round_to_extif_ticks(t->re_on_time, div);
401 t->re_off_time = round_to_extif_ticks(t->re_off_time, div);
402 t->re_cycle_time = round_to_extif_ticks(t->re_cycle_time, div);
404 t->access_time = round_to_extif_ticks(t->access_time, div);
405 t->cs_off_time = round_to_extif_ticks(t->cs_off_time, div);
406 t->cs_pulse_width = round_to_extif_ticks(t->cs_pulse_width, div);
408 DSSDBG("[reg]cson %d csoff %d reon %d reoff %d\n",
409 t->cs_on_time, t->cs_off_time, t->re_on_time, t->re_off_time);
410 DSSDBG("[reg]weon %d weoff %d recyc %d wecyc %d\n",
411 t->we_on_time, t->we_off_time, t->re_cycle_time,
413 DSSDBG("[reg]rdaccess %d cspulse %d\n",
414 t->access_time, t->cs_pulse_width);
416 return rfbi_convert_timings(t);
419 static int calc_extif_timings(struct rfbi_timings *t)
424 rfbi_get_clk_info(&extif_clk_period, &max_clk_div);
425 for (div = 1; div <= max_clk_div; div++) {
426 if (calc_reg_timing(t, div) == 0)
430 if (div <= max_clk_div)
433 DSSERR("can't setup timings\n");
438 void rfbi_set_timings(int rfbi_module, struct rfbi_timings *t)
443 r = calc_extif_timings(t);
445 DSSERR("Failed to calc timings\n");
448 BUG_ON(!t->converted);
450 rfbi_enable_clocks(1);
451 rfbi_write_reg(RFBI_ONOFF_TIME(rfbi_module), t->tim[0]);
452 rfbi_write_reg(RFBI_CYCLE_TIME(rfbi_module), t->tim[1]);
454 /* TIMEGRANULARITY */
455 REG_FLD_MOD(RFBI_CONFIG(rfbi_module),
456 (t->tim[2] ? 1 : 0), 4, 4);
458 rfbi_print_timings();
459 rfbi_enable_clocks(0);
462 static int ps_to_rfbi_ticks(int time, int div)
464 unsigned long tick_ps;
467 /* Calculate in picosecs to yield more exact results */
468 tick_ps = 1000000000 / (rfbi.l4_khz) * div;
470 ret = (time + tick_ps - 1) / tick_ps;
475 #ifdef OMAP_RFBI_RATE_LIMIT
476 unsigned long rfbi_get_max_tx_rate(void)
478 unsigned long l4_rate, dss1_rate;
479 int min_l4_ticks = 0;
482 /* According to TI this can't be calculated so make the
483 * adjustments for a couple of known frequencies and warn for
486 static const struct {
487 unsigned long l4_clk; /* HZ */
488 unsigned long dss1_clk; /* HZ */
489 unsigned long min_l4_ticks;
491 { 55, 132, 7, }, /* 7.86 MPix/s */
492 { 110, 110, 12, }, /* 9.16 MPix/s */
493 { 110, 132, 10, }, /* 11 Mpix/s */
494 { 120, 120, 10, }, /* 12 Mpix/s */
495 { 133, 133, 10, }, /* 13.3 Mpix/s */
498 l4_rate = rfbi.l4_khz / 1000;
499 dss1_rate = dss_clk_get_rate(DSS_CLK_FCK) / 1000000;
501 for (i = 0; i < ARRAY_SIZE(ftab); i++) {
502 /* Use a window instead of an exact match, to account
503 * for different DPLL multiplier / divider pairs.
505 if (abs(ftab[i].l4_clk - l4_rate) < 3 &&
506 abs(ftab[i].dss1_clk - dss1_rate) < 3) {
507 min_l4_ticks = ftab[i].min_l4_ticks;
511 if (i == ARRAY_SIZE(ftab)) {
512 /* Can't be sure, return anyway the maximum not
513 * rate-limited. This might cause a problem only for the
514 * tearing synchronisation.
516 DSSERR("can't determine maximum RFBI transfer rate\n");
517 return rfbi.l4_khz * 1000;
519 return rfbi.l4_khz * 1000 / min_l4_ticks;
522 int rfbi_get_max_tx_rate(void)
524 return rfbi.l4_khz * 1000;
528 static void rfbi_get_clk_info(u32 *clk_period, u32 *max_clk_div)
530 *clk_period = 1000000000 / rfbi.l4_khz;
534 static int rfbi_convert_timings(struct rfbi_timings *t)
537 int reon, reoff, weon, weoff, cson, csoff, cs_pulse;
538 int actim, recyc, wecyc;
539 int div = t->clk_div;
541 if (div <= 0 || div > 2)
544 /* Make sure that after conversion it still holds that:
545 * weoff > weon, reoff > reon, recyc >= reoff, wecyc >= weoff,
546 * csoff > cson, csoff >= max(weoff, reoff), actim > reon
548 weon = ps_to_rfbi_ticks(t->we_on_time, div);
549 weoff = ps_to_rfbi_ticks(t->we_off_time, div);
557 reon = ps_to_rfbi_ticks(t->re_on_time, div);
558 reoff = ps_to_rfbi_ticks(t->re_off_time, div);
566 cson = ps_to_rfbi_ticks(t->cs_on_time, div);
567 csoff = ps_to_rfbi_ticks(t->cs_off_time, div);
570 if (csoff < max(weoff, reoff))
571 csoff = max(weoff, reoff);
586 actim = ps_to_rfbi_ticks(t->access_time, div);
592 wecyc = ps_to_rfbi_ticks(t->we_cycle_time, div);
598 recyc = ps_to_rfbi_ticks(t->re_cycle_time, div);
604 cs_pulse = ps_to_rfbi_ticks(t->cs_pulse_width, div);
622 /* xxx FIX module selection missing */
623 int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode,
624 unsigned hs_pulse_time, unsigned vs_pulse_time,
625 int hs_pol_inv, int vs_pol_inv, int extif_div)
631 hs = ps_to_rfbi_ticks(hs_pulse_time, 1);
632 vs = ps_to_rfbi_ticks(vs_pulse_time, 1);
635 if (mode == OMAP_DSS_RFBI_TE_MODE_2)
637 else /* OMAP_DSS_RFBI_TE_MODE_1 */
644 DSSDBG("setup_te: mode %d hs %d vs %d hs_inv %d vs_inv %d\n",
645 mode, hs, vs, hs_pol_inv, vs_pol_inv);
647 rfbi_enable_clocks(1);
648 rfbi_write_reg(RFBI_HSYNC_WIDTH, hs);
649 rfbi_write_reg(RFBI_VSYNC_WIDTH, vs);
651 l = rfbi_read_reg(RFBI_CONFIG(0));
660 rfbi_enable_clocks(0);
664 EXPORT_SYMBOL(omap_rfbi_setup_te);
666 /* xxx FIX module selection missing */
667 int omap_rfbi_enable_te(bool enable, unsigned line)
671 DSSDBG("te %d line %d mode %d\n", enable, line, rfbi.te_mode);
672 if (line > (1 << 11) - 1)
675 rfbi_enable_clocks(1);
676 l = rfbi_read_reg(RFBI_CONFIG(0));
680 l |= rfbi.te_mode << 2;
683 rfbi_write_reg(RFBI_CONFIG(0), l);
684 rfbi_write_reg(RFBI_LINE_NUMBER, line);
685 rfbi_enable_clocks(0);
689 EXPORT_SYMBOL(omap_rfbi_enable_te);
692 static void rfbi_enable_config(int enable1, int enable2)
702 rfbi_enable_clocks(1);
704 l = rfbi_read_reg(RFBI_CONTROL);
706 l = FLD_MOD(l, cs, 3, 2);
707 l = FLD_MOD(l, 0, 1, 1);
709 rfbi_write_reg(RFBI_CONTROL, l);
712 l = rfbi_read_reg(RFBI_CONFIG(0));
713 l = FLD_MOD(l, 0, 3, 2); /* TRIGGERMODE: ITE */
714 /*l |= FLD_VAL(2, 8, 7); */ /* L4FORMAT, 2pix/L4 */
715 /*l |= FLD_VAL(0, 8, 7); */ /* L4FORMAT, 1pix/L4 */
717 l = FLD_MOD(l, 0, 16, 16); /* A0POLARITY */
718 l = FLD_MOD(l, 1, 20, 20); /* TE_VSYNC_POLARITY */
719 l = FLD_MOD(l, 1, 21, 21); /* HSYNCPOLARITY */
721 l = FLD_MOD(l, OMAP_DSS_RFBI_PARALLELMODE_8, 1, 0);
722 rfbi_write_reg(RFBI_CONFIG(0), l);
724 rfbi_enable_clocks(0);
728 int rfbi_configure(int rfbi_module, int bpp, int lines)
731 int cycle1 = 0, cycle2 = 0, cycle3 = 0;
732 enum omap_rfbi_cycleformat cycleformat;
733 enum omap_rfbi_datatype datatype;
734 enum omap_rfbi_parallelmode parallelmode;
738 datatype = OMAP_DSS_RFBI_DATATYPE_12;
741 datatype = OMAP_DSS_RFBI_DATATYPE_16;
744 datatype = OMAP_DSS_RFBI_DATATYPE_18;
747 datatype = OMAP_DSS_RFBI_DATATYPE_24;
753 rfbi.datatype = datatype;
757 parallelmode = OMAP_DSS_RFBI_PARALLELMODE_8;
760 parallelmode = OMAP_DSS_RFBI_PARALLELMODE_9;
763 parallelmode = OMAP_DSS_RFBI_PARALLELMODE_12;
766 parallelmode = OMAP_DSS_RFBI_PARALLELMODE_16;
772 rfbi.parallelmode = parallelmode;
774 if ((bpp % lines) == 0) {
775 switch (bpp / lines) {
777 cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_1_1;
780 cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_2_1;
783 cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_3_1;
789 } else if ((2 * bpp % lines) == 0) {
790 if ((2 * bpp / lines) == 3)
791 cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_3_2;
801 switch (cycleformat) {
802 case OMAP_DSS_RFBI_CYCLEFORMAT_1_1:
806 case OMAP_DSS_RFBI_CYCLEFORMAT_2_1:
811 case OMAP_DSS_RFBI_CYCLEFORMAT_3_1:
817 case OMAP_DSS_RFBI_CYCLEFORMAT_3_2:
819 cycle2 = (lines / 2) | ((lines / 2) << 16);
820 cycle3 = (lines << 16);
824 rfbi_enable_clocks(1);
826 REG_FLD_MOD(RFBI_CONTROL, 0, 3, 2); /* clear CS */
829 l |= FLD_VAL(parallelmode, 1, 0);
830 l |= FLD_VAL(0, 3, 2); /* TRIGGERMODE: ITE */
831 l |= FLD_VAL(0, 4, 4); /* TIMEGRANULARITY */
832 l |= FLD_VAL(datatype, 6, 5);
833 /* l |= FLD_VAL(2, 8, 7); */ /* L4FORMAT, 2pix/L4 */
834 l |= FLD_VAL(0, 8, 7); /* L4FORMAT, 1pix/L4 */
835 l |= FLD_VAL(cycleformat, 10, 9);
836 l |= FLD_VAL(0, 12, 11); /* UNUSEDBITS */
837 l |= FLD_VAL(0, 16, 16); /* A0POLARITY */
838 l |= FLD_VAL(0, 17, 17); /* REPOLARITY */
839 l |= FLD_VAL(0, 18, 18); /* WEPOLARITY */
840 l |= FLD_VAL(0, 19, 19); /* CSPOLARITY */
841 l |= FLD_VAL(1, 20, 20); /* TE_VSYNC_POLARITY */
842 l |= FLD_VAL(1, 21, 21); /* HSYNCPOLARITY */
843 rfbi_write_reg(RFBI_CONFIG(rfbi_module), l);
845 rfbi_write_reg(RFBI_DATA_CYCLE1(rfbi_module), cycle1);
846 rfbi_write_reg(RFBI_DATA_CYCLE2(rfbi_module), cycle2);
847 rfbi_write_reg(RFBI_DATA_CYCLE3(rfbi_module), cycle3);
850 l = rfbi_read_reg(RFBI_CONTROL);
851 l = FLD_MOD(l, rfbi_module+1, 3, 2); /* Select CSx */
852 l = FLD_MOD(l, 0, 1, 1); /* clear bypass */
853 rfbi_write_reg(RFBI_CONTROL, l);
856 DSSDBG("RFBI config: bpp %d, lines %d, cycles: 0x%x 0x%x 0x%x\n",
857 bpp, lines, cycle1, cycle2, cycle3);
859 rfbi_enable_clocks(0);
863 EXPORT_SYMBOL(rfbi_configure);
865 int omap_rfbi_prepare_update(struct omap_dss_device *dssdev,
866 u16 *x, u16 *y, u16 *w, u16 *h)
870 dssdev->driver->get_resolution(dssdev, &dw, &dh);
872 if (*x > dw || *y > dh)
884 if (*w == 0 || *h == 0)
887 if (dssdev->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
888 dss_setup_partial_planes(dssdev, x, y, w, h, true);
889 dispc_set_lcd_size(dssdev->manager->id, *w, *h);
894 EXPORT_SYMBOL(omap_rfbi_prepare_update);
896 int omap_rfbi_update(struct omap_dss_device *dssdev,
897 u16 x, u16 y, u16 w, u16 h,
898 void (*callback)(void *), void *data)
900 if (dssdev->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
901 rfbi_transfer_area(dssdev, w, h, callback, data);
903 struct omap_overlay *ovl;
907 ovl = dssdev->manager->overlays[0];
908 scr_width = ovl->info.screen_width;
909 addr = ovl->info.vaddr;
911 omap_rfbi_write_pixels(addr, scr_width, x, y, w, h);
918 EXPORT_SYMBOL(omap_rfbi_update);
920 void rfbi_dump_regs(struct seq_file *s)
922 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, rfbi_read_reg(r))
924 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
926 DUMPREG(RFBI_REVISION);
927 DUMPREG(RFBI_SYSCONFIG);
928 DUMPREG(RFBI_SYSSTATUS);
929 DUMPREG(RFBI_CONTROL);
930 DUMPREG(RFBI_PIXEL_CNT);
931 DUMPREG(RFBI_LINE_NUMBER);
936 DUMPREG(RFBI_STATUS);
938 DUMPREG(RFBI_CONFIG(0));
939 DUMPREG(RFBI_ONOFF_TIME(0));
940 DUMPREG(RFBI_CYCLE_TIME(0));
941 DUMPREG(RFBI_DATA_CYCLE1(0));
942 DUMPREG(RFBI_DATA_CYCLE2(0));
943 DUMPREG(RFBI_DATA_CYCLE3(0));
945 DUMPREG(RFBI_CONFIG(1));
946 DUMPREG(RFBI_ONOFF_TIME(1));
947 DUMPREG(RFBI_CYCLE_TIME(1));
948 DUMPREG(RFBI_DATA_CYCLE1(1));
949 DUMPREG(RFBI_DATA_CYCLE2(1));
950 DUMPREG(RFBI_DATA_CYCLE3(1));
952 DUMPREG(RFBI_VSYNC_WIDTH);
953 DUMPREG(RFBI_HSYNC_WIDTH);
955 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
959 int omapdss_rfbi_display_enable(struct omap_dss_device *dssdev)
963 r = omap_dss_start_device(dssdev);
965 DSSERR("failed to start device\n");
969 r = omap_dispc_register_isr(framedone_callback, NULL,
970 DISPC_IRQ_FRAMEDONE);
972 DSSERR("can't get FRAMEDONE irq\n");
976 dispc_set_lcd_display_type(dssdev->manager->id,
977 OMAP_DSS_LCD_DISPLAY_TFT);
979 dispc_set_parallel_interface_mode(dssdev->manager->id,
980 OMAP_DSS_PARALLELMODE_RFBI);
982 dispc_set_tft_data_lines(dssdev->manager->id, dssdev->ctrl.pixel_size);
984 rfbi_configure(dssdev->phy.rfbi.channel,
985 dssdev->ctrl.pixel_size,
986 dssdev->phy.rfbi.data_lines);
988 rfbi_set_timings(dssdev->phy.rfbi.channel,
989 &dssdev->ctrl.rfbi_timings);
994 omap_dss_stop_device(dssdev);
998 EXPORT_SYMBOL(omapdss_rfbi_display_enable);
1000 void omapdss_rfbi_display_disable(struct omap_dss_device *dssdev)
1002 omap_dispc_unregister_isr(framedone_callback, NULL,
1003 DISPC_IRQ_FRAMEDONE);
1004 omap_dss_stop_device(dssdev);
1006 EXPORT_SYMBOL(omapdss_rfbi_display_disable);
1008 int rfbi_init_display(struct omap_dss_device *dssdev)
1010 rfbi.dssdev[dssdev->phy.rfbi.channel] = dssdev;
1011 dssdev->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE;
1015 /* RFBI HW IP initialisation */
1016 static int omap_rfbihw_probe(struct platform_device *pdev)
1020 struct resource *rfbi_mem;
1024 spin_lock_init(&rfbi.cmd_lock);
1026 init_completion(&rfbi.cmd_done);
1027 atomic_set(&rfbi.cmd_fifo_full, 0);
1028 atomic_set(&rfbi.cmd_pending, 0);
1030 rfbi_mem = platform_get_resource(rfbi.pdev, IORESOURCE_MEM, 0);
1032 DSSERR("can't get IORESOURCE_MEM RFBI\n");
1035 rfbi.base = ioremap(rfbi_mem->start, resource_size(rfbi_mem));
1037 DSSERR("can't ioremap RFBI\n");
1041 rfbi_enable_clocks(1);
1045 rfbi.l4_khz = dss_clk_get_rate(DSS_CLK_ICK) / 1000;
1047 /* Enable autoidle and smart-idle */
1048 l = rfbi_read_reg(RFBI_SYSCONFIG);
1049 l |= (1 << 0) | (2 << 3);
1050 rfbi_write_reg(RFBI_SYSCONFIG, l);
1052 rev = rfbi_read_reg(RFBI_REVISION);
1053 dev_dbg(&pdev->dev, "OMAP RFBI rev %d.%d\n",
1054 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
1056 rfbi_enable_clocks(0);
1061 static int omap_rfbihw_remove(struct platform_device *pdev)
1067 static struct platform_driver omap_rfbihw_driver = {
1068 .probe = omap_rfbihw_probe,
1069 .remove = omap_rfbihw_remove,
1071 .name = "omapdss_rfbi",
1072 .owner = THIS_MODULE,
1076 int rfbi_init_platform_driver(void)
1078 return platform_driver_register(&omap_rfbihw_driver);
1081 void rfbi_uninit_platform_driver(void)
1083 return platform_driver_unregister(&omap_rfbihw_driver);