2 * linux/drivers/video/omap2/dss/rfbi.c
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 * Some code and ideas taken from drivers/video/omap/ driver
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
23 #define DSS_SUBSYS_NAME "RFBI"
25 #include <linux/kernel.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/vmalloc.h>
28 #include <linux/clk.h>
30 #include <linux/delay.h>
31 #include <linux/kfifo.h>
32 #include <linux/ktime.h>
33 #include <linux/hrtimer.h>
34 #include <linux/seq_file.h>
36 #include <plat/display.h>
39 #define RFBI_BASE 0x48050800
41 struct rfbi_reg { u16 idx; };
43 #define RFBI_REG(idx) ((const struct rfbi_reg) { idx })
45 #define RFBI_REVISION RFBI_REG(0x0000)
46 #define RFBI_SYSCONFIG RFBI_REG(0x0010)
47 #define RFBI_SYSSTATUS RFBI_REG(0x0014)
48 #define RFBI_CONTROL RFBI_REG(0x0040)
49 #define RFBI_PIXEL_CNT RFBI_REG(0x0044)
50 #define RFBI_LINE_NUMBER RFBI_REG(0x0048)
51 #define RFBI_CMD RFBI_REG(0x004c)
52 #define RFBI_PARAM RFBI_REG(0x0050)
53 #define RFBI_DATA RFBI_REG(0x0054)
54 #define RFBI_READ RFBI_REG(0x0058)
55 #define RFBI_STATUS RFBI_REG(0x005c)
57 #define RFBI_CONFIG(n) RFBI_REG(0x0060 + (n)*0x18)
58 #define RFBI_ONOFF_TIME(n) RFBI_REG(0x0064 + (n)*0x18)
59 #define RFBI_CYCLE_TIME(n) RFBI_REG(0x0068 + (n)*0x18)
60 #define RFBI_DATA_CYCLE1(n) RFBI_REG(0x006c + (n)*0x18)
61 #define RFBI_DATA_CYCLE2(n) RFBI_REG(0x0070 + (n)*0x18)
62 #define RFBI_DATA_CYCLE3(n) RFBI_REG(0x0074 + (n)*0x18)
64 #define RFBI_VSYNC_WIDTH RFBI_REG(0x0090)
65 #define RFBI_HSYNC_WIDTH RFBI_REG(0x0094)
67 #define REG_FLD_MOD(idx, val, start, end) \
68 rfbi_write_reg(idx, FLD_MOD(rfbi_read_reg(idx), val, start, end))
70 /* To work around an RFBI transfer rate limitation */
71 #define OMAP_RFBI_RATE_LIMIT 1
73 enum omap_rfbi_cycleformat {
74 OMAP_DSS_RFBI_CYCLEFORMAT_1_1 = 0,
75 OMAP_DSS_RFBI_CYCLEFORMAT_2_1 = 1,
76 OMAP_DSS_RFBI_CYCLEFORMAT_3_1 = 2,
77 OMAP_DSS_RFBI_CYCLEFORMAT_3_2 = 3,
80 enum omap_rfbi_datatype {
81 OMAP_DSS_RFBI_DATATYPE_12 = 0,
82 OMAP_DSS_RFBI_DATATYPE_16 = 1,
83 OMAP_DSS_RFBI_DATATYPE_18 = 2,
84 OMAP_DSS_RFBI_DATATYPE_24 = 3,
87 enum omap_rfbi_parallelmode {
88 OMAP_DSS_RFBI_PARALLELMODE_8 = 0,
89 OMAP_DSS_RFBI_PARALLELMODE_9 = 1,
90 OMAP_DSS_RFBI_PARALLELMODE_12 = 2,
91 OMAP_DSS_RFBI_PARALLELMODE_16 = 3,
99 static int rfbi_convert_timings(struct rfbi_timings *t);
100 static void rfbi_get_clk_info(u32 *clk_period, u32 *max_clk_div);
103 struct platform_device *pdev;
106 unsigned long l4_khz;
108 enum omap_rfbi_datatype datatype;
109 enum omap_rfbi_parallelmode parallelmode;
111 enum omap_rfbi_te_mode te_mode;
114 void (*framedone_callback)(void *data);
115 void *framedone_callback_data;
117 struct omap_dss_device *dssdev[2];
119 struct kfifo cmd_fifo;
121 struct completion cmd_done;
122 atomic_t cmd_fifo_full;
123 atomic_t cmd_pending;
126 struct update_region {
133 static inline void rfbi_write_reg(const struct rfbi_reg idx, u32 val)
135 __raw_writel(val, rfbi.base + idx.idx);
138 static inline u32 rfbi_read_reg(const struct rfbi_reg idx)
140 return __raw_readl(rfbi.base + idx.idx);
143 static void rfbi_enable_clocks(bool enable)
146 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
148 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
151 void omap_rfbi_write_command(const void *buf, u32 len)
153 rfbi_enable_clocks(1);
154 switch (rfbi.parallelmode) {
155 case OMAP_DSS_RFBI_PARALLELMODE_8:
159 rfbi_write_reg(RFBI_CMD, *b++);
163 case OMAP_DSS_RFBI_PARALLELMODE_16:
167 for (; len; len -= 2)
168 rfbi_write_reg(RFBI_CMD, *w++);
172 case OMAP_DSS_RFBI_PARALLELMODE_9:
173 case OMAP_DSS_RFBI_PARALLELMODE_12:
177 rfbi_enable_clocks(0);
179 EXPORT_SYMBOL(omap_rfbi_write_command);
181 void omap_rfbi_read_data(void *buf, u32 len)
183 rfbi_enable_clocks(1);
184 switch (rfbi.parallelmode) {
185 case OMAP_DSS_RFBI_PARALLELMODE_8:
189 rfbi_write_reg(RFBI_READ, 0);
190 *b++ = rfbi_read_reg(RFBI_READ);
195 case OMAP_DSS_RFBI_PARALLELMODE_16:
199 for (; len; len -= 2) {
200 rfbi_write_reg(RFBI_READ, 0);
201 *w++ = rfbi_read_reg(RFBI_READ);
206 case OMAP_DSS_RFBI_PARALLELMODE_9:
207 case OMAP_DSS_RFBI_PARALLELMODE_12:
211 rfbi_enable_clocks(0);
213 EXPORT_SYMBOL(omap_rfbi_read_data);
215 void omap_rfbi_write_data(const void *buf, u32 len)
217 rfbi_enable_clocks(1);
218 switch (rfbi.parallelmode) {
219 case OMAP_DSS_RFBI_PARALLELMODE_8:
223 rfbi_write_reg(RFBI_PARAM, *b++);
227 case OMAP_DSS_RFBI_PARALLELMODE_16:
231 for (; len; len -= 2)
232 rfbi_write_reg(RFBI_PARAM, *w++);
236 case OMAP_DSS_RFBI_PARALLELMODE_9:
237 case OMAP_DSS_RFBI_PARALLELMODE_12:
242 rfbi_enable_clocks(0);
244 EXPORT_SYMBOL(omap_rfbi_write_data);
246 void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width,
250 int start_offset = scr_width * y + x;
251 int horiz_offset = scr_width - w;
254 rfbi_enable_clocks(1);
256 if (rfbi.datatype == OMAP_DSS_RFBI_DATATYPE_16 &&
257 rfbi.parallelmode == OMAP_DSS_RFBI_PARALLELMODE_8) {
258 const u16 __iomem *pd = buf;
262 for (i = 0; i < w; ++i) {
263 const u8 __iomem *b = (const u8 __iomem *)pd;
264 rfbi_write_reg(RFBI_PARAM, __raw_readb(b+1));
265 rfbi_write_reg(RFBI_PARAM, __raw_readb(b+0));
270 } else if (rfbi.datatype == OMAP_DSS_RFBI_DATATYPE_24 &&
271 rfbi.parallelmode == OMAP_DSS_RFBI_PARALLELMODE_8) {
272 const u32 __iomem *pd = buf;
276 for (i = 0; i < w; ++i) {
277 const u8 __iomem *b = (const u8 __iomem *)pd;
278 rfbi_write_reg(RFBI_PARAM, __raw_readb(b+2));
279 rfbi_write_reg(RFBI_PARAM, __raw_readb(b+1));
280 rfbi_write_reg(RFBI_PARAM, __raw_readb(b+0));
285 } else if (rfbi.datatype == OMAP_DSS_RFBI_DATATYPE_16 &&
286 rfbi.parallelmode == OMAP_DSS_RFBI_PARALLELMODE_16) {
287 const u16 __iomem *pd = buf;
291 for (i = 0; i < w; ++i) {
292 rfbi_write_reg(RFBI_PARAM, __raw_readw(pd));
301 rfbi_enable_clocks(0);
303 EXPORT_SYMBOL(omap_rfbi_write_pixels);
305 void rfbi_transfer_area(struct omap_dss_device *dssdev, u16 width,
306 u16 height, void (*callback)(void *data), void *data)
310 /*BUG_ON(callback == 0);*/
311 BUG_ON(rfbi.framedone_callback != NULL);
313 DSSDBG("rfbi_transfer_area %dx%d\n", width, height);
315 dispc_set_lcd_size(dssdev->manager->id, width, height);
317 dispc_enable_channel(dssdev->manager->id, true);
319 rfbi.framedone_callback = callback;
320 rfbi.framedone_callback_data = data;
322 rfbi_enable_clocks(1);
324 rfbi_write_reg(RFBI_PIXEL_CNT, width * height);
326 l = rfbi_read_reg(RFBI_CONTROL);
327 l = FLD_MOD(l, 1, 0, 0); /* enable */
328 if (!rfbi.te_enabled)
329 l = FLD_MOD(l, 1, 4, 4); /* ITE */
331 rfbi_write_reg(RFBI_CONTROL, l);
334 static void framedone_callback(void *data, u32 mask)
336 void (*callback)(void *data);
338 DSSDBG("FRAMEDONE\n");
340 REG_FLD_MOD(RFBI_CONTROL, 0, 0, 0);
342 rfbi_enable_clocks(0);
344 callback = rfbi.framedone_callback;
345 rfbi.framedone_callback = NULL;
347 if (callback != NULL)
348 callback(rfbi.framedone_callback_data);
350 atomic_set(&rfbi.cmd_pending, 0);
354 static void rfbi_print_timings(void)
359 l = rfbi_read_reg(RFBI_CONFIG(0));
360 time = 1000000000 / rfbi.l4_khz;
364 DSSDBG("Tick time %u ps\n", time);
365 l = rfbi_read_reg(RFBI_ONOFF_TIME(0));
366 DSSDBG("CSONTIME %d, CSOFFTIME %d, WEONTIME %d, WEOFFTIME %d, "
367 "REONTIME %d, REOFFTIME %d\n",
368 l & 0x0f, (l >> 4) & 0x3f, (l >> 10) & 0x0f, (l >> 14) & 0x3f,
369 (l >> 20) & 0x0f, (l >> 24) & 0x3f);
371 l = rfbi_read_reg(RFBI_CYCLE_TIME(0));
372 DSSDBG("WECYCLETIME %d, RECYCLETIME %d, CSPULSEWIDTH %d, "
374 (l & 0x3f), (l >> 6) & 0x3f, (l >> 12) & 0x3f,
378 static void rfbi_print_timings(void) {}
384 static u32 extif_clk_period;
386 static inline unsigned long round_to_extif_ticks(unsigned long ps, int div)
388 int bus_tick = extif_clk_period * div;
389 return (ps + bus_tick - 1) / bus_tick * bus_tick;
392 static int calc_reg_timing(struct rfbi_timings *t, int div)
396 t->cs_on_time = round_to_extif_ticks(t->cs_on_time, div);
398 t->we_on_time = round_to_extif_ticks(t->we_on_time, div);
399 t->we_off_time = round_to_extif_ticks(t->we_off_time, div);
400 t->we_cycle_time = round_to_extif_ticks(t->we_cycle_time, div);
402 t->re_on_time = round_to_extif_ticks(t->re_on_time, div);
403 t->re_off_time = round_to_extif_ticks(t->re_off_time, div);
404 t->re_cycle_time = round_to_extif_ticks(t->re_cycle_time, div);
406 t->access_time = round_to_extif_ticks(t->access_time, div);
407 t->cs_off_time = round_to_extif_ticks(t->cs_off_time, div);
408 t->cs_pulse_width = round_to_extif_ticks(t->cs_pulse_width, div);
410 DSSDBG("[reg]cson %d csoff %d reon %d reoff %d\n",
411 t->cs_on_time, t->cs_off_time, t->re_on_time, t->re_off_time);
412 DSSDBG("[reg]weon %d weoff %d recyc %d wecyc %d\n",
413 t->we_on_time, t->we_off_time, t->re_cycle_time,
415 DSSDBG("[reg]rdaccess %d cspulse %d\n",
416 t->access_time, t->cs_pulse_width);
418 return rfbi_convert_timings(t);
421 static int calc_extif_timings(struct rfbi_timings *t)
426 rfbi_get_clk_info(&extif_clk_period, &max_clk_div);
427 for (div = 1; div <= max_clk_div; div++) {
428 if (calc_reg_timing(t, div) == 0)
432 if (div <= max_clk_div)
435 DSSERR("can't setup timings\n");
440 void rfbi_set_timings(int rfbi_module, struct rfbi_timings *t)
445 r = calc_extif_timings(t);
447 DSSERR("Failed to calc timings\n");
450 BUG_ON(!t->converted);
452 rfbi_enable_clocks(1);
453 rfbi_write_reg(RFBI_ONOFF_TIME(rfbi_module), t->tim[0]);
454 rfbi_write_reg(RFBI_CYCLE_TIME(rfbi_module), t->tim[1]);
456 /* TIMEGRANULARITY */
457 REG_FLD_MOD(RFBI_CONFIG(rfbi_module),
458 (t->tim[2] ? 1 : 0), 4, 4);
460 rfbi_print_timings();
461 rfbi_enable_clocks(0);
464 static int ps_to_rfbi_ticks(int time, int div)
466 unsigned long tick_ps;
469 /* Calculate in picosecs to yield more exact results */
470 tick_ps = 1000000000 / (rfbi.l4_khz) * div;
472 ret = (time + tick_ps - 1) / tick_ps;
477 #ifdef OMAP_RFBI_RATE_LIMIT
478 unsigned long rfbi_get_max_tx_rate(void)
480 unsigned long l4_rate, dss1_rate;
481 int min_l4_ticks = 0;
484 /* According to TI this can't be calculated so make the
485 * adjustments for a couple of known frequencies and warn for
488 static const struct {
489 unsigned long l4_clk; /* HZ */
490 unsigned long dss1_clk; /* HZ */
491 unsigned long min_l4_ticks;
493 { 55, 132, 7, }, /* 7.86 MPix/s */
494 { 110, 110, 12, }, /* 9.16 MPix/s */
495 { 110, 132, 10, }, /* 11 Mpix/s */
496 { 120, 120, 10, }, /* 12 Mpix/s */
497 { 133, 133, 10, }, /* 13.3 Mpix/s */
500 l4_rate = rfbi.l4_khz / 1000;
501 dss1_rate = dss_clk_get_rate(DSS_CLK_FCK1) / 1000000;
503 for (i = 0; i < ARRAY_SIZE(ftab); i++) {
504 /* Use a window instead of an exact match, to account
505 * for different DPLL multiplier / divider pairs.
507 if (abs(ftab[i].l4_clk - l4_rate) < 3 &&
508 abs(ftab[i].dss1_clk - dss1_rate) < 3) {
509 min_l4_ticks = ftab[i].min_l4_ticks;
513 if (i == ARRAY_SIZE(ftab)) {
514 /* Can't be sure, return anyway the maximum not
515 * rate-limited. This might cause a problem only for the
516 * tearing synchronisation.
518 DSSERR("can't determine maximum RFBI transfer rate\n");
519 return rfbi.l4_khz * 1000;
521 return rfbi.l4_khz * 1000 / min_l4_ticks;
524 int rfbi_get_max_tx_rate(void)
526 return rfbi.l4_khz * 1000;
530 static void rfbi_get_clk_info(u32 *clk_period, u32 *max_clk_div)
532 *clk_period = 1000000000 / rfbi.l4_khz;
536 static int rfbi_convert_timings(struct rfbi_timings *t)
539 int reon, reoff, weon, weoff, cson, csoff, cs_pulse;
540 int actim, recyc, wecyc;
541 int div = t->clk_div;
543 if (div <= 0 || div > 2)
546 /* Make sure that after conversion it still holds that:
547 * weoff > weon, reoff > reon, recyc >= reoff, wecyc >= weoff,
548 * csoff > cson, csoff >= max(weoff, reoff), actim > reon
550 weon = ps_to_rfbi_ticks(t->we_on_time, div);
551 weoff = ps_to_rfbi_ticks(t->we_off_time, div);
559 reon = ps_to_rfbi_ticks(t->re_on_time, div);
560 reoff = ps_to_rfbi_ticks(t->re_off_time, div);
568 cson = ps_to_rfbi_ticks(t->cs_on_time, div);
569 csoff = ps_to_rfbi_ticks(t->cs_off_time, div);
572 if (csoff < max(weoff, reoff))
573 csoff = max(weoff, reoff);
588 actim = ps_to_rfbi_ticks(t->access_time, div);
594 wecyc = ps_to_rfbi_ticks(t->we_cycle_time, div);
600 recyc = ps_to_rfbi_ticks(t->re_cycle_time, div);
606 cs_pulse = ps_to_rfbi_ticks(t->cs_pulse_width, div);
624 /* xxx FIX module selection missing */
625 int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode,
626 unsigned hs_pulse_time, unsigned vs_pulse_time,
627 int hs_pol_inv, int vs_pol_inv, int extif_div)
633 hs = ps_to_rfbi_ticks(hs_pulse_time, 1);
634 vs = ps_to_rfbi_ticks(vs_pulse_time, 1);
637 if (mode == OMAP_DSS_RFBI_TE_MODE_2)
639 else /* OMAP_DSS_RFBI_TE_MODE_1 */
646 DSSDBG("setup_te: mode %d hs %d vs %d hs_inv %d vs_inv %d\n",
647 mode, hs, vs, hs_pol_inv, vs_pol_inv);
649 rfbi_enable_clocks(1);
650 rfbi_write_reg(RFBI_HSYNC_WIDTH, hs);
651 rfbi_write_reg(RFBI_VSYNC_WIDTH, vs);
653 l = rfbi_read_reg(RFBI_CONFIG(0));
662 rfbi_enable_clocks(0);
666 EXPORT_SYMBOL(omap_rfbi_setup_te);
668 /* xxx FIX module selection missing */
669 int omap_rfbi_enable_te(bool enable, unsigned line)
673 DSSDBG("te %d line %d mode %d\n", enable, line, rfbi.te_mode);
674 if (line > (1 << 11) - 1)
677 rfbi_enable_clocks(1);
678 l = rfbi_read_reg(RFBI_CONFIG(0));
682 l |= rfbi.te_mode << 2;
685 rfbi_write_reg(RFBI_CONFIG(0), l);
686 rfbi_write_reg(RFBI_LINE_NUMBER, line);
687 rfbi_enable_clocks(0);
691 EXPORT_SYMBOL(omap_rfbi_enable_te);
694 static void rfbi_enable_config(int enable1, int enable2)
704 rfbi_enable_clocks(1);
706 l = rfbi_read_reg(RFBI_CONTROL);
708 l = FLD_MOD(l, cs, 3, 2);
709 l = FLD_MOD(l, 0, 1, 1);
711 rfbi_write_reg(RFBI_CONTROL, l);
714 l = rfbi_read_reg(RFBI_CONFIG(0));
715 l = FLD_MOD(l, 0, 3, 2); /* TRIGGERMODE: ITE */
716 /*l |= FLD_VAL(2, 8, 7); */ /* L4FORMAT, 2pix/L4 */
717 /*l |= FLD_VAL(0, 8, 7); */ /* L4FORMAT, 1pix/L4 */
719 l = FLD_MOD(l, 0, 16, 16); /* A0POLARITY */
720 l = FLD_MOD(l, 1, 20, 20); /* TE_VSYNC_POLARITY */
721 l = FLD_MOD(l, 1, 21, 21); /* HSYNCPOLARITY */
723 l = FLD_MOD(l, OMAP_DSS_RFBI_PARALLELMODE_8, 1, 0);
724 rfbi_write_reg(RFBI_CONFIG(0), l);
726 rfbi_enable_clocks(0);
730 int rfbi_configure(int rfbi_module, int bpp, int lines)
733 int cycle1 = 0, cycle2 = 0, cycle3 = 0;
734 enum omap_rfbi_cycleformat cycleformat;
735 enum omap_rfbi_datatype datatype;
736 enum omap_rfbi_parallelmode parallelmode;
740 datatype = OMAP_DSS_RFBI_DATATYPE_12;
743 datatype = OMAP_DSS_RFBI_DATATYPE_16;
746 datatype = OMAP_DSS_RFBI_DATATYPE_18;
749 datatype = OMAP_DSS_RFBI_DATATYPE_24;
755 rfbi.datatype = datatype;
759 parallelmode = OMAP_DSS_RFBI_PARALLELMODE_8;
762 parallelmode = OMAP_DSS_RFBI_PARALLELMODE_9;
765 parallelmode = OMAP_DSS_RFBI_PARALLELMODE_12;
768 parallelmode = OMAP_DSS_RFBI_PARALLELMODE_16;
774 rfbi.parallelmode = parallelmode;
776 if ((bpp % lines) == 0) {
777 switch (bpp / lines) {
779 cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_1_1;
782 cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_2_1;
785 cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_3_1;
791 } else if ((2 * bpp % lines) == 0) {
792 if ((2 * bpp / lines) == 3)
793 cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_3_2;
803 switch (cycleformat) {
804 case OMAP_DSS_RFBI_CYCLEFORMAT_1_1:
808 case OMAP_DSS_RFBI_CYCLEFORMAT_2_1:
813 case OMAP_DSS_RFBI_CYCLEFORMAT_3_1:
819 case OMAP_DSS_RFBI_CYCLEFORMAT_3_2:
821 cycle2 = (lines / 2) | ((lines / 2) << 16);
822 cycle3 = (lines << 16);
826 rfbi_enable_clocks(1);
828 REG_FLD_MOD(RFBI_CONTROL, 0, 3, 2); /* clear CS */
831 l |= FLD_VAL(parallelmode, 1, 0);
832 l |= FLD_VAL(0, 3, 2); /* TRIGGERMODE: ITE */
833 l |= FLD_VAL(0, 4, 4); /* TIMEGRANULARITY */
834 l |= FLD_VAL(datatype, 6, 5);
835 /* l |= FLD_VAL(2, 8, 7); */ /* L4FORMAT, 2pix/L4 */
836 l |= FLD_VAL(0, 8, 7); /* L4FORMAT, 1pix/L4 */
837 l |= FLD_VAL(cycleformat, 10, 9);
838 l |= FLD_VAL(0, 12, 11); /* UNUSEDBITS */
839 l |= FLD_VAL(0, 16, 16); /* A0POLARITY */
840 l |= FLD_VAL(0, 17, 17); /* REPOLARITY */
841 l |= FLD_VAL(0, 18, 18); /* WEPOLARITY */
842 l |= FLD_VAL(0, 19, 19); /* CSPOLARITY */
843 l |= FLD_VAL(1, 20, 20); /* TE_VSYNC_POLARITY */
844 l |= FLD_VAL(1, 21, 21); /* HSYNCPOLARITY */
845 rfbi_write_reg(RFBI_CONFIG(rfbi_module), l);
847 rfbi_write_reg(RFBI_DATA_CYCLE1(rfbi_module), cycle1);
848 rfbi_write_reg(RFBI_DATA_CYCLE2(rfbi_module), cycle2);
849 rfbi_write_reg(RFBI_DATA_CYCLE3(rfbi_module), cycle3);
852 l = rfbi_read_reg(RFBI_CONTROL);
853 l = FLD_MOD(l, rfbi_module+1, 3, 2); /* Select CSx */
854 l = FLD_MOD(l, 0, 1, 1); /* clear bypass */
855 rfbi_write_reg(RFBI_CONTROL, l);
858 DSSDBG("RFBI config: bpp %d, lines %d, cycles: 0x%x 0x%x 0x%x\n",
859 bpp, lines, cycle1, cycle2, cycle3);
861 rfbi_enable_clocks(0);
865 EXPORT_SYMBOL(rfbi_configure);
867 int omap_rfbi_prepare_update(struct omap_dss_device *dssdev,
868 u16 *x, u16 *y, u16 *w, u16 *h)
872 dssdev->driver->get_resolution(dssdev, &dw, &dh);
874 if (*x > dw || *y > dh)
886 if (*w == 0 || *h == 0)
889 if (dssdev->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
890 dss_setup_partial_planes(dssdev, x, y, w, h, true);
891 dispc_set_lcd_size(dssdev->manager->id, *w, *h);
896 EXPORT_SYMBOL(omap_rfbi_prepare_update);
898 int omap_rfbi_update(struct omap_dss_device *dssdev,
899 u16 x, u16 y, u16 w, u16 h,
900 void (*callback)(void *), void *data)
902 if (dssdev->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
903 rfbi_transfer_area(dssdev, w, h, callback, data);
905 struct omap_overlay *ovl;
909 ovl = dssdev->manager->overlays[0];
910 scr_width = ovl->info.screen_width;
911 addr = ovl->info.vaddr;
913 omap_rfbi_write_pixels(addr, scr_width, x, y, w, h);
920 EXPORT_SYMBOL(omap_rfbi_update);
922 void rfbi_dump_regs(struct seq_file *s)
924 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, rfbi_read_reg(r))
926 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
928 DUMPREG(RFBI_REVISION);
929 DUMPREG(RFBI_SYSCONFIG);
930 DUMPREG(RFBI_SYSSTATUS);
931 DUMPREG(RFBI_CONTROL);
932 DUMPREG(RFBI_PIXEL_CNT);
933 DUMPREG(RFBI_LINE_NUMBER);
938 DUMPREG(RFBI_STATUS);
940 DUMPREG(RFBI_CONFIG(0));
941 DUMPREG(RFBI_ONOFF_TIME(0));
942 DUMPREG(RFBI_CYCLE_TIME(0));
943 DUMPREG(RFBI_DATA_CYCLE1(0));
944 DUMPREG(RFBI_DATA_CYCLE2(0));
945 DUMPREG(RFBI_DATA_CYCLE3(0));
947 DUMPREG(RFBI_CONFIG(1));
948 DUMPREG(RFBI_ONOFF_TIME(1));
949 DUMPREG(RFBI_CYCLE_TIME(1));
950 DUMPREG(RFBI_DATA_CYCLE1(1));
951 DUMPREG(RFBI_DATA_CYCLE2(1));
952 DUMPREG(RFBI_DATA_CYCLE3(1));
954 DUMPREG(RFBI_VSYNC_WIDTH);
955 DUMPREG(RFBI_HSYNC_WIDTH);
957 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
961 int omapdss_rfbi_display_enable(struct omap_dss_device *dssdev)
965 r = omap_dss_start_device(dssdev);
967 DSSERR("failed to start device\n");
971 r = omap_dispc_register_isr(framedone_callback, NULL,
972 DISPC_IRQ_FRAMEDONE);
974 DSSERR("can't get FRAMEDONE irq\n");
978 dispc_set_lcd_display_type(dssdev->manager->id,
979 OMAP_DSS_LCD_DISPLAY_TFT);
981 dispc_set_parallel_interface_mode(dssdev->manager->id,
982 OMAP_DSS_PARALLELMODE_RFBI);
984 dispc_set_tft_data_lines(dssdev->manager->id, dssdev->ctrl.pixel_size);
986 rfbi_configure(dssdev->phy.rfbi.channel,
987 dssdev->ctrl.pixel_size,
988 dssdev->phy.rfbi.data_lines);
990 rfbi_set_timings(dssdev->phy.rfbi.channel,
991 &dssdev->ctrl.rfbi_timings);
996 omap_dss_stop_device(dssdev);
1000 EXPORT_SYMBOL(omapdss_rfbi_display_enable);
1002 void omapdss_rfbi_display_disable(struct omap_dss_device *dssdev)
1004 omap_dispc_unregister_isr(framedone_callback, NULL,
1005 DISPC_IRQ_FRAMEDONE);
1006 omap_dss_stop_device(dssdev);
1008 EXPORT_SYMBOL(omapdss_rfbi_display_disable);
1010 int rfbi_init_display(struct omap_dss_device *dssdev)
1012 rfbi.dssdev[dssdev->phy.rfbi.channel] = dssdev;
1013 dssdev->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE;
1017 /* RFBI HW IP initialisation */
1018 static int omap_rfbihw_probe(struct platform_device *pdev)
1025 spin_lock_init(&rfbi.cmd_lock);
1027 init_completion(&rfbi.cmd_done);
1028 atomic_set(&rfbi.cmd_fifo_full, 0);
1029 atomic_set(&rfbi.cmd_pending, 0);
1031 rfbi.base = ioremap(RFBI_BASE, SZ_256);
1033 DSSERR("can't ioremap RFBI\n");
1037 rfbi_enable_clocks(1);
1041 rfbi.l4_khz = dss_clk_get_rate(DSS_CLK_ICK) / 1000;
1043 /* Enable autoidle and smart-idle */
1044 l = rfbi_read_reg(RFBI_SYSCONFIG);
1045 l |= (1 << 0) | (2 << 3);
1046 rfbi_write_reg(RFBI_SYSCONFIG, l);
1048 rev = rfbi_read_reg(RFBI_REVISION);
1049 dev_dbg(&pdev->dev, "OMAP RFBI rev %d.%d\n",
1050 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
1052 rfbi_enable_clocks(0);
1057 static int omap_rfbihw_remove(struct platform_device *pdev)
1063 static struct platform_driver omap_rfbihw_driver = {
1064 .probe = omap_rfbihw_probe,
1065 .remove = omap_rfbihw_remove,
1067 .name = "omapdss_rfbi",
1068 .owner = THIS_MODULE,
1072 int rfbi_init_platform_driver(void)
1074 return platform_driver_register(&omap_rfbihw_driver);
1077 void rfbi_uninit_platform_driver(void)
1079 return platform_driver_unregister(&omap_rfbihw_driver);