drivers/video/omap2/dss/dss_features.c

   1 /*
   2  * linux/drivers/video/omap2/dss/dss_features.c
   3  *
   4  * Copyright (C) 2010 Texas Instruments
   5  * Author: Archit Taneja <archit@ti.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License version 2 as published by
   9  * the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include <linux/kernel.h>
  21 #include <linux/types.h>
  22 #include <linux/err.h>
  23 #include <linux/slab.h>
  24
  25 #include <video/omapdss.h>
  26 #include <plat/cpu.h>
  27
  28 #include "dss.h"
  29 #include "dss_features.h"
  30
  31 /* Defines a generic omap register field */
  32 struct dss_reg_field {
  33         u8 start, end;
  34 };
  35
  36 struct dss_param_range {
  37         int min, max;
  38 };
  39
  40 struct omap_dss_features {
  41         const struct dss_reg_field *reg_fields;
  42         const int num_reg_fields;
  43
  44         const u32 has_feature;
  45
  46         const int num_mgrs;
  47         const int num_ovls;
  48         const enum omap_display_type *supported_displays;
  49         const enum omap_color_mode *supported_color_modes;
  50         const char * const *clksrc_names;
  51         const struct dss_param_range *dss_params;
  52 };
  53
  54 /* This struct is assigned to one of the below during initialization */
  55 static const struct omap_dss_features *omap_current_dss_features;
  56
  57 static const struct dss_reg_field omap2_dss_reg_fields[] = {
  58         [FEAT_REG_FIRHINC]                      = { 11, 0 },
  59         [FEAT_REG_FIRVINC]                      = { 27, 16 },
  60         [FEAT_REG_FIFOLOWTHRESHOLD]             = { 8, 0 },
  61         [FEAT_REG_FIFOHIGHTHRESHOLD]            = { 24, 16 },
  62         [FEAT_REG_FIFOSIZE]                     = { 8, 0 },
  63         [FEAT_REG_HORIZONTALACCU]               = { 9, 0 },
  64         [FEAT_REG_VERTICALACCU]                 = { 25, 16 },
  65         [FEAT_REG_DISPC_CLK_SWITCH]             = { 0, 0 },
  66         [FEAT_REG_DSIPLL_REGN]                  = { 0, 0 },
  67         [FEAT_REG_DSIPLL_REGM]                  = { 0, 0 },
  68         [FEAT_REG_DSIPLL_REGM_DISPC]            = { 0, 0 },
  69         [FEAT_REG_DSIPLL_REGM_DSI]              = { 0, 0 },
  70 };
  71
  72 static const struct dss_reg_field omap3_dss_reg_fields[] = {
  73         [FEAT_REG_FIRHINC]                      = { 12, 0 },
  74         [FEAT_REG_FIRVINC]                      = { 28, 16 },
  75         [FEAT_REG_FIFOLOWTHRESHOLD]             = { 11, 0 },
  76         [FEAT_REG_FIFOHIGHTHRESHOLD]            = { 27, 16 },
  77         [FEAT_REG_FIFOSIZE]                     = { 10, 0 },
  78         [FEAT_REG_HORIZONTALACCU]               = { 9, 0 },
  79         [FEAT_REG_VERTICALACCU]                 = { 25, 16 },
  80         [FEAT_REG_DISPC_CLK_SWITCH]             = { 0, 0 },
  81         [FEAT_REG_DSIPLL_REGN]                  = { 7, 1 },
  82         [FEAT_REG_DSIPLL_REGM]                  = { 18, 8 },
  83         [FEAT_REG_DSIPLL_REGM_DISPC]            = { 22, 19 },
  84         [FEAT_REG_DSIPLL_REGM_DSI]              = { 26, 23 },
  85 };
  86
  87 static const struct dss_reg_field omap4_dss_reg_fields[] = {
  88         [FEAT_REG_FIRHINC]                      = { 12, 0 },
  89         [FEAT_REG_FIRVINC]                      = { 28, 16 },
  90         [FEAT_REG_FIFOLOWTHRESHOLD]             = { 15, 0 },
  91         [FEAT_REG_FIFOHIGHTHRESHOLD]            = { 31, 16 },
  92         [FEAT_REG_FIFOSIZE]                     = { 15, 0 },
  93         [FEAT_REG_HORIZONTALACCU]               = { 10, 0 },
  94         [FEAT_REG_VERTICALACCU]                 = { 26, 16 },
  95         [FEAT_REG_DISPC_CLK_SWITCH]             = { 9, 8 },
  96         [FEAT_REG_DSIPLL_REGN]                  = { 8, 1 },
  97         [FEAT_REG_DSIPLL_REGM]                  = { 20, 9 },
  98         [FEAT_REG_DSIPLL_REGM_DISPC]            = { 25, 21 },
  99         [FEAT_REG_DSIPLL_REGM_DSI]              = { 30, 26 },
 100 };
 101
 102 static const enum omap_display_type omap2_dss_supported_displays[] = {
 103         /* OMAP_DSS_CHANNEL_LCD */
 104         OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI,
 105
 106         /* OMAP_DSS_CHANNEL_DIGIT */
 107         OMAP_DISPLAY_TYPE_VENC,
 108 };
 109
 110 static const enum omap_display_type omap3430_dss_supported_displays[] = {
 111         /* OMAP_DSS_CHANNEL_LCD */
 112         OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
 113         OMAP_DISPLAY_TYPE_SDI | OMAP_DISPLAY_TYPE_DSI,
 114
 115         /* OMAP_DSS_CHANNEL_DIGIT */
 116         OMAP_DISPLAY_TYPE_VENC,
 117 };
 118
 119 static const enum omap_display_type omap3630_dss_supported_displays[] = {
 120         /* OMAP_DSS_CHANNEL_LCD */
 121         OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
 122         OMAP_DISPLAY_TYPE_DSI,
 123
 124         /* OMAP_DSS_CHANNEL_DIGIT */
 125         OMAP_DISPLAY_TYPE_VENC,
 126 };
 127
 128 static const enum omap_display_type omap4_dss_supported_displays[] = {
 129         /* OMAP_DSS_CHANNEL_LCD */
 130         OMAP_DISPLAY_TYPE_DBI | OMAP_DISPLAY_TYPE_DSI,
 131
 132         /* OMAP_DSS_CHANNEL_DIGIT */
 133         OMAP_DISPLAY_TYPE_VENC | OMAP_DISPLAY_TYPE_HDMI,
 134
 135         /* OMAP_DSS_CHANNEL_LCD2 */
 136         OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
 137         OMAP_DISPLAY_TYPE_DSI,
 138 };
 139
 140 static const enum omap_color_mode omap2_dss_supported_color_modes[] = {
 141         /* OMAP_DSS_GFX */
 142         OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
 143         OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
 144         OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_RGB16 |
 145         OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P,
 146
 147         /* OMAP_DSS_VIDEO1 */
 148         OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
 149         OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
 150         OMAP_DSS_COLOR_UYVY,
 151
 152         /* OMAP_DSS_VIDEO2 */
 153         OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
 154         OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
 155         OMAP_DSS_COLOR_UYVY,
 156 };
 157
 158 static const enum omap_color_mode omap3_dss_supported_color_modes[] = {
 159         /* OMAP_DSS_GFX */
 160         OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
 161         OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
 162         OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
 163         OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
 164         OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_ARGB32 |
 165         OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
 166
 167         /* OMAP_DSS_VIDEO1 */
 168         OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P |
 169         OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_RGB16 |
 170         OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_UYVY,
 171
 172         /* OMAP_DSS_VIDEO2 */
 173         OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
 174         OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
 175         OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
 176         OMAP_DSS_COLOR_UYVY | OMAP_DSS_COLOR_ARGB32 |
 177         OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
 178 };
 179
 180 static const char * const omap2_dss_clk_source_names[] = {
 181         [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC]  = "N/A",
 182         [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI]    = "N/A",
 183         [OMAP_DSS_CLK_SRC_FCK]                  = "DSS_FCLK1",
 184 };
 185
 186 static const char * const omap3_dss_clk_source_names[] = {
 187         [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC]  = "DSI1_PLL_FCLK",
 188         [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI]    = "DSI2_PLL_FCLK",
 189         [OMAP_DSS_CLK_SRC_FCK]                  = "DSS1_ALWON_FCLK",
 190 };
 191
 192 static const char * const omap4_dss_clk_source_names[] = {
 193         [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC]  = "PLL1_CLK1",
 194         [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI]    = "PLL1_CLK2",
 195         [OMAP_DSS_CLK_SRC_FCK]                  = "DSS_FCLK",
 196         [OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC] = "PLL2_CLK1",
 197         [OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI]   = "PLL2_CLK2",
 198 };
 199
 200 static const struct dss_param_range omap2_dss_param_range[] = {
 201         [FEAT_PARAM_DSS_FCK]                    = { 0, 173000000 },
 202         [FEAT_PARAM_DSIPLL_REGN]                = { 0, 0 },
 203         [FEAT_PARAM_DSIPLL_REGM]                = { 0, 0 },
 204         [FEAT_PARAM_DSIPLL_REGM_DISPC]          = { 0, 0 },
 205         [FEAT_PARAM_DSIPLL_REGM_DSI]            = { 0, 0 },
 206         [FEAT_PARAM_DSIPLL_FINT]                = { 0, 0 },
 207         [FEAT_PARAM_DSIPLL_LPDIV]               = { 0, 0 },
 208 };
 209
 210 static const struct dss_param_range omap3_dss_param_range[] = {
 211         [FEAT_PARAM_DSS_FCK]                    = { 0, 173000000 },
 212         [FEAT_PARAM_DSIPLL_REGN]                = { 0, (1 << 7) - 1 },
 213         [FEAT_PARAM_DSIPLL_REGM]                = { 0, (1 << 11) - 1 },
 214         [FEAT_PARAM_DSIPLL_REGM_DISPC]          = { 0, (1 << 4) - 1 },
 215         [FEAT_PARAM_DSIPLL_REGM_DSI]            = { 0, (1 << 4) - 1 },
 216         [FEAT_PARAM_DSIPLL_FINT]                = { 750000, 2100000 },
 217         [FEAT_PARAM_DSIPLL_LPDIV]               = { 1, (1 << 13) - 1},
 218 };
 219
 220 static const struct dss_param_range omap4_dss_param_range[] = {
 221         [FEAT_PARAM_DSS_FCK]                    = { 0, 186000000 },
 222         [FEAT_PARAM_DSIPLL_REGN]                = { 0, (1 << 8) - 1 },
 223         [FEAT_PARAM_DSIPLL_REGM]                = { 0, (1 << 12) - 1 },
 224         [FEAT_PARAM_DSIPLL_REGM_DISPC]          = { 0, (1 << 5) - 1 },
 225         [FEAT_PARAM_DSIPLL_REGM_DSI]            = { 0, (1 << 5) - 1 },
 226         [FEAT_PARAM_DSIPLL_FINT]                = { 500000, 2500000 },
 227         [FEAT_PARAM_DSIPLL_LPDIV]               = { 0, (1 << 13) - 1 },
 228 };
 229
 230 /* OMAP2 DSS Features */
 231 static const struct omap_dss_features omap2_dss_features = {
 232         .reg_fields = omap2_dss_reg_fields,
 233         .num_reg_fields = ARRAY_SIZE(omap2_dss_reg_fields),
 234
 235         .has_feature    =
 236                 FEAT_LCDENABLEPOL | FEAT_LCDENABLESIGNAL |
 237                 FEAT_PCKFREEENABLE | FEAT_FUNCGATED |
 238                 FEAT_ROWREPEATENABLE | FEAT_RESIZECONF,
 239
 240         .num_mgrs = 2,
 241         .num_ovls = 3,
 242         .supported_displays = omap2_dss_supported_displays,
 243         .supported_color_modes = omap2_dss_supported_color_modes,
 244         .clksrc_names = omap2_dss_clk_source_names,
 245         .dss_params = omap2_dss_param_range,
 246 };
 247
 248 /* OMAP3 DSS Features */
 249 static const struct omap_dss_features omap3430_dss_features = {
 250         .reg_fields = omap3_dss_reg_fields,
 251         .num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields),
 252
 253         .has_feature    =
 254                 FEAT_GLOBAL_ALPHA | FEAT_LCDENABLEPOL |
 255                 FEAT_LCDENABLESIGNAL | FEAT_PCKFREEENABLE |
 256                 FEAT_FUNCGATED | FEAT_ROWREPEATENABLE |
 257                 FEAT_LINEBUFFERSPLIT | FEAT_RESIZECONF |
 258                 FEAT_DSI_PLL_FREQSEL | FEAT_DSI_REVERSE_TXCLKESC,
 259
 260         .num_mgrs = 2,
 261         .num_ovls = 3,
 262         .supported_displays = omap3430_dss_supported_displays,
 263         .supported_color_modes = omap3_dss_supported_color_modes,
 264         .clksrc_names = omap3_dss_clk_source_names,
 265         .dss_params = omap3_dss_param_range,
 266 };
 267
 268 static const struct omap_dss_features omap3630_dss_features = {
 269         .reg_fields = omap3_dss_reg_fields,
 270         .num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields),
 271
 272         .has_feature    =
 273                 FEAT_GLOBAL_ALPHA | FEAT_LCDENABLEPOL |
 274                 FEAT_LCDENABLESIGNAL | FEAT_PCKFREEENABLE |
 275                 FEAT_PRE_MULT_ALPHA | FEAT_FUNCGATED |
 276                 FEAT_ROWREPEATENABLE | FEAT_LINEBUFFERSPLIT |
 277                 FEAT_RESIZECONF | FEAT_DSI_PLL_PWR_BUG |
 278                 FEAT_DSI_PLL_FREQSEL,
 279
 280         .num_mgrs = 2,
 281         .num_ovls = 3,
 282         .supported_displays = omap3630_dss_supported_displays,
 283         .supported_color_modes = omap3_dss_supported_color_modes,
 284         .clksrc_names = omap3_dss_clk_source_names,
 285         .dss_params = omap3_dss_param_range,
 286 };
 287
 288 /* OMAP4 DSS Features */
 289 /* For OMAP4430 ES 1.0 revision */
 290 static const struct omap_dss_features omap4430_es1_0_dss_features  = {
 291         .reg_fields = omap4_dss_reg_fields,
 292         .num_reg_fields = ARRAY_SIZE(omap4_dss_reg_fields),
 293
 294         .has_feature    =
 295                 FEAT_GLOBAL_ALPHA | FEAT_PRE_MULT_ALPHA |
 296                 FEAT_MGR_LCD2 | FEAT_GLOBAL_ALPHA_VID1 |
 297                 FEAT_CORE_CLK_DIV | FEAT_LCD_CLK_SRC |
 298                 FEAT_DSI_DCS_CMD_CONFIG_VC | FEAT_DSI_VC_OCP_WIDTH |
 299                 FEAT_DSI_GNQ,
 300
 301         .num_mgrs = 3,
 302         .num_ovls = 3,
 303         .supported_displays = omap4_dss_supported_displays,
 304         .supported_color_modes = omap3_dss_supported_color_modes,
 305         .clksrc_names = omap4_dss_clk_source_names,
 306         .dss_params = omap4_dss_param_range,
 307 };
 308
 309 /* For all the other OMAP4 versions */
 310 static const struct omap_dss_features omap4_dss_features = {
 311         .reg_fields = omap4_dss_reg_fields,
 312         .num_reg_fields = ARRAY_SIZE(omap4_dss_reg_fields),
 313
 314         .has_feature    =
 315                 FEAT_GLOBAL_ALPHA | FEAT_PRE_MULT_ALPHA |
 316                 FEAT_MGR_LCD2 | FEAT_GLOBAL_ALPHA_VID1 |
 317                 FEAT_CORE_CLK_DIV | FEAT_LCD_CLK_SRC |
 318                 FEAT_DSI_DCS_CMD_CONFIG_VC | FEAT_DSI_VC_OCP_WIDTH |
 319                 FEAT_DSI_GNQ | FEAT_HDMI_CTS_SWMODE,
 320
 321         .num_mgrs = 3,
 322         .num_ovls = 3,
 323         .supported_displays = omap4_dss_supported_displays,
 324         .supported_color_modes = omap3_dss_supported_color_modes,
 325         .clksrc_names = omap4_dss_clk_source_names,
 326         .dss_params = omap4_dss_param_range,
 327 };
 328
 329 /* Functions returning values related to a DSS feature */
 330 int dss_feat_get_num_mgrs(void)
 331 {
 332         return omap_current_dss_features->num_mgrs;
 333 }
 334
 335 int dss_feat_get_num_ovls(void)
 336 {
 337         return omap_current_dss_features->num_ovls;
 338 }
 339
 340 unsigned long dss_feat_get_param_min(enum dss_range_param param)
 341 {
 342         return omap_current_dss_features->dss_params[param].min;
 343 }
 344
 345 unsigned long dss_feat_get_param_max(enum dss_range_param param)
 346 {
 347         return omap_current_dss_features->dss_params[param].max;
 348 }
 349
 350 enum omap_display_type dss_feat_get_supported_displays(enum omap_channel channel)
 351 {
 352         return omap_current_dss_features->supported_displays[channel];
 353 }
 354
 355 enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane)
 356 {
 357         return omap_current_dss_features->supported_color_modes[plane];
 358 }
 359
 360 bool dss_feat_color_mode_supported(enum omap_plane plane,
 361                 enum omap_color_mode color_mode)
 362 {
 363         return omap_current_dss_features->supported_color_modes[plane] &
 364                         color_mode;
 365 }
 366
 367 const char *dss_feat_get_clk_source_name(enum omap_dss_clk_source id)
 368 {
 369         return omap_current_dss_features->clksrc_names[id];
 370 }
 371
 372 /* DSS has_feature check */
 373 bool dss_has_feature(enum dss_feat_id id)
 374 {
 375         return omap_current_dss_features->has_feature & id;
 376 }
 377
 378 void dss_feat_get_reg_field(enum dss_feat_reg_field id, u8 *start, u8 *end)
 379 {
 380         if (id >= omap_current_dss_features->num_reg_fields)
 381                 BUG();
 382
 383         *start = omap_current_dss_features->reg_fields[id].start;
 384         *end = omap_current_dss_features->reg_fields[id].end;
 385 }
 386
 387 void dss_features_init(void)
 388 {
 389         if (cpu_is_omap24xx())
 390                 omap_current_dss_features = &omap2_dss_features;
 391         else if (cpu_is_omap3630())
 392                 omap_current_dss_features = &omap3630_dss_features;
 393         else if (cpu_is_omap34xx())
 394                 omap_current_dss_features = &omap3430_dss_features;
 395         else if (omap_rev() == OMAP4430_REV_ES1_0)
 396                 omap_current_dss_features = &omap4430_es1_0_dss_features;
 397         else if (cpu_is_omap44xx())
 398                 omap_current_dss_features = &omap4_dss_features;
 399         else
 400                 DSSWARN("Unsupported OMAP version");
 401 }