drivers/video/omap2/dss/dss.c

   1 /*
   2  * linux/drivers/video/omap2/dss/dss.c
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * Some code and ideas taken from drivers/video/omap/ driver
   8  * by Imre Deak.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published by
  12  * the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #define DSS_SUBSYS_NAME "DSS"
  24
  25 #include <linux/kernel.h>
  26 #include <linux/io.h>
  27 #include <linux/err.h>
  28 #include <linux/delay.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/seq_file.h>
  31 #include <linux/clk.h>
  32
  33 #include <plat/display.h>
  34 #include "dss.h"
  35
  36 #define DSS_BASE                        0x48050000
  37
  38 #define DSS_SZ_REGS                     SZ_512
  39
  40 struct dss_reg {
  41         u16 idx;
  42 };
  43
  44 #define DSS_REG(idx)                    ((const struct dss_reg) { idx })
  45
  46 #define DSS_REVISION                    DSS_REG(0x0000)
  47 #define DSS_SYSCONFIG                   DSS_REG(0x0010)
  48 #define DSS_SYSSTATUS                   DSS_REG(0x0014)
  49 #define DSS_IRQSTATUS                   DSS_REG(0x0018)
  50 #define DSS_CONTROL                     DSS_REG(0x0040)
  51 #define DSS_SDI_CONTROL                 DSS_REG(0x0044)
  52 #define DSS_PLL_CONTROL                 DSS_REG(0x0048)
  53 #define DSS_SDI_STATUS                  DSS_REG(0x005C)
  54
  55 #define REG_GET(idx, start, end) \
  56         FLD_GET(dss_read_reg(idx), start, end)
  57
  58 #define REG_FLD_MOD(idx, val, start, end) \
  59         dss_write_reg(idx, FLD_MOD(dss_read_reg(idx), val, start, end))
  60
  61 static struct {
  62         void __iomem    *base;
  63
  64         struct clk      *dpll4_m4_ck;
  65
  66         unsigned long   cache_req_pck;
  67         unsigned long   cache_prate;
  68         struct dss_clock_info cache_dss_cinfo;
  69         struct dispc_clock_info cache_dispc_cinfo;
  70
  71         enum dss_clk_source dsi_clk_source;
  72         enum dss_clk_source dispc_clk_source;
  73
  74         u32             ctx[DSS_SZ_REGS / sizeof(u32)];
  75 } dss;
  76
  77 static int _omap_dss_wait_reset(void);
  78
  79 static inline void dss_write_reg(const struct dss_reg idx, u32 val)
  80 {
  81         __raw_writel(val, dss.base + idx.idx);
  82 }
  83
  84 static inline u32 dss_read_reg(const struct dss_reg idx)
  85 {
  86         return __raw_readl(dss.base + idx.idx);
  87 }
  88
  89 #define SR(reg) \
  90         dss.ctx[(DSS_##reg).idx / sizeof(u32)] = dss_read_reg(DSS_##reg)
  91 #define RR(reg) \
  92         dss_write_reg(DSS_##reg, dss.ctx[(DSS_##reg).idx / sizeof(u32)])
  93
  94 void dss_save_context(void)
  95 {
  96         if (cpu_is_omap24xx())
  97                 return;
  98
  99         SR(SYSCONFIG);
 100         SR(CONTROL);
 101
 102 #ifdef CONFIG_OMAP2_DSS_SDI
 103         SR(SDI_CONTROL);
 104         SR(PLL_CONTROL);
 105 #endif
 106 }
 107
 108 void dss_restore_context(void)
 109 {
 110         if (_omap_dss_wait_reset())
 111                 DSSERR("DSS not coming out of reset after sleep\n");
 112
 113         RR(SYSCONFIG);
 114         RR(CONTROL);
 115
 116 #ifdef CONFIG_OMAP2_DSS_SDI
 117         RR(SDI_CONTROL);
 118         RR(PLL_CONTROL);
 119 #endif
 120 }
 121
 122 #undef SR
 123 #undef RR
 124
 125 void dss_sdi_init(u8 datapairs)
 126 {
 127         u32 l;
 128
 129         BUG_ON(datapairs > 3 || datapairs < 1);
 130
 131         l = dss_read_reg(DSS_SDI_CONTROL);
 132         l = FLD_MOD(l, 0xf, 19, 15);            /* SDI_PDIV */
 133         l = FLD_MOD(l, datapairs-1, 3, 2);      /* SDI_PRSEL */
 134         l = FLD_MOD(l, 2, 1, 0);                /* SDI_BWSEL */
 135         dss_write_reg(DSS_SDI_CONTROL, l);
 136
 137         l = dss_read_reg(DSS_PLL_CONTROL);
 138         l = FLD_MOD(l, 0x7, 25, 22);    /* SDI_PLL_FREQSEL */
 139         l = FLD_MOD(l, 0xb, 16, 11);    /* SDI_PLL_REGN */
 140         l = FLD_MOD(l, 0xb4, 10, 1);    /* SDI_PLL_REGM */
 141         dss_write_reg(DSS_PLL_CONTROL, l);
 142 }
 143
 144 int dss_sdi_enable(void)
 145 {
 146         unsigned long timeout;
 147
 148         dispc_pck_free_enable(1);
 149
 150         /* Reset SDI PLL */
 151         REG_FLD_MOD(DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */
 152         udelay(1);      /* wait 2x PCLK */
 153
 154         /* Lock SDI PLL */
 155         REG_FLD_MOD(DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */
 156
 157         /* Waiting for PLL lock request to complete */
 158         timeout = jiffies + msecs_to_jiffies(500);
 159         while (dss_read_reg(DSS_SDI_STATUS) & (1 << 6)) {
 160                 if (time_after_eq(jiffies, timeout)) {
 161                         DSSERR("PLL lock request timed out\n");
 162                         goto err1;
 163                 }
 164         }
 165
 166         /* Clearing PLL_GO bit */
 167         REG_FLD_MOD(DSS_PLL_CONTROL, 0, 28, 28);
 168
 169         /* Waiting for PLL to lock */
 170         timeout = jiffies + msecs_to_jiffies(500);
 171         while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 5))) {
 172                 if (time_after_eq(jiffies, timeout)) {
 173                         DSSERR("PLL lock timed out\n");
 174                         goto err1;
 175                 }
 176         }
 177
 178         dispc_lcd_enable_signal(1);
 179
 180         /* Waiting for SDI reset to complete */
 181         timeout = jiffies + msecs_to_jiffies(500);
 182         while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 2))) {
 183                 if (time_after_eq(jiffies, timeout)) {
 184                         DSSERR("SDI reset timed out\n");
 185                         goto err2;
 186                 }
 187         }
 188
 189         return 0;
 190
 191  err2:
 192         dispc_lcd_enable_signal(0);
 193  err1:
 194         /* Reset SDI PLL */
 195         REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
 196
 197         dispc_pck_free_enable(0);
 198
 199         return -ETIMEDOUT;
 200 }
 201
 202 void dss_sdi_disable(void)
 203 {
 204         dispc_lcd_enable_signal(0);
 205
 206         dispc_pck_free_enable(0);
 207
 208         /* Reset SDI PLL */
 209         REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
 210 }
 211
 212 void dss_dump_clocks(struct seq_file *s)
 213 {
 214         unsigned long dpll4_ck_rate;
 215         unsigned long dpll4_m4_ck_rate;
 216
 217         dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
 218
 219         dpll4_ck_rate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
 220         dpll4_m4_ck_rate = clk_get_rate(dss.dpll4_m4_ck);
 221
 222         seq_printf(s, "- DSS -\n");
 223
 224         seq_printf(s, "dpll4_ck %lu\n", dpll4_ck_rate);
 225
 226         if (cpu_is_omap3630())
 227                 seq_printf(s, "dss1_alwon_fclk = %lu / %lu  = %lu\n",
 228                         dpll4_ck_rate,
 229                         dpll4_ck_rate / dpll4_m4_ck_rate,
 230                         dss_clk_get_rate(DSS_CLK_FCK1));
 231         else
 232                 seq_printf(s, "dss1_alwon_fclk = %lu / %lu * 2 = %lu\n",
 233                         dpll4_ck_rate,
 234                         dpll4_ck_rate / dpll4_m4_ck_rate,
 235                         dss_clk_get_rate(DSS_CLK_FCK1));
 236
 237         dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
 238 }
 239
 240 void dss_dump_regs(struct seq_file *s)
 241 {
 242 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(r))
 243
 244         dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
 245
 246         DUMPREG(DSS_REVISION);
 247         DUMPREG(DSS_SYSCONFIG);
 248         DUMPREG(DSS_SYSSTATUS);
 249         DUMPREG(DSS_IRQSTATUS);
 250         DUMPREG(DSS_CONTROL);
 251         DUMPREG(DSS_SDI_CONTROL);
 252         DUMPREG(DSS_PLL_CONTROL);
 253         DUMPREG(DSS_SDI_STATUS);
 254
 255         dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
 256 #undef DUMPREG
 257 }
 258
 259 void dss_select_dispc_clk_source(enum dss_clk_source clk_src)
 260 {
 261         int b;
 262
 263         BUG_ON(clk_src != DSS_SRC_DSI1_PLL_FCLK &&
 264                         clk_src != DSS_SRC_DSS1_ALWON_FCLK);
 265
 266         b = clk_src == DSS_SRC_DSS1_ALWON_FCLK ? 0 : 1;
 267
 268         REG_FLD_MOD(DSS_CONTROL, b, 0, 0);      /* DISPC_CLK_SWITCH */
 269
 270         dss.dispc_clk_source = clk_src;
 271 }
 272
 273 void dss_select_dsi_clk_source(enum dss_clk_source clk_src)
 274 {
 275         int b;
 276
 277         BUG_ON(clk_src != DSS_SRC_DSI2_PLL_FCLK &&
 278                         clk_src != DSS_SRC_DSS1_ALWON_FCLK);
 279
 280         b = clk_src == DSS_SRC_DSS1_ALWON_FCLK ? 0 : 1;
 281
 282         REG_FLD_MOD(DSS_CONTROL, b, 1, 1);      /* DSI_CLK_SWITCH */
 283
 284         dss.dsi_clk_source = clk_src;
 285 }
 286
 287 enum dss_clk_source dss_get_dispc_clk_source(void)
 288 {
 289         return dss.dispc_clk_source;
 290 }
 291
 292 enum dss_clk_source dss_get_dsi_clk_source(void)
 293 {
 294         return dss.dsi_clk_source;
 295 }
 296
 297 /* calculate clock rates using dividers in cinfo */
 298 int dss_calc_clock_rates(struct dss_clock_info *cinfo)
 299 {
 300         unsigned long prate;
 301
 302         if (cinfo->fck_div > (cpu_is_omap3630() ? 32 : 16) ||
 303                                                 cinfo->fck_div == 0)
 304                 return -EINVAL;
 305
 306         prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
 307
 308         cinfo->fck = prate / cinfo->fck_div;
 309
 310         return 0;
 311 }
 312
 313 int dss_set_clock_div(struct dss_clock_info *cinfo)
 314 {
 315         unsigned long prate;
 316         int r;
 317
 318         if (cpu_is_omap34xx()) {
 319                 prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
 320                 DSSDBG("dpll4_m4 = %ld\n", prate);
 321
 322                 r = clk_set_rate(dss.dpll4_m4_ck, prate / cinfo->fck_div);
 323                 if (r)
 324                         return r;
 325         }
 326
 327         DSSDBG("fck = %ld (%d)\n", cinfo->fck, cinfo->fck_div);
 328
 329         return 0;
 330 }
 331
 332 int dss_get_clock_div(struct dss_clock_info *cinfo)
 333 {
 334         cinfo->fck = dss_clk_get_rate(DSS_CLK_FCK1);
 335
 336         if (cpu_is_omap34xx()) {
 337                 unsigned long prate;
 338                 prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
 339                 if (cpu_is_omap3630())
 340                         cinfo->fck_div = prate / (cinfo->fck);
 341                 else
 342                         cinfo->fck_div = prate / (cinfo->fck / 2);
 343         } else {
 344                 cinfo->fck_div = 0;
 345         }
 346
 347         return 0;
 348 }
 349
 350 unsigned long dss_get_dpll4_rate(void)
 351 {
 352         if (cpu_is_omap34xx())
 353                 return clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
 354         else
 355                 return 0;
 356 }
 357
 358 int dss_calc_clock_div(bool is_tft, unsigned long req_pck,
 359                 struct dss_clock_info *dss_cinfo,
 360                 struct dispc_clock_info *dispc_cinfo)
 361 {
 362         unsigned long prate;
 363         struct dss_clock_info best_dss;
 364         struct dispc_clock_info best_dispc;
 365
 366         unsigned long fck;
 367
 368         u16 fck_div;
 369
 370         int match = 0;
 371         int min_fck_per_pck;
 372
 373         prate = dss_get_dpll4_rate();
 374
 375         fck = dss_clk_get_rate(DSS_CLK_FCK1);
 376         if (req_pck == dss.cache_req_pck &&
 377                         ((cpu_is_omap34xx() && prate == dss.cache_prate) ||
 378                          dss.cache_dss_cinfo.fck == fck)) {
 379                 DSSDBG("dispc clock info found from cache.\n");
 380                 *dss_cinfo = dss.cache_dss_cinfo;
 381                 *dispc_cinfo = dss.cache_dispc_cinfo;
 382                 return 0;
 383         }
 384
 385         min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
 386
 387         if (min_fck_per_pck &&
 388                 req_pck * min_fck_per_pck > DISPC_MAX_FCK) {
 389                 DSSERR("Requested pixel clock not possible with the current "
 390                                 "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
 391                                 "the constraint off.\n");
 392                 min_fck_per_pck = 0;
 393         }
 394
 395 retry:
 396         memset(&best_dss, 0, sizeof(best_dss));
 397         memset(&best_dispc, 0, sizeof(best_dispc));
 398
 399         if (cpu_is_omap24xx()) {
 400                 struct dispc_clock_info cur_dispc;
 401                 /* XXX can we change the clock on omap2? */
 402                 fck = dss_clk_get_rate(DSS_CLK_FCK1);
 403                 fck_div = 1;
 404
 405                 dispc_find_clk_divs(is_tft, req_pck, fck, &cur_dispc);
 406                 match = 1;
 407
 408                 best_dss.fck = fck;
 409                 best_dss.fck_div = fck_div;
 410
 411                 best_dispc = cur_dispc;
 412
 413                 goto found;
 414         } else if (cpu_is_omap34xx()) {
 415                 for (fck_div = (cpu_is_omap3630() ? 32 : 16);
 416                                         fck_div > 0; --fck_div) {
 417                         struct dispc_clock_info cur_dispc;
 418
 419                         if (cpu_is_omap3630())
 420                                 fck = prate / fck_div;
 421                         else
 422                                 fck = prate / fck_div * 2;
 423
 424                         if (fck > DISPC_MAX_FCK)
 425                                 continue;
 426
 427                         if (min_fck_per_pck &&
 428                                         fck < req_pck * min_fck_per_pck)
 429                                 continue;
 430
 431                         match = 1;
 432
 433                         dispc_find_clk_divs(is_tft, req_pck, fck, &cur_dispc);
 434
 435                         if (abs(cur_dispc.pck - req_pck) <
 436                                         abs(best_dispc.pck - req_pck)) {
 437
 438                                 best_dss.fck = fck;
 439                                 best_dss.fck_div = fck_div;
 440
 441                                 best_dispc = cur_dispc;
 442
 443                                 if (cur_dispc.pck == req_pck)
 444                                         goto found;
 445                         }
 446                 }
 447         } else {
 448                 BUG();
 449         }
 450
 451 found:
 452         if (!match) {
 453                 if (min_fck_per_pck) {
 454                         DSSERR("Could not find suitable clock settings.\n"
 455                                         "Turning FCK/PCK constraint off and"
 456                                         "trying again.\n");
 457                         min_fck_per_pck = 0;
 458                         goto retry;
 459                 }
 460
 461                 DSSERR("Could not find suitable clock settings.\n");
 462
 463                 return -EINVAL;
 464         }
 465
 466         if (dss_cinfo)
 467                 *dss_cinfo = best_dss;
 468         if (dispc_cinfo)
 469                 *dispc_cinfo = best_dispc;
 470
 471         dss.cache_req_pck = req_pck;
 472         dss.cache_prate = prate;
 473         dss.cache_dss_cinfo = best_dss;
 474         dss.cache_dispc_cinfo = best_dispc;
 475
 476         return 0;
 477 }
 478
 479
 480
 481 static irqreturn_t dss_irq_handler_omap2(int irq, void *arg)
 482 {
 483         dispc_irq_handler();
 484
 485         return IRQ_HANDLED;
 486 }
 487
 488 static irqreturn_t dss_irq_handler_omap3(int irq, void *arg)
 489 {
 490         u32 irqstatus;
 491
 492         irqstatus = dss_read_reg(DSS_IRQSTATUS);
 493
 494         if (irqstatus & (1<<0)) /* DISPC_IRQ */
 495                 dispc_irq_handler();
 496 #ifdef CONFIG_OMAP2_DSS_DSI
 497         if (irqstatus & (1<<1)) /* DSI_IRQ */
 498                 dsi_irq_handler();
 499 #endif
 500
 501         return IRQ_HANDLED;
 502 }
 503
 504 static int _omap_dss_wait_reset(void)
 505 {
 506         int t = 0;
 507
 508         while (REG_GET(DSS_SYSSTATUS, 0, 0) == 0) {
 509                 if (++t > 1000) {
 510                         DSSERR("soft reset failed\n");
 511                         return -ENODEV;
 512                 }
 513                 udelay(1);
 514         }
 515
 516         return 0;
 517 }
 518
 519 static int _omap_dss_reset(void)
 520 {
 521         /* Soft reset */
 522         REG_FLD_MOD(DSS_SYSCONFIG, 1, 1, 1);
 523         return _omap_dss_wait_reset();
 524 }
 525
 526 void dss_set_venc_output(enum omap_dss_venc_type type)
 527 {
 528         int l = 0;
 529
 530         if (type == OMAP_DSS_VENC_TYPE_COMPOSITE)
 531                 l = 0;
 532         else if (type == OMAP_DSS_VENC_TYPE_SVIDEO)
 533                 l = 1;
 534         else
 535                 BUG();
 536
 537         /* venc out selection. 0 = comp, 1 = svideo */
 538         REG_FLD_MOD(DSS_CONTROL, l, 6, 6);
 539 }
 540
 541 void dss_set_dac_pwrdn_bgz(bool enable)
 542 {
 543         REG_FLD_MOD(DSS_CONTROL, enable, 5, 5); /* DAC Power-Down Control */
 544 }
 545
 546 int dss_init(bool skip_init)
 547 {
 548         int r;
 549         u32 rev;
 550
 551         dss.base = ioremap(DSS_BASE, DSS_SZ_REGS);
 552         if (!dss.base) {
 553                 DSSERR("can't ioremap DSS\n");
 554                 r = -ENOMEM;
 555                 goto fail0;
 556         }
 557
 558         if (!skip_init) {
 559                 /* disable LCD and DIGIT output. This seems to fix the synclost
 560                  * problem that we get, if the bootloader starts the DSS and
 561                  * the kernel resets it */
 562                 omap_writel(omap_readl(0x48050440) & ~0x3, 0x48050440);
 563
 564                 /* We need to wait here a bit, otherwise we sometimes start to
 565                  * get synclost errors, and after that only power cycle will
 566                  * restore DSS functionality. I have no idea why this happens.
 567                  * And we have to wait _before_ resetting the DSS, but after
 568                  * enabling clocks.
 569                  */
 570                 msleep(50);
 571
 572                 _omap_dss_reset();
 573         }
 574
 575         /* autoidle */
 576         REG_FLD_MOD(DSS_SYSCONFIG, 1, 0, 0);
 577
 578         /* Select DPLL */
 579         REG_FLD_MOD(DSS_CONTROL, 0, 0, 0);
 580
 581 #ifdef CONFIG_OMAP2_DSS_VENC
 582         REG_FLD_MOD(DSS_CONTROL, 1, 4, 4);      /* venc dac demen */
 583         REG_FLD_MOD(DSS_CONTROL, 1, 3, 3);      /* venc clock 4x enable */
 584         REG_FLD_MOD(DSS_CONTROL, 0, 2, 2);      /* venc clock mode = normal */
 585 #endif
 586
 587         r = request_irq(INT_24XX_DSS_IRQ,
 588                         cpu_is_omap24xx()
 589                         ? dss_irq_handler_omap2
 590                         : dss_irq_handler_omap3,
 591                         0, "OMAP DSS", NULL);
 592
 593         if (r < 0) {
 594                 DSSERR("omap2 dss: request_irq failed\n");
 595                 goto fail1;
 596         }
 597
 598         if (cpu_is_omap34xx()) {
 599                 dss.dpll4_m4_ck = clk_get(NULL, "dpll4_m4_ck");
 600                 if (IS_ERR(dss.dpll4_m4_ck)) {
 601                         DSSERR("Failed to get dpll4_m4_ck\n");
 602                         r = PTR_ERR(dss.dpll4_m4_ck);
 603                         goto fail2;
 604                 }
 605         }
 606
 607         dss.dsi_clk_source = DSS_SRC_DSS1_ALWON_FCLK;
 608         dss.dispc_clk_source = DSS_SRC_DSS1_ALWON_FCLK;
 609
 610         dss_save_context();
 611
 612         rev = dss_read_reg(DSS_REVISION);
 613         printk(KERN_INFO "OMAP DSS rev %d.%d\n",
 614                         FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
 615
 616         return 0;
 617
 618 fail2:
 619         free_irq(INT_24XX_DSS_IRQ, NULL);
 620 fail1:
 621         iounmap(dss.base);
 622 fail0:
 623         return r;
 624 }
 625
 626 void dss_exit(void)
 627 {
 628         if (cpu_is_omap34xx())
 629                 clk_put(dss.dpll4_m4_ck);
 630
 631         free_irq(INT_24XX_DSS_IRQ, NULL);
 632
 633         iounmap(dss.base);
 634 }
 635