drivers/video/omap2/dss/dsi.c

   1 /*
   2  * linux/drivers/video/omap2/dss/dsi.c
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License version 2 as published by
   9  * the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #define DSS_SUBSYS_NAME "DSI"
  21
  22 #include <linux/kernel.h>
  23 #include <linux/io.h>
  24 #include <linux/clk.h>
  25 #include <linux/device.h>
  26 #include <linux/err.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/delay.h>
  29 #include <linux/mutex.h>
  30 #include <linux/module.h>
  31 #include <linux/semaphore.h>
  32 #include <linux/seq_file.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/regulator/consumer.h>
  35 #include <linux/wait.h>
  36 #include <linux/workqueue.h>
  37 #include <linux/sched.h>
  38 #include <linux/slab.h>
  39 #include <linux/debugfs.h>
  40 #include <linux/pm_runtime.h>
  41
  42 #include <video/omapdss.h>
  43 #include <video/mipi_display.h>
  44 #include <plat/clock.h>
  45
  46 #include "dss.h"
  47 #include "dss_features.h"
  48
  49 /*#define VERBOSE_IRQ*/
  50 #define DSI_CATCH_MISSING_TE
  51
  52 struct dsi_reg { u16 idx; };
  53
  54 #define DSI_REG(idx)            ((const struct dsi_reg) { idx })
  55
  56 #define DSI_SZ_REGS             SZ_1K
  57 /* DSI Protocol Engine */
  58
  59 #define DSI_REVISION                    DSI_REG(0x0000)
  60 #define DSI_SYSCONFIG                   DSI_REG(0x0010)
  61 #define DSI_SYSSTATUS                   DSI_REG(0x0014)
  62 #define DSI_IRQSTATUS                   DSI_REG(0x0018)
  63 #define DSI_IRQENABLE                   DSI_REG(0x001C)
  64 #define DSI_CTRL                        DSI_REG(0x0040)
  65 #define DSI_GNQ                         DSI_REG(0x0044)
  66 #define DSI_COMPLEXIO_CFG1              DSI_REG(0x0048)
  67 #define DSI_COMPLEXIO_IRQ_STATUS        DSI_REG(0x004C)
  68 #define DSI_COMPLEXIO_IRQ_ENABLE        DSI_REG(0x0050)
  69 #define DSI_CLK_CTRL                    DSI_REG(0x0054)
  70 #define DSI_TIMING1                     DSI_REG(0x0058)
  71 #define DSI_TIMING2                     DSI_REG(0x005C)
  72 #define DSI_VM_TIMING1                  DSI_REG(0x0060)
  73 #define DSI_VM_TIMING2                  DSI_REG(0x0064)
  74 #define DSI_VM_TIMING3                  DSI_REG(0x0068)
  75 #define DSI_CLK_TIMING                  DSI_REG(0x006C)
  76 #define DSI_TX_FIFO_VC_SIZE             DSI_REG(0x0070)
  77 #define DSI_RX_FIFO_VC_SIZE             DSI_REG(0x0074)
  78 #define DSI_COMPLEXIO_CFG2              DSI_REG(0x0078)
  79 #define DSI_RX_FIFO_VC_FULLNESS         DSI_REG(0x007C)
  80 #define DSI_VM_TIMING4                  DSI_REG(0x0080)
  81 #define DSI_TX_FIFO_VC_EMPTINESS        DSI_REG(0x0084)
  82 #define DSI_VM_TIMING5                  DSI_REG(0x0088)
  83 #define DSI_VM_TIMING6                  DSI_REG(0x008C)
  84 #define DSI_VM_TIMING7                  DSI_REG(0x0090)
  85 #define DSI_STOPCLK_TIMING              DSI_REG(0x0094)
  86 #define DSI_VC_CTRL(n)                  DSI_REG(0x0100 + (n * 0x20))
  87 #define DSI_VC_TE(n)                    DSI_REG(0x0104 + (n * 0x20))
  88 #define DSI_VC_LONG_PACKET_HEADER(n)    DSI_REG(0x0108 + (n * 0x20))
  89 #define DSI_VC_LONG_PACKET_PAYLOAD(n)   DSI_REG(0x010C + (n * 0x20))
  90 #define DSI_VC_SHORT_PACKET_HEADER(n)   DSI_REG(0x0110 + (n * 0x20))
  91 #define DSI_VC_IRQSTATUS(n)             DSI_REG(0x0118 + (n * 0x20))
  92 #define DSI_VC_IRQENABLE(n)             DSI_REG(0x011C + (n * 0x20))
  93
  94 /* DSIPHY_SCP */
  95
  96 #define DSI_DSIPHY_CFG0                 DSI_REG(0x200 + 0x0000)
  97 #define DSI_DSIPHY_CFG1                 DSI_REG(0x200 + 0x0004)
  98 #define DSI_DSIPHY_CFG2                 DSI_REG(0x200 + 0x0008)
  99 #define DSI_DSIPHY_CFG5                 DSI_REG(0x200 + 0x0014)
 100 #define DSI_DSIPHY_CFG10                DSI_REG(0x200 + 0x0028)
 101
 102 /* DSI_PLL_CTRL_SCP */
 103
 104 #define DSI_PLL_CONTROL                 DSI_REG(0x300 + 0x0000)
 105 #define DSI_PLL_STATUS                  DSI_REG(0x300 + 0x0004)
 106 #define DSI_PLL_GO                      DSI_REG(0x300 + 0x0008)
 107 #define DSI_PLL_CONFIGURATION1          DSI_REG(0x300 + 0x000C)
 108 #define DSI_PLL_CONFIGURATION2          DSI_REG(0x300 + 0x0010)
 109
 110 #define REG_GET(dsidev, idx, start, end) \
 111         FLD_GET(dsi_read_reg(dsidev, idx), start, end)
 112
 113 #define REG_FLD_MOD(dsidev, idx, val, start, end) \
 114         dsi_write_reg(dsidev, idx, FLD_MOD(dsi_read_reg(dsidev, idx), val, start, end))
 115
 116 /* Global interrupts */
 117 #define DSI_IRQ_VC0             (1 << 0)
 118 #define DSI_IRQ_VC1             (1 << 1)
 119 #define DSI_IRQ_VC2             (1 << 2)
 120 #define DSI_IRQ_VC3             (1 << 3)
 121 #define DSI_IRQ_WAKEUP          (1 << 4)
 122 #define DSI_IRQ_RESYNC          (1 << 5)
 123 #define DSI_IRQ_PLL_LOCK        (1 << 7)
 124 #define DSI_IRQ_PLL_UNLOCK      (1 << 8)
 125 #define DSI_IRQ_PLL_RECALL      (1 << 9)
 126 #define DSI_IRQ_COMPLEXIO_ERR   (1 << 10)
 127 #define DSI_IRQ_HS_TX_TIMEOUT   (1 << 14)
 128 #define DSI_IRQ_LP_RX_TIMEOUT   (1 << 15)
 129 #define DSI_IRQ_TE_TRIGGER      (1 << 16)
 130 #define DSI_IRQ_ACK_TRIGGER     (1 << 17)
 131 #define DSI_IRQ_SYNC_LOST       (1 << 18)
 132 #define DSI_IRQ_LDO_POWER_GOOD  (1 << 19)
 133 #define DSI_IRQ_TA_TIMEOUT      (1 << 20)
 134 #define DSI_IRQ_ERROR_MASK \
 135         (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
 136         DSI_IRQ_TA_TIMEOUT | DSI_IRQ_SYNC_LOST)
 137 #define DSI_IRQ_CHANNEL_MASK    0xf
 138
 139 /* Virtual channel interrupts */
 140 #define DSI_VC_IRQ_CS           (1 << 0)
 141 #define DSI_VC_IRQ_ECC_CORR     (1 << 1)
 142 #define DSI_VC_IRQ_PACKET_SENT  (1 << 2)
 143 #define DSI_VC_IRQ_FIFO_TX_OVF  (1 << 3)
 144 #define DSI_VC_IRQ_FIFO_RX_OVF  (1 << 4)
 145 #define DSI_VC_IRQ_BTA          (1 << 5)
 146 #define DSI_VC_IRQ_ECC_NO_CORR  (1 << 6)
 147 #define DSI_VC_IRQ_FIFO_TX_UDF  (1 << 7)
 148 #define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
 149 #define DSI_VC_IRQ_ERROR_MASK \
 150         (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
 151         DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
 152         DSI_VC_IRQ_FIFO_TX_UDF)
 153
 154 /* ComplexIO interrupts */
 155 #define DSI_CIO_IRQ_ERRSYNCESC1         (1 << 0)
 156 #define DSI_CIO_IRQ_ERRSYNCESC2         (1 << 1)
 157 #define DSI_CIO_IRQ_ERRSYNCESC3         (1 << 2)
 158 #define DSI_CIO_IRQ_ERRSYNCESC4         (1 << 3)
 159 #define DSI_CIO_IRQ_ERRSYNCESC5         (1 << 4)
 160 #define DSI_CIO_IRQ_ERRESC1             (1 << 5)
 161 #define DSI_CIO_IRQ_ERRESC2             (1 << 6)
 162 #define DSI_CIO_IRQ_ERRESC3             (1 << 7)
 163 #define DSI_CIO_IRQ_ERRESC4             (1 << 8)
 164 #define DSI_CIO_IRQ_ERRESC5             (1 << 9)
 165 #define DSI_CIO_IRQ_ERRCONTROL1         (1 << 10)
 166 #define DSI_CIO_IRQ_ERRCONTROL2         (1 << 11)
 167 #define DSI_CIO_IRQ_ERRCONTROL3         (1 << 12)
 168 #define DSI_CIO_IRQ_ERRCONTROL4         (1 << 13)
 169 #define DSI_CIO_IRQ_ERRCONTROL5         (1 << 14)
 170 #define DSI_CIO_IRQ_STATEULPS1          (1 << 15)
 171 #define DSI_CIO_IRQ_STATEULPS2          (1 << 16)
 172 #define DSI_CIO_IRQ_STATEULPS3          (1 << 17)
 173 #define DSI_CIO_IRQ_STATEULPS4          (1 << 18)
 174 #define DSI_CIO_IRQ_STATEULPS5          (1 << 19)
 175 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_1  (1 << 20)
 176 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_1  (1 << 21)
 177 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_2  (1 << 22)
 178 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_2  (1 << 23)
 179 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_3  (1 << 24)
 180 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_3  (1 << 25)
 181 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_4  (1 << 26)
 182 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_4  (1 << 27)
 183 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_5  (1 << 28)
 184 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_5  (1 << 29)
 185 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0  (1 << 30)
 186 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1  (1 << 31)
 187 #define DSI_CIO_IRQ_ERROR_MASK \
 188         (DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \
 189          DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRSYNCESC4 | \
 190          DSI_CIO_IRQ_ERRSYNCESC5 | \
 191          DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \
 192          DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRESC4 | \
 193          DSI_CIO_IRQ_ERRESC5 | \
 194          DSI_CIO_IRQ_ERRCONTROL1 | DSI_CIO_IRQ_ERRCONTROL2 | \
 195          DSI_CIO_IRQ_ERRCONTROL3 | DSI_CIO_IRQ_ERRCONTROL4 | \
 196          DSI_CIO_IRQ_ERRCONTROL5 | \
 197          DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \
 198          DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \
 199          DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3 | \
 200          DSI_CIO_IRQ_ERRCONTENTIONLP0_4 | DSI_CIO_IRQ_ERRCONTENTIONLP1_4 | \
 201          DSI_CIO_IRQ_ERRCONTENTIONLP0_5 | DSI_CIO_IRQ_ERRCONTENTIONLP1_5)
 202
 203 typedef void (*omap_dsi_isr_t) (void *arg, u32 mask);
 204
 205 #define DSI_MAX_NR_ISRS                2
 206 #define DSI_MAX_NR_LANES        5
 207
 208 enum dsi_lane_function {
 209         DSI_LANE_UNUSED = 0,
 210         DSI_LANE_CLK,
 211         DSI_LANE_DATA1,
 212         DSI_LANE_DATA2,
 213         DSI_LANE_DATA3,
 214         DSI_LANE_DATA4,
 215 };
 216
 217 struct dsi_lane_config {
 218         enum dsi_lane_function function;
 219         u8 polarity;
 220 };
 221
 222 struct dsi_isr_data {
 223         omap_dsi_isr_t  isr;
 224         void            *arg;
 225         u32             mask;
 226 };
 227
 228 enum fifo_size {
 229         DSI_FIFO_SIZE_0         = 0,
 230         DSI_FIFO_SIZE_32        = 1,
 231         DSI_FIFO_SIZE_64        = 2,
 232         DSI_FIFO_SIZE_96        = 3,
 233         DSI_FIFO_SIZE_128       = 4,
 234 };
 235
 236 enum dsi_vc_source {
 237         DSI_VC_SOURCE_L4 = 0,
 238         DSI_VC_SOURCE_VP,
 239 };
 240
 241 struct dsi_irq_stats {
 242         unsigned long last_reset;
 243         unsigned irq_count;
 244         unsigned dsi_irqs[32];
 245         unsigned vc_irqs[4][32];
 246         unsigned cio_irqs[32];
 247 };
 248
 249 struct dsi_isr_tables {
 250         struct dsi_isr_data isr_table[DSI_MAX_NR_ISRS];
 251         struct dsi_isr_data isr_table_vc[4][DSI_MAX_NR_ISRS];
 252         struct dsi_isr_data isr_table_cio[DSI_MAX_NR_ISRS];
 253 };
 254
 255 struct dsi_data {
 256         struct platform_device *pdev;
 257         void __iomem    *base;
 258
 259         int irq;
 260
 261         struct clk *dss_clk;
 262         struct clk *sys_clk;
 263
 264         int (*enable_pads)(int dsi_id, unsigned lane_mask);
 265         void (*disable_pads)(int dsi_id, unsigned lane_mask);
 266
 267         struct dsi_clock_info current_cinfo;
 268
 269         bool vdds_dsi_enabled;
 270         struct regulator *vdds_dsi_reg;
 271
 272         struct {
 273                 enum dsi_vc_source source;
 274                 struct omap_dss_device *dssdev;
 275                 enum fifo_size fifo_size;
 276                 int vc_id;
 277         } vc[4];
 278
 279         struct mutex lock;
 280         struct semaphore bus_lock;
 281
 282         unsigned pll_locked;
 283
 284         spinlock_t irq_lock;
 285         struct dsi_isr_tables isr_tables;
 286         /* space for a copy used by the interrupt handler */
 287         struct dsi_isr_tables isr_tables_copy;
 288
 289         int update_channel;
 290 #ifdef DEBUG
 291         unsigned update_bytes;
 292 #endif
 293
 294         bool te_enabled;
 295         bool ulps_enabled;
 296
 297         void (*framedone_callback)(int, void *);
 298         void *framedone_data;
 299
 300         struct delayed_work framedone_timeout_work;
 301
 302 #ifdef DSI_CATCH_MISSING_TE
 303         struct timer_list te_timer;
 304 #endif
 305
 306         unsigned long cache_req_pck;
 307         unsigned long cache_clk_freq;
 308         struct dsi_clock_info cache_cinfo;
 309
 310         u32             errors;
 311         spinlock_t      errors_lock;
 312 #ifdef DEBUG
 313         ktime_t perf_setup_time;
 314         ktime_t perf_start_time;
 315 #endif
 316         int debug_read;
 317         int debug_write;
 318
 319 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
 320         spinlock_t irq_stats_lock;
 321         struct dsi_irq_stats irq_stats;
 322 #endif
 323         /* DSI PLL Parameter Ranges */
 324         unsigned long regm_max, regn_max;
 325         unsigned long  regm_dispc_max, regm_dsi_max;
 326         unsigned long  fint_min, fint_max;
 327         unsigned long lpdiv_max;
 328
 329         unsigned num_lanes_supported;
 330
 331         struct dsi_lane_config lanes[DSI_MAX_NR_LANES];
 332         unsigned num_lanes_used;
 333
 334         unsigned scp_clk_refcount;
 335 };
 336
 337 struct dsi_packet_sent_handler_data {
 338         struct platform_device *dsidev;
 339         struct completion *completion;
 340 };
 341
 342 static struct platform_device *dsi_pdev_map[MAX_NUM_DSI];
 343
 344 #ifdef DEBUG
 345 static bool dsi_perf;
 346 module_param(dsi_perf, bool, 0644);
 347 #endif
 348
 349 static inline struct dsi_data *dsi_get_dsidrv_data(struct platform_device *dsidev)
 350 {
 351         return dev_get_drvdata(&dsidev->dev);
 352 }
 353
 354 static inline struct platform_device *dsi_get_dsidev_from_dssdev(struct omap_dss_device *dssdev)
 355 {
 356         return dsi_pdev_map[dssdev->phy.dsi.module];
 357 }
 358
 359 struct platform_device *dsi_get_dsidev_from_id(int module)
 360 {
 361         return dsi_pdev_map[module];
 362 }
 363
 364 static inline int dsi_get_dsidev_id(struct platform_device *dsidev)
 365 {
 366         return dsidev->id;
 367 }
 368
 369 static inline void dsi_write_reg(struct platform_device *dsidev,
 370                 const struct dsi_reg idx, u32 val)
 371 {
 372         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 373
 374         __raw_writel(val, dsi->base + idx.idx);
 375 }
 376
 377 static inline u32 dsi_read_reg(struct platform_device *dsidev,
 378                 const struct dsi_reg idx)
 379 {
 380         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 381
 382         return __raw_readl(dsi->base + idx.idx);
 383 }
 384
 385 void dsi_bus_lock(struct omap_dss_device *dssdev)
 386 {
 387         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
 388         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 389
 390         down(&dsi->bus_lock);
 391 }
 392 EXPORT_SYMBOL(dsi_bus_lock);
 393
 394 void dsi_bus_unlock(struct omap_dss_device *dssdev)
 395 {
 396         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
 397         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 398
 399         up(&dsi->bus_lock);
 400 }
 401 EXPORT_SYMBOL(dsi_bus_unlock);
 402
 403 static bool dsi_bus_is_locked(struct platform_device *dsidev)
 404 {
 405         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 406
 407         return dsi->bus_lock.count == 0;
 408 }
 409
 410 static void dsi_completion_handler(void *data, u32 mask)
 411 {
 412         complete((struct completion *)data);
 413 }
 414
 415 static inline int wait_for_bit_change(struct platform_device *dsidev,
 416                 const struct dsi_reg idx, int bitnum, int value)
 417 {
 418         unsigned long timeout;
 419         ktime_t wait;
 420         int t;
 421
 422         /* first busyloop to see if the bit changes right away */
 423         t = 100;
 424         while (t-- > 0) {
 425                 if (REG_GET(dsidev, idx, bitnum, bitnum) == value)
 426                         return value;
 427         }
 428
 429         /* then loop for 500ms, sleeping for 1ms in between */
 430         timeout = jiffies + msecs_to_jiffies(500);
 431         while (time_before(jiffies, timeout)) {
 432                 if (REG_GET(dsidev, idx, bitnum, bitnum) == value)
 433                         return value;
 434
 435                 wait = ns_to_ktime(1000 * 1000);
 436                 set_current_state(TASK_UNINTERRUPTIBLE);
 437                 schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
 438         }
 439
 440         return !value;
 441 }
 442
 443 u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)
 444 {
 445         switch (fmt) {
 446         case OMAP_DSS_DSI_FMT_RGB888:
 447         case OMAP_DSS_DSI_FMT_RGB666:
 448                 return 24;
 449         case OMAP_DSS_DSI_FMT_RGB666_PACKED:
 450                 return 18;
 451         case OMAP_DSS_DSI_FMT_RGB565:
 452                 return 16;
 453         default:
 454                 BUG();
 455         }
 456 }
 457
 458 #ifdef DEBUG
 459 static void dsi_perf_mark_setup(struct platform_device *dsidev)
 460 {
 461         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 462         dsi->perf_setup_time = ktime_get();
 463 }
 464
 465 static void dsi_perf_mark_start(struct platform_device *dsidev)
 466 {
 467         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 468         dsi->perf_start_time = ktime_get();
 469 }
 470
 471 static void dsi_perf_show(struct platform_device *dsidev, const char *name)
 472 {
 473         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 474         ktime_t t, setup_time, trans_time;
 475         u32 total_bytes;
 476         u32 setup_us, trans_us, total_us;
 477
 478         if (!dsi_perf)
 479                 return;
 480
 481         t = ktime_get();
 482
 483         setup_time = ktime_sub(dsi->perf_start_time, dsi->perf_setup_time);
 484         setup_us = (u32)ktime_to_us(setup_time);
 485         if (setup_us == 0)
 486                 setup_us = 1;
 487
 488         trans_time = ktime_sub(t, dsi->perf_start_time);
 489         trans_us = (u32)ktime_to_us(trans_time);
 490         if (trans_us == 0)
 491                 trans_us = 1;
 492
 493         total_us = setup_us + trans_us;
 494
 495         total_bytes = dsi->update_bytes;
 496
 497         printk(KERN_INFO "DSI(%s): %u us + %u us = %u us (%uHz), "
 498                         "%u bytes, %u kbytes/sec\n",
 499                         name,
 500                         setup_us,
 501                         trans_us,
 502                         total_us,
 503                         1000*1000 / total_us,
 504                         total_bytes,
 505                         total_bytes * 1000 / total_us);
 506 }
 507 #else
 508 static inline void dsi_perf_mark_setup(struct platform_device *dsidev)
 509 {
 510 }
 511
 512 static inline void dsi_perf_mark_start(struct platform_device *dsidev)
 513 {
 514 }
 515
 516 static inline void dsi_perf_show(struct platform_device *dsidev,
 517                 const char *name)
 518 {
 519 }
 520 #endif
 521
 522 static void print_irq_status(u32 status)
 523 {
 524         if (status == 0)
 525                 return;
 526
 527 #ifndef VERBOSE_IRQ
 528         if ((status & ~DSI_IRQ_CHANNEL_MASK) == 0)
 529                 return;
 530 #endif
 531         printk(KERN_DEBUG "DSI IRQ: 0x%x: ", status);
 532
 533 #define PIS(x) \
 534         if (status & DSI_IRQ_##x) \
 535                 printk(#x " ");
 536 #ifdef VERBOSE_IRQ
 537         PIS(VC0);
 538         PIS(VC1);
 539         PIS(VC2);
 540         PIS(VC3);
 541 #endif
 542         PIS(WAKEUP);
 543         PIS(RESYNC);
 544         PIS(PLL_LOCK);
 545         PIS(PLL_UNLOCK);
 546         PIS(PLL_RECALL);
 547         PIS(COMPLEXIO_ERR);
 548         PIS(HS_TX_TIMEOUT);
 549         PIS(LP_RX_TIMEOUT);
 550         PIS(TE_TRIGGER);
 551         PIS(ACK_TRIGGER);
 552         PIS(SYNC_LOST);
 553         PIS(LDO_POWER_GOOD);
 554         PIS(TA_TIMEOUT);
 555 #undef PIS
 556
 557         printk("\n");
 558 }
 559
 560 static void print_irq_status_vc(int channel, u32 status)
 561 {
 562         if (status == 0)
 563                 return;
 564
 565 #ifndef VERBOSE_IRQ
 566         if ((status & ~DSI_VC_IRQ_PACKET_SENT) == 0)
 567                 return;
 568 #endif
 569         printk(KERN_DEBUG "DSI VC(%d) IRQ 0x%x: ", channel, status);
 570
 571 #define PIS(x) \
 572         if (status & DSI_VC_IRQ_##x) \
 573                 printk(#x " ");
 574         PIS(CS);
 575         PIS(ECC_CORR);
 576 #ifdef VERBOSE_IRQ
 577         PIS(PACKET_SENT);
 578 #endif
 579         PIS(FIFO_TX_OVF);
 580         PIS(FIFO_RX_OVF);
 581         PIS(BTA);
 582         PIS(ECC_NO_CORR);
 583         PIS(FIFO_TX_UDF);
 584         PIS(PP_BUSY_CHANGE);
 585 #undef PIS
 586         printk("\n");
 587 }
 588
 589 static void print_irq_status_cio(u32 status)
 590 {
 591         if (status == 0)
 592                 return;
 593
 594         printk(KERN_DEBUG "DSI CIO IRQ 0x%x: ", status);
 595
 596 #define PIS(x) \
 597         if (status & DSI_CIO_IRQ_##x) \
 598                 printk(#x " ");
 599         PIS(ERRSYNCESC1);
 600         PIS(ERRSYNCESC2);
 601         PIS(ERRSYNCESC3);
 602         PIS(ERRESC1);
 603         PIS(ERRESC2);
 604         PIS(ERRESC3);
 605         PIS(ERRCONTROL1);
 606         PIS(ERRCONTROL2);
 607         PIS(ERRCONTROL3);
 608         PIS(STATEULPS1);
 609         PIS(STATEULPS2);
 610         PIS(STATEULPS3);
 611         PIS(ERRCONTENTIONLP0_1);
 612         PIS(ERRCONTENTIONLP1_1);
 613         PIS(ERRCONTENTIONLP0_2);
 614         PIS(ERRCONTENTIONLP1_2);
 615         PIS(ERRCONTENTIONLP0_3);
 616         PIS(ERRCONTENTIONLP1_3);
 617         PIS(ULPSACTIVENOT_ALL0);
 618         PIS(ULPSACTIVENOT_ALL1);
 619 #undef PIS
 620
 621         printk("\n");
 622 }
 623
 624 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
 625 static void dsi_collect_irq_stats(struct platform_device *dsidev, u32 irqstatus,
 626                 u32 *vcstatus, u32 ciostatus)
 627 {
 628         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 629         int i;
 630
 631         spin_lock(&dsi->irq_stats_lock);
 632
 633         dsi->irq_stats.irq_count++;
 634         dss_collect_irq_stats(irqstatus, dsi->irq_stats.dsi_irqs);
 635
 636         for (i = 0; i < 4; ++i)
 637                 dss_collect_irq_stats(vcstatus[i], dsi->irq_stats.vc_irqs[i]);
 638
 639         dss_collect_irq_stats(ciostatus, dsi->irq_stats.cio_irqs);
 640
 641         spin_unlock(&dsi->irq_stats_lock);
 642 }
 643 #else
 644 #define dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus)
 645 #endif
 646
 647 static int debug_irq;
 648
 649 static void dsi_handle_irq_errors(struct platform_device *dsidev, u32 irqstatus,
 650                 u32 *vcstatus, u32 ciostatus)
 651 {
 652         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 653         int i;
 654
 655         if (irqstatus & DSI_IRQ_ERROR_MASK) {
 656                 DSSERR("DSI error, irqstatus %x\n", irqstatus);
 657                 print_irq_status(irqstatus);
 658                 spin_lock(&dsi->errors_lock);
 659                 dsi->errors |= irqstatus & DSI_IRQ_ERROR_MASK;
 660                 spin_unlock(&dsi->errors_lock);
 661         } else if (debug_irq) {
 662                 print_irq_status(irqstatus);
 663         }
 664
 665         for (i = 0; i < 4; ++i) {
 666                 if (vcstatus[i] & DSI_VC_IRQ_ERROR_MASK) {
 667                         DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
 668                                        i, vcstatus[i]);
 669                         print_irq_status_vc(i, vcstatus[i]);
 670                 } else if (debug_irq) {
 671                         print_irq_status_vc(i, vcstatus[i]);
 672                 }
 673         }
 674
 675         if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) {
 676                 DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus);
 677                 print_irq_status_cio(ciostatus);
 678         } else if (debug_irq) {
 679                 print_irq_status_cio(ciostatus);
 680         }
 681 }
 682
 683 static void dsi_call_isrs(struct dsi_isr_data *isr_array,
 684                 unsigned isr_array_size, u32 irqstatus)
 685 {
 686         struct dsi_isr_data *isr_data;
 687         int i;
 688
 689         for (i = 0; i < isr_array_size; i++) {
 690                 isr_data = &isr_array[i];
 691                 if (isr_data->isr && isr_data->mask & irqstatus)
 692                         isr_data->isr(isr_data->arg, irqstatus);
 693         }
 694 }
 695
 696 static void dsi_handle_isrs(struct dsi_isr_tables *isr_tables,
 697                 u32 irqstatus, u32 *vcstatus, u32 ciostatus)
 698 {
 699         int i;
 700
 701         dsi_call_isrs(isr_tables->isr_table,
 702                         ARRAY_SIZE(isr_tables->isr_table),
 703                         irqstatus);
 704
 705         for (i = 0; i < 4; ++i) {
 706                 if (vcstatus[i] == 0)
 707                         continue;
 708                 dsi_call_isrs(isr_tables->isr_table_vc[i],
 709                                 ARRAY_SIZE(isr_tables->isr_table_vc[i]),
 710                                 vcstatus[i]);
 711         }
 712
 713         if (ciostatus != 0)
 714                 dsi_call_isrs(isr_tables->isr_table_cio,
 715                                 ARRAY_SIZE(isr_tables->isr_table_cio),
 716                                 ciostatus);
 717 }
 718
 719 static irqreturn_t omap_dsi_irq_handler(int irq, void *arg)
 720 {
 721         struct platform_device *dsidev;
 722         struct dsi_data *dsi;
 723         u32 irqstatus, vcstatus[4], ciostatus;
 724         int i;
 725
 726         dsidev = (struct platform_device *) arg;
 727         dsi = dsi_get_dsidrv_data(dsidev);
 728
 729         spin_lock(&dsi->irq_lock);
 730
 731         irqstatus = dsi_read_reg(dsidev, DSI_IRQSTATUS);
 732
 733         /* IRQ is not for us */
 734         if (!irqstatus) {
 735                 spin_unlock(&dsi->irq_lock);
 736                 return IRQ_NONE;
 737         }
 738
 739         dsi_write_reg(dsidev, DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
 740         /* flush posted write */
 741         dsi_read_reg(dsidev, DSI_IRQSTATUS);
 742
 743         for (i = 0; i < 4; ++i) {
 744                 if ((irqstatus & (1 << i)) == 0) {
 745                         vcstatus[i] = 0;
 746                         continue;
 747                 }
 748
 749                 vcstatus[i] = dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
 750
 751                 dsi_write_reg(dsidev, DSI_VC_IRQSTATUS(i), vcstatus[i]);
 752                 /* flush posted write */
 753                 dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
 754         }
 755
 756         if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) {
 757                 ciostatus = dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
 758
 759                 dsi_write_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
 760                 /* flush posted write */
 761                 dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
 762         } else {
 763                 ciostatus = 0;
 764         }
 765
 766 #ifdef DSI_CATCH_MISSING_TE
 767         if (irqstatus & DSI_IRQ_TE_TRIGGER)
 768                 del_timer(&dsi->te_timer);
 769 #endif
 770
 771         /* make a copy and unlock, so that isrs can unregister
 772          * themselves */
 773         memcpy(&dsi->isr_tables_copy, &dsi->isr_tables,
 774                 sizeof(dsi->isr_tables));
 775
 776         spin_unlock(&dsi->irq_lock);
 777
 778         dsi_handle_isrs(&dsi->isr_tables_copy, irqstatus, vcstatus, ciostatus);
 779
 780         dsi_handle_irq_errors(dsidev, irqstatus, vcstatus, ciostatus);
 781
 782         dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus);
 783
 784         return IRQ_HANDLED;
 785 }
 786
 787 /* dsi->irq_lock has to be locked by the caller */
 788 static void _omap_dsi_configure_irqs(struct platform_device *dsidev,
 789                 struct dsi_isr_data *isr_array,
 790                 unsigned isr_array_size, u32 default_mask,
 791                 const struct dsi_reg enable_reg,
 792                 const struct dsi_reg status_reg)
 793 {
 794         struct dsi_isr_data *isr_data;
 795         u32 mask;
 796         u32 old_mask;
 797         int i;
 798
 799         mask = default_mask;
 800
 801         for (i = 0; i < isr_array_size; i++) {
 802                 isr_data = &isr_array[i];
 803
 804                 if (isr_data->isr == NULL)
 805                         continue;
 806
 807                 mask |= isr_data->mask;
 808         }
 809
 810         old_mask = dsi_read_reg(dsidev, enable_reg);
 811         /* clear the irqstatus for newly enabled irqs */
 812         dsi_write_reg(dsidev, status_reg, (mask ^ old_mask) & mask);
 813         dsi_write_reg(dsidev, enable_reg, mask);
 814
 815         /* flush posted writes */
 816         dsi_read_reg(dsidev, enable_reg);
 817         dsi_read_reg(dsidev, status_reg);
 818 }
 819
 820 /* dsi->irq_lock has to be locked by the caller */
 821 static void _omap_dsi_set_irqs(struct platform_device *dsidev)
 822 {
 823         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 824         u32 mask = DSI_IRQ_ERROR_MASK;
 825 #ifdef DSI_CATCH_MISSING_TE
 826         mask |= DSI_IRQ_TE_TRIGGER;
 827 #endif
 828         _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table,
 829                         ARRAY_SIZE(dsi->isr_tables.isr_table), mask,
 830                         DSI_IRQENABLE, DSI_IRQSTATUS);
 831 }
 832
 833 /* dsi->irq_lock has to be locked by the caller */
 834 static void _omap_dsi_set_irqs_vc(struct platform_device *dsidev, int vc)
 835 {
 836         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 837
 838         _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_vc[vc],
 839                         ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc]),
 840                         DSI_VC_IRQ_ERROR_MASK,
 841                         DSI_VC_IRQENABLE(vc), DSI_VC_IRQSTATUS(vc));
 842 }
 843
 844 /* dsi->irq_lock has to be locked by the caller */
 845 static void _omap_dsi_set_irqs_cio(struct platform_device *dsidev)
 846 {
 847         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 848
 849         _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_cio,
 850                         ARRAY_SIZE(dsi->isr_tables.isr_table_cio),
 851                         DSI_CIO_IRQ_ERROR_MASK,
 852                         DSI_COMPLEXIO_IRQ_ENABLE, DSI_COMPLEXIO_IRQ_STATUS);
 853 }
 854
 855 static void _dsi_initialize_irq(struct platform_device *dsidev)
 856 {
 857         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 858         unsigned long flags;
 859         int vc;
 860
 861         spin_lock_irqsave(&dsi->irq_lock, flags);
 862
 863         memset(&dsi->isr_tables, 0, sizeof(dsi->isr_tables));
 864
 865         _omap_dsi_set_irqs(dsidev);
 866         for (vc = 0; vc < 4; ++vc)
 867                 _omap_dsi_set_irqs_vc(dsidev, vc);
 868         _omap_dsi_set_irqs_cio(dsidev);
 869
 870         spin_unlock_irqrestore(&dsi->irq_lock, flags);
 871 }
 872
 873 static int _dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
 874                 struct dsi_isr_data *isr_array, unsigned isr_array_size)
 875 {
 876         struct dsi_isr_data *isr_data;
 877         int free_idx;
 878         int i;
 879
 880         BUG_ON(isr == NULL);
 881
 882         /* check for duplicate entry and find a free slot */
 883         free_idx = -1;
 884         for (i = 0; i < isr_array_size; i++) {
 885                 isr_data = &isr_array[i];
 886
 887                 if (isr_data->isr == isr && isr_data->arg == arg &&
 888                                 isr_data->mask == mask) {
 889                         return -EINVAL;
 890                 }
 891
 892                 if (isr_data->isr == NULL && free_idx == -1)
 893                         free_idx = i;
 894         }
 895
 896         if (free_idx == -1)
 897                 return -EBUSY;
 898
 899         isr_data = &isr_array[free_idx];
 900         isr_data->isr = isr;
 901         isr_data->arg = arg;
 902         isr_data->mask = mask;
 903
 904         return 0;
 905 }
 906
 907 static int _dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
 908                 struct dsi_isr_data *isr_array, unsigned isr_array_size)
 909 {
 910         struct dsi_isr_data *isr_data;
 911         int i;
 912
 913         for (i = 0; i < isr_array_size; i++) {
 914                 isr_data = &isr_array[i];
 915                 if (isr_data->isr != isr || isr_data->arg != arg ||
 916                                 isr_data->mask != mask)
 917                         continue;
 918
 919                 isr_data->isr = NULL;
 920                 isr_data->arg = NULL;
 921                 isr_data->mask = 0;
 922
 923                 return 0;
 924         }
 925
 926         return -EINVAL;
 927 }
 928
 929 static int dsi_register_isr(struct platform_device *dsidev, omap_dsi_isr_t isr,
 930                 void *arg, u32 mask)
 931 {
 932         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 933         unsigned long flags;
 934         int r;
 935
 936         spin_lock_irqsave(&dsi->irq_lock, flags);
 937
 938         r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table,
 939                         ARRAY_SIZE(dsi->isr_tables.isr_table));
 940
 941         if (r == 0)
 942                 _omap_dsi_set_irqs(dsidev);
 943
 944         spin_unlock_irqrestore(&dsi->irq_lock, flags);
 945
 946         return r;
 947 }
 948
 949 static int dsi_unregister_isr(struct platform_device *dsidev,
 950                 omap_dsi_isr_t isr, void *arg, u32 mask)
 951 {
 952         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 953         unsigned long flags;
 954         int r;
 955
 956         spin_lock_irqsave(&dsi->irq_lock, flags);
 957
 958         r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table,
 959                         ARRAY_SIZE(dsi->isr_tables.isr_table));
 960
 961         if (r == 0)
 962                 _omap_dsi_set_irqs(dsidev);
 963
 964         spin_unlock_irqrestore(&dsi->irq_lock, flags);
 965
 966         return r;
 967 }
 968
 969 static int dsi_register_isr_vc(struct platform_device *dsidev, int channel,
 970                 omap_dsi_isr_t isr, void *arg, u32 mask)
 971 {
 972         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 973         unsigned long flags;
 974         int r;
 975
 976         spin_lock_irqsave(&dsi->irq_lock, flags);
 977
 978         r = _dsi_register_isr(isr, arg, mask,
 979                         dsi->isr_tables.isr_table_vc[channel],
 980                         ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
 981
 982         if (r == 0)
 983                 _omap_dsi_set_irqs_vc(dsidev, channel);
 984
 985         spin_unlock_irqrestore(&dsi->irq_lock, flags);
 986
 987         return r;
 988 }
 989
 990 static int dsi_unregister_isr_vc(struct platform_device *dsidev, int channel,
 991                 omap_dsi_isr_t isr, void *arg, u32 mask)
 992 {
 993         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 994         unsigned long flags;
 995         int r;
 996
 997         spin_lock_irqsave(&dsi->irq_lock, flags);
 998
 999         r = _dsi_unregister_isr(isr, arg, mask,
1000                         dsi->isr_tables.isr_table_vc[channel],
1001                         ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
1002
1003         if (r == 0)
1004                 _omap_dsi_set_irqs_vc(dsidev, channel);
1005
1006         spin_unlock_irqrestore(&dsi->irq_lock, flags);
1007
1008         return r;
1009 }
1010
1011 static int dsi_register_isr_cio(struct platform_device *dsidev,
1012                 omap_dsi_isr_t isr, void *arg, u32 mask)
1013 {
1014         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1015         unsigned long flags;
1016         int r;
1017
1018         spin_lock_irqsave(&dsi->irq_lock, flags);
1019
1020         r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
1021                         ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1022
1023         if (r == 0)
1024                 _omap_dsi_set_irqs_cio(dsidev);
1025
1026         spin_unlock_irqrestore(&dsi->irq_lock, flags);
1027
1028         return r;
1029 }
1030
1031 static int dsi_unregister_isr_cio(struct platform_device *dsidev,
1032                 omap_dsi_isr_t isr, void *arg, u32 mask)
1033 {
1034         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1035         unsigned long flags;
1036         int r;
1037
1038         spin_lock_irqsave(&dsi->irq_lock, flags);
1039
1040         r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
1041                         ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1042
1043         if (r == 0)
1044                 _omap_dsi_set_irqs_cio(dsidev);
1045
1046         spin_unlock_irqrestore(&dsi->irq_lock, flags);
1047
1048         return r;
1049 }
1050
1051 static u32 dsi_get_errors(struct platform_device *dsidev)
1052 {
1053         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1054         unsigned long flags;
1055         u32 e;
1056         spin_lock_irqsave(&dsi->errors_lock, flags);
1057         e = dsi->errors;
1058         dsi->errors = 0;
1059         spin_unlock_irqrestore(&dsi->errors_lock, flags);
1060         return e;
1061 }
1062
1063 int dsi_runtime_get(struct platform_device *dsidev)
1064 {
1065         int r;
1066         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1067
1068         DSSDBG("dsi_runtime_get\n");
1069
1070         r = pm_runtime_get_sync(&dsi->pdev->dev);
1071         WARN_ON(r < 0);
1072         return r < 0 ? r : 0;
1073 }
1074
1075 void dsi_runtime_put(struct platform_device *dsidev)
1076 {
1077         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1078         int r;
1079
1080         DSSDBG("dsi_runtime_put\n");
1081
1082         r = pm_runtime_put_sync(&dsi->pdev->dev);
1083         WARN_ON(r < 0);
1084 }
1085
1086 /* source clock for DSI PLL. this could also be PCLKFREE */
1087 static inline void dsi_enable_pll_clock(struct platform_device *dsidev,
1088                 bool enable)
1089 {
1090         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1091
1092         if (enable)
1093                 clk_enable(dsi->sys_clk);
1094         else
1095                 clk_disable(dsi->sys_clk);
1096
1097         if (enable && dsi->pll_locked) {
1098                 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 1, 1) != 1)
1099                         DSSERR("cannot lock PLL when enabling clocks\n");
1100         }
1101 }
1102
1103 #ifdef DEBUG
1104 static void _dsi_print_reset_status(struct platform_device *dsidev)
1105 {
1106         u32 l;
1107         int b0, b1, b2;
1108
1109         if (!dss_debug)
1110                 return;
1111
1112         /* A dummy read using the SCP interface to any DSIPHY register is
1113          * required after DSIPHY reset to complete the reset of the DSI complex
1114          * I/O. */
1115         l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
1116
1117         printk(KERN_DEBUG "DSI resets: ");
1118
1119         l = dsi_read_reg(dsidev, DSI_PLL_STATUS);
1120         printk("PLL (%d) ", FLD_GET(l, 0, 0));
1121
1122         l = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1);
1123         printk("CIO (%d) ", FLD_GET(l, 29, 29));
1124
1125         if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) {
1126                 b0 = 28;
1127                 b1 = 27;
1128                 b2 = 26;
1129         } else {
1130                 b0 = 24;
1131                 b1 = 25;
1132                 b2 = 26;
1133         }
1134
1135         l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
1136         printk("PHY (%x%x%x, %d, %d, %d)\n",
1137                         FLD_GET(l, b0, b0),
1138                         FLD_GET(l, b1, b1),
1139                         FLD_GET(l, b2, b2),
1140                         FLD_GET(l, 29, 29),
1141                         FLD_GET(l, 30, 30),
1142                         FLD_GET(l, 31, 31));
1143 }
1144 #else
1145 #define _dsi_print_reset_status(x)
1146 #endif
1147
1148 static inline int dsi_if_enable(struct platform_device *dsidev, bool enable)
1149 {
1150         DSSDBG("dsi_if_enable(%d)\n", enable);
1151
1152         enable = enable ? 1 : 0;
1153         REG_FLD_MOD(dsidev, DSI_CTRL, enable, 0, 0); /* IF_EN */
1154
1155         if (wait_for_bit_change(dsidev, DSI_CTRL, 0, enable) != enable) {
1156                         DSSERR("Failed to set dsi_if_enable to %d\n", enable);
1157                         return -EIO;
1158         }
1159
1160         return 0;
1161 }
1162
1163 unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev)
1164 {
1165         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1166
1167         return dsi->current_cinfo.dsi_pll_hsdiv_dispc_clk;
1168 }
1169
1170 static unsigned long dsi_get_pll_hsdiv_dsi_rate(struct platform_device *dsidev)
1171 {
1172         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1173
1174         return dsi->current_cinfo.dsi_pll_hsdiv_dsi_clk;
1175 }
1176
1177 static unsigned long dsi_get_txbyteclkhs(struct platform_device *dsidev)
1178 {
1179         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1180
1181         return dsi->current_cinfo.clkin4ddr / 16;
1182 }
1183
1184 static unsigned long dsi_fclk_rate(struct platform_device *dsidev)
1185 {
1186         unsigned long r;
1187         int dsi_module = dsi_get_dsidev_id(dsidev);
1188         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1189
1190         if (dss_get_dsi_clk_source(dsi_module) == OMAP_DSS_CLK_SRC_FCK) {
1191                 /* DSI FCLK source is DSS_CLK_FCK */
1192                 r = clk_get_rate(dsi->dss_clk);
1193         } else {
1194                 /* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */
1195                 r = dsi_get_pll_hsdiv_dsi_rate(dsidev);
1196         }
1197
1198         return r;
1199 }
1200
1201 static int dsi_set_lp_clk_divisor(struct omap_dss_device *dssdev)
1202 {
1203         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
1204         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1205         unsigned long dsi_fclk;
1206         unsigned lp_clk_div;
1207         unsigned long lp_clk;
1208
1209         lp_clk_div = dssdev->clocks.dsi.lp_clk_div;
1210
1211         if (lp_clk_div == 0 || lp_clk_div > dsi->lpdiv_max)
1212                 return -EINVAL;
1213
1214         dsi_fclk = dsi_fclk_rate(dsidev);
1215
1216         lp_clk = dsi_fclk / 2 / lp_clk_div;
1217
1218         DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk);
1219         dsi->current_cinfo.lp_clk = lp_clk;
1220         dsi->current_cinfo.lp_clk_div = lp_clk_div;
1221
1222         /* LP_CLK_DIVISOR */
1223         REG_FLD_MOD(dsidev, DSI_CLK_CTRL, lp_clk_div, 12, 0);
1224
1225         /* LP_RX_SYNCHRO_ENABLE */
1226         REG_FLD_MOD(dsidev, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21);
1227
1228         return 0;
1229 }
1230
1231 static void dsi_enable_scp_clk(struct platform_device *dsidev)
1232 {
1233         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1234
1235         if (dsi->scp_clk_refcount++ == 0)
1236                 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */
1237 }
1238
1239 static void dsi_disable_scp_clk(struct platform_device *dsidev)
1240 {
1241         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1242
1243         WARN_ON(dsi->scp_clk_refcount == 0);
1244         if (--dsi->scp_clk_refcount == 0)
1245                 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */
1246 }
1247
1248 enum dsi_pll_power_state {
1249         DSI_PLL_POWER_OFF       = 0x0,
1250         DSI_PLL_POWER_ON_HSCLK  = 0x1,
1251         DSI_PLL_POWER_ON_ALL    = 0x2,
1252         DSI_PLL_POWER_ON_DIV    = 0x3,
1253 };
1254
1255 static int dsi_pll_power(struct platform_device *dsidev,
1256                 enum dsi_pll_power_state state)
1257 {
1258         int t = 0;
1259
1260         /* DSI-PLL power command 0x3 is not working */
1261         if (dss_has_feature(FEAT_DSI_PLL_PWR_BUG) &&
1262                         state == DSI_PLL_POWER_ON_DIV)
1263                 state = DSI_PLL_POWER_ON_ALL;
1264
1265         /* PLL_PWR_CMD */
1266         REG_FLD_MOD(dsidev, DSI_CLK_CTRL, state, 31, 30);
1267
1268         /* PLL_PWR_STATUS */
1269         while (FLD_GET(dsi_read_reg(dsidev, DSI_CLK_CTRL), 29, 28) != state) {
1270                 if (++t > 1000) {
1271                         DSSERR("Failed to set DSI PLL power mode to %d\n",
1272                                         state);
1273                         return -ENODEV;
1274                 }
1275                 udelay(1);
1276         }
1277
1278         return 0;
1279 }
1280
1281 /* calculate clock rates using dividers in cinfo */
1282 static int dsi_calc_clock_rates(struct omap_dss_device *dssdev,
1283                 struct dsi_clock_info *cinfo)
1284 {
1285         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
1286         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1287
1288         if (cinfo->regn == 0 || cinfo->regn > dsi->regn_max)
1289                 return -EINVAL;
1290
1291         if (cinfo->regm == 0 || cinfo->regm > dsi->regm_max)
1292                 return -EINVAL;
1293
1294         if (cinfo->regm_dispc > dsi->regm_dispc_max)
1295                 return -EINVAL;
1296
1297         if (cinfo->regm_dsi > dsi->regm_dsi_max)
1298                 return -EINVAL;
1299
1300         if (cinfo->use_sys_clk) {
1301                 cinfo->clkin = clk_get_rate(dsi->sys_clk);
1302                 /* XXX it is unclear if highfreq should be used
1303                  * with DSS_SYS_CLK source also */
1304                 cinfo->highfreq = 0;
1305         } else {
1306                 cinfo->clkin = dispc_mgr_pclk_rate(dssdev->manager->id);
1307
1308                 if (cinfo->clkin < 32000000)
1309                         cinfo->highfreq = 0;
1310                 else
1311                         cinfo->highfreq = 1;
1312         }
1313
1314         cinfo->fint = cinfo->clkin / (cinfo->regn * (cinfo->highfreq ? 2 : 1));
1315
1316         if (cinfo->fint > dsi->fint_max || cinfo->fint < dsi->fint_min)
1317                 return -EINVAL;
1318
1319         cinfo->clkin4ddr = 2 * cinfo->regm * cinfo->fint;
1320
1321         if (cinfo->clkin4ddr > 1800 * 1000 * 1000)
1322                 return -EINVAL;
1323
1324         if (cinfo->regm_dispc > 0)
1325                 cinfo->dsi_pll_hsdiv_dispc_clk =
1326                         cinfo->clkin4ddr / cinfo->regm_dispc;
1327         else
1328                 cinfo->dsi_pll_hsdiv_dispc_clk = 0;
1329
1330         if (cinfo->regm_dsi > 0)
1331                 cinfo->dsi_pll_hsdiv_dsi_clk =
1332                         cinfo->clkin4ddr / cinfo->regm_dsi;
1333         else
1334                 cinfo->dsi_pll_hsdiv_dsi_clk = 0;
1335
1336         return 0;
1337 }
1338
1339 int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev, bool is_tft,
1340                 unsigned long req_pck, struct dsi_clock_info *dsi_cinfo,
1341                 struct dispc_clock_info *dispc_cinfo)
1342 {
1343         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1344         struct dsi_clock_info cur, best;
1345         struct dispc_clock_info best_dispc;
1346         int min_fck_per_pck;
1347         int match = 0;
1348         unsigned long dss_sys_clk, max_dss_fck;
1349
1350         dss_sys_clk = clk_get_rate(dsi->sys_clk);
1351
1352         max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
1353
1354         if (req_pck == dsi->cache_req_pck &&
1355                         dsi->cache_cinfo.clkin == dss_sys_clk) {
1356                 DSSDBG("DSI clock info found from cache\n");
1357                 *dsi_cinfo = dsi->cache_cinfo;
1358                 dispc_find_clk_divs(is_tft, req_pck,
1359                         dsi_cinfo->dsi_pll_hsdiv_dispc_clk, dispc_cinfo);
1360                 return 0;
1361         }
1362
1363         min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
1364
1365         if (min_fck_per_pck &&
1366                 req_pck * min_fck_per_pck > max_dss_fck) {
1367                 DSSERR("Requested pixel clock not possible with the current "
1368                                 "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
1369                                 "the constraint off.\n");
1370                 min_fck_per_pck = 0;
1371         }
1372
1373         DSSDBG("dsi_pll_calc\n");
1374
1375 retry:
1376         memset(&best, 0, sizeof(best));
1377         memset(&best_dispc, 0, sizeof(best_dispc));
1378
1379         memset(&cur, 0, sizeof(cur));
1380         cur.clkin = dss_sys_clk;
1381         cur.use_sys_clk = 1;
1382         cur.highfreq = 0;
1383
1384         /* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */
1385         /* highfreq: 0.75MHz < Fint = clkin / (2*regn) < 2.1MHz */
1386         /* To reduce PLL lock time, keep Fint high (around 2 MHz) */
1387         for (cur.regn = 1; cur.regn < dsi->regn_max; ++cur.regn) {
1388                 if (cur.highfreq == 0)
1389                         cur.fint = cur.clkin / cur.regn;
1390                 else
1391                         cur.fint = cur.clkin / (2 * cur.regn);
1392
1393                 if (cur.fint > dsi->fint_max || cur.fint < dsi->fint_min)
1394                         continue;
1395
1396                 /* DSIPHY(MHz) = (2 * regm / regn) * (clkin / (highfreq + 1)) */
1397                 for (cur.regm = 1; cur.regm < dsi->regm_max; ++cur.regm) {
1398                         unsigned long a, b;
1399
1400                         a = 2 * cur.regm * (cur.clkin/1000);
1401                         b = cur.regn * (cur.highfreq + 1);
1402                         cur.clkin4ddr = a / b * 1000;
1403
1404                         if (cur.clkin4ddr > 1800 * 1000 * 1000)
1405                                 break;
1406
1407                         /* dsi_pll_hsdiv_dispc_clk(MHz) =
1408                          * DSIPHY(MHz) / regm_dispc  < 173MHz/186Mhz */
1409                         for (cur.regm_dispc = 1; cur.regm_dispc <
1410                                         dsi->regm_dispc_max; ++cur.regm_dispc) {
1411                                 struct dispc_clock_info cur_dispc;
1412                                 cur.dsi_pll_hsdiv_dispc_clk =
1413                                         cur.clkin4ddr / cur.regm_dispc;
1414
1415                                 /* this will narrow down the search a bit,
1416                                  * but still give pixclocks below what was
1417                                  * requested */
1418                                 if (cur.dsi_pll_hsdiv_dispc_clk  < req_pck)
1419                                         break;
1420
1421                                 if (cur.dsi_pll_hsdiv_dispc_clk > max_dss_fck)
1422                                         continue;
1423
1424                                 if (min_fck_per_pck &&
1425                                         cur.dsi_pll_hsdiv_dispc_clk <
1426                                                 req_pck * min_fck_per_pck)
1427                                         continue;
1428
1429                                 match = 1;
1430
1431                                 dispc_find_clk_divs(is_tft, req_pck,
1432                                                 cur.dsi_pll_hsdiv_dispc_clk,
1433                                                 &cur_dispc);
1434
1435                                 if (abs(cur_dispc.pck - req_pck) <
1436                                                 abs(best_dispc.pck - req_pck)) {
1437                                         best = cur;
1438                                         best_dispc = cur_dispc;
1439
1440                                         if (cur_dispc.pck == req_pck)
1441                                                 goto found;
1442                                 }
1443                         }
1444                 }
1445         }
1446 found:
1447         if (!match) {
1448                 if (min_fck_per_pck) {
1449                         DSSERR("Could not find suitable clock settings.\n"
1450                                         "Turning FCK/PCK constraint off and"
1451                                         "trying again.\n");
1452                         min_fck_per_pck = 0;
1453                         goto retry;
1454                 }
1455
1456                 DSSERR("Could not find suitable clock settings.\n");
1457
1458                 return -EINVAL;
1459         }
1460
1461         /* dsi_pll_hsdiv_dsi_clk (regm_dsi) is not used */
1462         best.regm_dsi = 0;
1463         best.dsi_pll_hsdiv_dsi_clk = 0;
1464
1465         if (dsi_cinfo)
1466                 *dsi_cinfo = best;
1467         if (dispc_cinfo)
1468                 *dispc_cinfo = best_dispc;
1469
1470         dsi->cache_req_pck = req_pck;
1471         dsi->cache_clk_freq = 0;
1472         dsi->cache_cinfo = best;
1473
1474         return 0;
1475 }
1476
1477 int dsi_pll_set_clock_div(struct platform_device *dsidev,
1478                 struct dsi_clock_info *cinfo)
1479 {
1480         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1481         int r = 0;
1482         u32 l;
1483         int f = 0;
1484         u8 regn_start, regn_end, regm_start, regm_end;
1485         u8 regm_dispc_start, regm_dispc_end, regm_dsi_start, regm_dsi_end;
1486
1487         DSSDBGF();
1488
1489         dsi->current_cinfo.use_sys_clk = cinfo->use_sys_clk;
1490         dsi->current_cinfo.highfreq = cinfo->highfreq;
1491
1492         dsi->current_cinfo.fint = cinfo->fint;
1493         dsi->current_cinfo.clkin4ddr = cinfo->clkin4ddr;
1494         dsi->current_cinfo.dsi_pll_hsdiv_dispc_clk =
1495                         cinfo->dsi_pll_hsdiv_dispc_clk;
1496         dsi->current_cinfo.dsi_pll_hsdiv_dsi_clk =
1497                         cinfo->dsi_pll_hsdiv_dsi_clk;
1498
1499         dsi->current_cinfo.regn = cinfo->regn;
1500         dsi->current_cinfo.regm = cinfo->regm;
1501         dsi->current_cinfo.regm_dispc = cinfo->regm_dispc;
1502         dsi->current_cinfo.regm_dsi = cinfo->regm_dsi;
1503
1504         DSSDBG("DSI Fint %ld\n", cinfo->fint);
1505
1506         DSSDBG("clkin (%s) rate %ld, highfreq %d\n",
1507                         cinfo->use_sys_clk ? "dss_sys_clk" : "pclkfree",
1508                         cinfo->clkin,
1509                         cinfo->highfreq);
1510
1511         /* DSIPHY == CLKIN4DDR */
1512         DSSDBG("CLKIN4DDR = 2 * %d / %d * %lu / %d = %lu\n",
1513                         cinfo->regm,
1514                         cinfo->regn,
1515                         cinfo->clkin,
1516                         cinfo->highfreq + 1,
1517                         cinfo->clkin4ddr);
1518
1519         DSSDBG("Data rate on 1 DSI lane %ld Mbps\n",
1520                         cinfo->clkin4ddr / 1000 / 1000 / 2);
1521
1522         DSSDBG("Clock lane freq %ld Hz\n", cinfo->clkin4ddr / 4);
1523
1524         DSSDBG("regm_dispc = %d, %s (%s) = %lu\n", cinfo->regm_dispc,
1525                 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
1526                 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
1527                 cinfo->dsi_pll_hsdiv_dispc_clk);
1528         DSSDBG("regm_dsi = %d, %s (%s) = %lu\n", cinfo->regm_dsi,
1529                 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
1530                 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
1531                 cinfo->dsi_pll_hsdiv_dsi_clk);
1532
1533         dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGN, &regn_start, &regn_end);
1534         dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM, &regm_start, &regm_end);
1535         dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DISPC, &regm_dispc_start,
1536                         &regm_dispc_end);
1537         dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DSI, &regm_dsi_start,
1538                         &regm_dsi_end);
1539
1540         /* DSI_PLL_AUTOMODE = manual */
1541         REG_FLD_MOD(dsidev, DSI_PLL_CONTROL, 0, 0, 0);
1542
1543         l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION1);
1544         l = FLD_MOD(l, 1, 0, 0);                /* DSI_PLL_STOPMODE */
1545         /* DSI_PLL_REGN */
1546         l = FLD_MOD(l, cinfo->regn - 1, regn_start, regn_end);
1547         /* DSI_PLL_REGM */
1548         l = FLD_MOD(l, cinfo->regm, regm_start, regm_end);
1549         /* DSI_CLOCK_DIV */
1550         l = FLD_MOD(l, cinfo->regm_dispc > 0 ? cinfo->regm_dispc - 1 : 0,
1551                         regm_dispc_start, regm_dispc_end);
1552         /* DSIPROTO_CLOCK_DIV */
1553         l = FLD_MOD(l, cinfo->regm_dsi > 0 ? cinfo->regm_dsi - 1 : 0,
1554                         regm_dsi_start, regm_dsi_end);
1555         dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION1, l);
1556
1557         BUG_ON(cinfo->fint < dsi->fint_min || cinfo->fint > dsi->fint_max);
1558
1559         if (dss_has_feature(FEAT_DSI_PLL_FREQSEL)) {
1560                 f = cinfo->fint < 1000000 ? 0x3 :
1561                         cinfo->fint < 1250000 ? 0x4 :
1562                         cinfo->fint < 1500000 ? 0x5 :
1563                         cinfo->fint < 1750000 ? 0x6 :
1564                         0x7;
1565         }
1566
1567         l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION2);
1568
1569         if (dss_has_feature(FEAT_DSI_PLL_FREQSEL))
1570                 l = FLD_MOD(l, f, 4, 1);        /* DSI_PLL_FREQSEL */
1571         l = FLD_MOD(l, cinfo->use_sys_clk ? 0 : 1,
1572                         11, 11);                /* DSI_PLL_CLKSEL */
1573         l = FLD_MOD(l, cinfo->highfreq,
1574                         12, 12);                /* DSI_PLL_HIGHFREQ */
1575         l = FLD_MOD(l, 1, 13, 13);              /* DSI_PLL_REFEN */
1576         l = FLD_MOD(l, 0, 14, 14);              /* DSIPHY_CLKINEN */
1577         l = FLD_MOD(l, 1, 20, 20);              /* DSI_HSDIVBYPASS */
1578         dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION2, l);
1579
1580         REG_FLD_MOD(dsidev, DSI_PLL_GO, 1, 0, 0);       /* DSI_PLL_GO */
1581
1582         if (wait_for_bit_change(dsidev, DSI_PLL_GO, 0, 0) != 0) {
1583                 DSSERR("dsi pll go bit not going down.\n");
1584                 r = -EIO;
1585                 goto err;
1586         }
1587
1588         if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 1, 1) != 1) {
1589                 DSSERR("cannot lock PLL\n");
1590                 r = -EIO;
1591                 goto err;
1592         }
1593
1594         dsi->pll_locked = 1;
1595
1596         l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION2);
1597         l = FLD_MOD(l, 0, 0, 0);        /* DSI_PLL_IDLE */
1598         l = FLD_MOD(l, 0, 5, 5);        /* DSI_PLL_PLLLPMODE */
1599         l = FLD_MOD(l, 0, 6, 6);        /* DSI_PLL_LOWCURRSTBY */
1600         l = FLD_MOD(l, 0, 7, 7);        /* DSI_PLL_TIGHTPHASELOCK */
1601         l = FLD_MOD(l, 0, 8, 8);        /* DSI_PLL_DRIFTGUARDEN */
1602         l = FLD_MOD(l, 0, 10, 9);       /* DSI_PLL_LOCKSEL */
1603         l = FLD_MOD(l, 1, 13, 13);      /* DSI_PLL_REFEN */
1604         l = FLD_MOD(l, 1, 14, 14);      /* DSIPHY_CLKINEN */
1605         l = FLD_MOD(l, 0, 15, 15);      /* DSI_BYPASSEN */
1606         l = FLD_MOD(l, 1, 16, 16);      /* DSS_CLOCK_EN */
1607         l = FLD_MOD(l, 0, 17, 17);      /* DSS_CLOCK_PWDN */
1608         l = FLD_MOD(l, 1, 18, 18);      /* DSI_PROTO_CLOCK_EN */
1609         l = FLD_MOD(l, 0, 19, 19);      /* DSI_PROTO_CLOCK_PWDN */
1610         l = FLD_MOD(l, 0, 20, 20);      /* DSI_HSDIVBYPASS */
1611         dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION2, l);
1612
1613         DSSDBG("PLL config done\n");
1614 err:
1615         return r;
1616 }
1617
1618 int dsi_pll_init(struct platform_device *dsidev, bool enable_hsclk,
1619                 bool enable_hsdiv)
1620 {
1621         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1622         int r = 0;
1623         enum dsi_pll_power_state pwstate;
1624
1625         DSSDBG("PLL init\n");
1626
1627         if (dsi->vdds_dsi_reg == NULL) {
1628                 struct regulator *vdds_dsi;
1629
1630                 vdds_dsi = regulator_get(&dsi->pdev->dev, "vdds_dsi");
1631
1632                 if (IS_ERR(vdds_dsi)) {
1633                         DSSERR("can't get VDDS_DSI regulator\n");
1634                         return PTR_ERR(vdds_dsi);
1635                 }
1636
1637                 dsi->vdds_dsi_reg = vdds_dsi;
1638         }
1639
1640         dsi_enable_pll_clock(dsidev, 1);
1641         /*
1642          * Note: SCP CLK is not required on OMAP3, but it is required on OMAP4.
1643          */
1644         dsi_enable_scp_clk(dsidev);
1645
1646         if (!dsi->vdds_dsi_enabled) {
1647                 r = regulator_enable(dsi->vdds_dsi_reg);
1648                 if (r)
1649                         goto err0;
1650                 dsi->vdds_dsi_enabled = true;
1651         }
1652
1653         /* XXX PLL does not come out of reset without this... */
1654         dispc_pck_free_enable(1);
1655
1656         if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 0, 1) != 1) {
1657                 DSSERR("PLL not coming out of reset.\n");
1658                 r = -ENODEV;
1659                 dispc_pck_free_enable(0);
1660                 goto err1;
1661         }
1662
1663         /* XXX ... but if left on, we get problems when planes do not
1664          * fill the whole display. No idea about this */
1665         dispc_pck_free_enable(0);
1666
1667         if (enable_hsclk && enable_hsdiv)
1668                 pwstate = DSI_PLL_POWER_ON_ALL;
1669         else if (enable_hsclk)
1670                 pwstate = DSI_PLL_POWER_ON_HSCLK;
1671         else if (enable_hsdiv)
1672                 pwstate = DSI_PLL_POWER_ON_DIV;
1673         else
1674                 pwstate = DSI_PLL_POWER_OFF;
1675
1676         r = dsi_pll_power(dsidev, pwstate);
1677
1678         if (r)
1679                 goto err1;
1680
1681         DSSDBG("PLL init done\n");
1682
1683         return 0;
1684 err1:
1685         if (dsi->vdds_dsi_enabled) {
1686                 regulator_disable(dsi->vdds_dsi_reg);
1687                 dsi->vdds_dsi_enabled = false;
1688         }
1689 err0:
1690         dsi_disable_scp_clk(dsidev);
1691         dsi_enable_pll_clock(dsidev, 0);
1692         return r;
1693 }
1694
1695 void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes)
1696 {
1697         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1698
1699         dsi->pll_locked = 0;
1700         dsi_pll_power(dsidev, DSI_PLL_POWER_OFF);
1701         if (disconnect_lanes) {
1702                 WARN_ON(!dsi->vdds_dsi_enabled);
1703                 regulator_disable(dsi->vdds_dsi_reg);
1704                 dsi->vdds_dsi_enabled = false;
1705         }
1706
1707         dsi_disable_scp_clk(dsidev);
1708         dsi_enable_pll_clock(dsidev, 0);
1709
1710         DSSDBG("PLL uninit done\n");
1711 }
1712
1713 static void dsi_dump_dsidev_clocks(struct platform_device *dsidev,
1714                 struct seq_file *s)
1715 {
1716         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1717         struct dsi_clock_info *cinfo = &dsi->current_cinfo;
1718         enum omap_dss_clk_source dispc_clk_src, dsi_clk_src;
1719         int dsi_module = dsi_get_dsidev_id(dsidev);
1720
1721         dispc_clk_src = dss_get_dispc_clk_source();
1722         dsi_clk_src = dss_get_dsi_clk_source(dsi_module);
1723
1724         if (dsi_runtime_get(dsidev))
1725                 return;
1726
1727         seq_printf(s,   "- DSI%d PLL -\n", dsi_module + 1);
1728
1729         seq_printf(s,   "dsi pll source = %s\n",
1730                         cinfo->use_sys_clk ? "dss_sys_clk" : "pclkfree");
1731
1732         seq_printf(s,   "Fint\t\t%-16luregn %u\n", cinfo->fint, cinfo->regn);
1733
1734         seq_printf(s,   "CLKIN4DDR\t%-16luregm %u\n",
1735                         cinfo->clkin4ddr, cinfo->regm);
1736
1737         seq_printf(s,   "DSI_PLL_HSDIV_DISPC (%s)\t%-16luregm_dispc %u\t(%s)\n",
1738                         dss_feat_get_clk_source_name(dsi_module == 0 ?
1739                                 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC :
1740                                 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC),
1741                         cinfo->dsi_pll_hsdiv_dispc_clk,
1742                         cinfo->regm_dispc,
1743                         dispc_clk_src == OMAP_DSS_CLK_SRC_FCK ?
1744                         "off" : "on");
1745
1746         seq_printf(s,   "DSI_PLL_HSDIV_DSI (%s)\t%-16luregm_dsi %u\t(%s)\n",
1747                         dss_feat_get_clk_source_name(dsi_module == 0 ?
1748                                 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI :
1749                                 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI),
1750                         cinfo->dsi_pll_hsdiv_dsi_clk,
1751                         cinfo->regm_dsi,
1752                         dsi_clk_src == OMAP_DSS_CLK_SRC_FCK ?
1753                         "off" : "on");
1754
1755         seq_printf(s,   "- DSI%d -\n", dsi_module + 1);
1756
1757         seq_printf(s,   "dsi fclk source = %s (%s)\n",
1758                         dss_get_generic_clk_source_name(dsi_clk_src),
1759                         dss_feat_get_clk_source_name(dsi_clk_src));
1760
1761         seq_printf(s,   "DSI_FCLK\t%lu\n", dsi_fclk_rate(dsidev));
1762
1763         seq_printf(s,   "DDR_CLK\t\t%lu\n",
1764                         cinfo->clkin4ddr / 4);
1765
1766         seq_printf(s,   "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs(dsidev));
1767
1768         seq_printf(s,   "LP_CLK\t\t%lu\n", cinfo->lp_clk);
1769
1770         dsi_runtime_put(dsidev);
1771 }
1772
1773 void dsi_dump_clocks(struct seq_file *s)
1774 {
1775         struct platform_device *dsidev;
1776         int i;
1777
1778         for  (i = 0; i < MAX_NUM_DSI; i++) {
1779                 dsidev = dsi_get_dsidev_from_id(i);
1780                 if (dsidev)
1781                         dsi_dump_dsidev_clocks(dsidev, s);
1782         }
1783 }
1784
1785 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
1786 static void dsi_dump_dsidev_irqs(struct platform_device *dsidev,
1787                 struct seq_file *s)
1788 {
1789         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1790         unsigned long flags;
1791         struct dsi_irq_stats stats;
1792         int dsi_module = dsi_get_dsidev_id(dsidev);
1793
1794         spin_lock_irqsave(&dsi->irq_stats_lock, flags);
1795
1796         stats = dsi->irq_stats;
1797         memset(&dsi->irq_stats, 0, sizeof(dsi->irq_stats));
1798         dsi->irq_stats.last_reset = jiffies;
1799
1800         spin_unlock_irqrestore(&dsi->irq_stats_lock, flags);
1801
1802         seq_printf(s, "period %u ms\n",
1803                         jiffies_to_msecs(jiffies - stats.last_reset));
1804
1805         seq_printf(s, "irqs %d\n", stats.irq_count);
1806 #define PIS(x) \
1807         seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]);
1808
1809         seq_printf(s, "-- DSI%d interrupts --\n", dsi_module + 1);
1810         PIS(VC0);
1811         PIS(VC1);
1812         PIS(VC2);
1813         PIS(VC3);
1814         PIS(WAKEUP);
1815         PIS(RESYNC);
1816         PIS(PLL_LOCK);
1817         PIS(PLL_UNLOCK);
1818         PIS(PLL_RECALL);
1819         PIS(COMPLEXIO_ERR);
1820         PIS(HS_TX_TIMEOUT);
1821         PIS(LP_RX_TIMEOUT);
1822         PIS(TE_TRIGGER);
1823         PIS(ACK_TRIGGER);
1824         PIS(SYNC_LOST);
1825         PIS(LDO_POWER_GOOD);
1826         PIS(TA_TIMEOUT);
1827 #undef PIS
1828
1829 #define PIS(x) \
1830         seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \
1831                         stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \
1832                         stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \
1833                         stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \
1834                         stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]);
1835
1836         seq_printf(s, "-- VC interrupts --\n");
1837         PIS(CS);
1838         PIS(ECC_CORR);
1839         PIS(PACKET_SENT);
1840         PIS(FIFO_TX_OVF);
1841         PIS(FIFO_RX_OVF);
1842         PIS(BTA);
1843         PIS(ECC_NO_CORR);
1844         PIS(FIFO_TX_UDF);
1845         PIS(PP_BUSY_CHANGE);
1846 #undef PIS
1847
1848 #define PIS(x) \
1849         seq_printf(s, "%-20s %10d\n", #x, \
1850                         stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]);
1851
1852         seq_printf(s, "-- CIO interrupts --\n");
1853         PIS(ERRSYNCESC1);
1854         PIS(ERRSYNCESC2);
1855         PIS(ERRSYNCESC3);
1856         PIS(ERRESC1);
1857         PIS(ERRESC2);
1858         PIS(ERRESC3);
1859         PIS(ERRCONTROL1);
1860         PIS(ERRCONTROL2);
1861         PIS(ERRCONTROL3);
1862         PIS(STATEULPS1);
1863         PIS(STATEULPS2);
1864         PIS(STATEULPS3);
1865         PIS(ERRCONTENTIONLP0_1);
1866         PIS(ERRCONTENTIONLP1_1);
1867         PIS(ERRCONTENTIONLP0_2);
1868         PIS(ERRCONTENTIONLP1_2);
1869         PIS(ERRCONTENTIONLP0_3);
1870         PIS(ERRCONTENTIONLP1_3);
1871         PIS(ULPSACTIVENOT_ALL0);
1872         PIS(ULPSACTIVENOT_ALL1);
1873 #undef PIS
1874 }
1875
1876 static void dsi1_dump_irqs(struct seq_file *s)
1877 {
1878         struct platform_device *dsidev = dsi_get_dsidev_from_id(0);
1879
1880         dsi_dump_dsidev_irqs(dsidev, s);
1881 }
1882
1883 static void dsi2_dump_irqs(struct seq_file *s)
1884 {
1885         struct platform_device *dsidev = dsi_get_dsidev_from_id(1);
1886
1887         dsi_dump_dsidev_irqs(dsidev, s);
1888 }
1889
1890 void dsi_create_debugfs_files_irq(struct dentry *debugfs_dir,
1891                 const struct file_operations *debug_fops)
1892 {
1893         struct platform_device *dsidev;
1894
1895         dsidev = dsi_get_dsidev_from_id(0);
1896         if (dsidev)
1897                 debugfs_create_file("dsi1_irqs", S_IRUGO, debugfs_dir,
1898                         &dsi1_dump_irqs, debug_fops);
1899
1900         dsidev = dsi_get_dsidev_from_id(1);
1901         if (dsidev)
1902                 debugfs_create_file("dsi2_irqs", S_IRUGO, debugfs_dir,
1903                         &dsi2_dump_irqs, debug_fops);
1904 }
1905 #endif
1906
1907 static void dsi_dump_dsidev_regs(struct platform_device *dsidev,
1908                 struct seq_file *s)
1909 {
1910 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsidev, r))
1911
1912         if (dsi_runtime_get(dsidev))
1913                 return;
1914         dsi_enable_scp_clk(dsidev);
1915
1916         DUMPREG(DSI_REVISION);
1917         DUMPREG(DSI_SYSCONFIG);
1918         DUMPREG(DSI_SYSSTATUS);
1919         DUMPREG(DSI_IRQSTATUS);
1920         DUMPREG(DSI_IRQENABLE);
1921         DUMPREG(DSI_CTRL);
1922         DUMPREG(DSI_COMPLEXIO_CFG1);
1923         DUMPREG(DSI_COMPLEXIO_IRQ_STATUS);
1924         DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE);
1925         DUMPREG(DSI_CLK_CTRL);
1926         DUMPREG(DSI_TIMING1);
1927         DUMPREG(DSI_TIMING2);
1928         DUMPREG(DSI_VM_TIMING1);
1929         DUMPREG(DSI_VM_TIMING2);
1930         DUMPREG(DSI_VM_TIMING3);
1931         DUMPREG(DSI_CLK_TIMING);
1932         DUMPREG(DSI_TX_FIFO_VC_SIZE);
1933         DUMPREG(DSI_RX_FIFO_VC_SIZE);
1934         DUMPREG(DSI_COMPLEXIO_CFG2);
1935         DUMPREG(DSI_RX_FIFO_VC_FULLNESS);
1936         DUMPREG(DSI_VM_TIMING4);
1937         DUMPREG(DSI_TX_FIFO_VC_EMPTINESS);
1938         DUMPREG(DSI_VM_TIMING5);
1939         DUMPREG(DSI_VM_TIMING6);
1940         DUMPREG(DSI_VM_TIMING7);
1941         DUMPREG(DSI_STOPCLK_TIMING);
1942
1943         DUMPREG(DSI_VC_CTRL(0));
1944         DUMPREG(DSI_VC_TE(0));
1945         DUMPREG(DSI_VC_LONG_PACKET_HEADER(0));
1946         DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0));
1947         DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0));
1948         DUMPREG(DSI_VC_IRQSTATUS(0));
1949         DUMPREG(DSI_VC_IRQENABLE(0));
1950
1951         DUMPREG(DSI_VC_CTRL(1));
1952         DUMPREG(DSI_VC_TE(1));
1953         DUMPREG(DSI_VC_LONG_PACKET_HEADER(1));
1954         DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1));
1955         DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1));
1956         DUMPREG(DSI_VC_IRQSTATUS(1));
1957         DUMPREG(DSI_VC_IRQENABLE(1));
1958
1959         DUMPREG(DSI_VC_CTRL(2));
1960         DUMPREG(DSI_VC_TE(2));
1961         DUMPREG(DSI_VC_LONG_PACKET_HEADER(2));
1962         DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2));
1963         DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2));
1964         DUMPREG(DSI_VC_IRQSTATUS(2));
1965         DUMPREG(DSI_VC_IRQENABLE(2));
1966
1967         DUMPREG(DSI_VC_CTRL(3));
1968         DUMPREG(DSI_VC_TE(3));
1969         DUMPREG(DSI_VC_LONG_PACKET_HEADER(3));
1970         DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3));
1971         DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3));
1972         DUMPREG(DSI_VC_IRQSTATUS(3));
1973         DUMPREG(DSI_VC_IRQENABLE(3));
1974
1975         DUMPREG(DSI_DSIPHY_CFG0);
1976         DUMPREG(DSI_DSIPHY_CFG1);
1977         DUMPREG(DSI_DSIPHY_CFG2);
1978         DUMPREG(DSI_DSIPHY_CFG5);
1979
1980         DUMPREG(DSI_PLL_CONTROL);
1981         DUMPREG(DSI_PLL_STATUS);
1982         DUMPREG(DSI_PLL_GO);
1983         DUMPREG(DSI_PLL_CONFIGURATION1);
1984         DUMPREG(DSI_PLL_CONFIGURATION2);
1985
1986         dsi_disable_scp_clk(dsidev);
1987         dsi_runtime_put(dsidev);
1988 #undef DUMPREG
1989 }
1990
1991 static void dsi1_dump_regs(struct seq_file *s)
1992 {
1993         struct platform_device *dsidev = dsi_get_dsidev_from_id(0);
1994
1995         dsi_dump_dsidev_regs(dsidev, s);
1996 }
1997
1998 static void dsi2_dump_regs(struct seq_file *s)
1999 {
2000         struct platform_device *dsidev = dsi_get_dsidev_from_id(1);
2001
2002         dsi_dump_dsidev_regs(dsidev, s);
2003 }
2004
2005 void dsi_create_debugfs_files_reg(struct dentry *debugfs_dir,
2006                 const struct file_operations *debug_fops)
2007 {
2008         struct platform_device *dsidev;
2009
2010         dsidev = dsi_get_dsidev_from_id(0);
2011         if (dsidev)
2012                 debugfs_create_file("dsi1_regs", S_IRUGO, debugfs_dir,
2013                         &dsi1_dump_regs, debug_fops);
2014
2015         dsidev = dsi_get_dsidev_from_id(1);
2016         if (dsidev)
2017                 debugfs_create_file("dsi2_regs", S_IRUGO, debugfs_dir,
2018                         &dsi2_dump_regs, debug_fops);
2019 }
2020 enum dsi_cio_power_state {
2021         DSI_COMPLEXIO_POWER_OFF         = 0x0,
2022         DSI_COMPLEXIO_POWER_ON          = 0x1,
2023         DSI_COMPLEXIO_POWER_ULPS        = 0x2,
2024 };
2025
2026 static int dsi_cio_power(struct platform_device *dsidev,
2027                 enum dsi_cio_power_state state)
2028 {
2029         int t = 0;
2030
2031         /* PWR_CMD */
2032         REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG1, state, 28, 27);
2033
2034         /* PWR_STATUS */
2035         while (FLD_GET(dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1),
2036                         26, 25) != state) {
2037                 if (++t > 1000) {
2038                         DSSERR("failed to set complexio power state to "
2039                                         "%d\n", state);
2040                         return -ENODEV;
2041                 }
2042                 udelay(1);
2043         }
2044
2045         return 0;
2046 }
2047
2048 static unsigned dsi_get_line_buf_size(struct platform_device *dsidev)
2049 {
2050         int val;
2051
2052         /* line buffer on OMAP3 is 1024 x 24bits */
2053         /* XXX: for some reason using full buffer size causes
2054          * considerable TX slowdown with update sizes that fill the
2055          * whole buffer */
2056         if (!dss_has_feature(FEAT_DSI_GNQ))
2057                 return 1023 * 3;
2058
2059         val = REG_GET(dsidev, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */
2060
2061         switch (val) {
2062         case 1:
2063                 return 512 * 3;         /* 512x24 bits */
2064         case 2:
2065                 return 682 * 3;         /* 682x24 bits */
2066         case 3:
2067                 return 853 * 3;         /* 853x24 bits */
2068         case 4:
2069                 return 1024 * 3;        /* 1024x24 bits */
2070         case 5:
2071                 return 1194 * 3;        /* 1194x24 bits */
2072         case 6:
2073                 return 1365 * 3;        /* 1365x24 bits */
2074         default:
2075                 BUG();
2076         }
2077 }
2078
2079 static int dsi_parse_lane_config(struct omap_dss_device *dssdev)
2080 {
2081         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2082         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2083         u8 lanes[DSI_MAX_NR_LANES];
2084         u8 polarities[DSI_MAX_NR_LANES];
2085         int num_lanes, i;
2086
2087         static const enum dsi_lane_function functions[] = {
2088                 DSI_LANE_CLK,
2089                 DSI_LANE_DATA1,
2090                 DSI_LANE_DATA2,
2091                 DSI_LANE_DATA3,
2092                 DSI_LANE_DATA4,
2093         };
2094
2095         lanes[0] = dssdev->phy.dsi.clk_lane;
2096         lanes[1] = dssdev->phy.dsi.data1_lane;
2097         lanes[2] = dssdev->phy.dsi.data2_lane;
2098         lanes[3] = dssdev->phy.dsi.data3_lane;
2099         lanes[4] = dssdev->phy.dsi.data4_lane;
2100         polarities[0] = dssdev->phy.dsi.clk_pol;
2101         polarities[1] = dssdev->phy.dsi.data1_pol;
2102         polarities[2] = dssdev->phy.dsi.data2_pol;
2103         polarities[3] = dssdev->phy.dsi.data3_pol;
2104         polarities[4] = dssdev->phy.dsi.data4_pol;
2105
2106         num_lanes = 0;
2107
2108         for (i = 0; i < dsi->num_lanes_supported; ++i)
2109                 dsi->lanes[i].function = DSI_LANE_UNUSED;
2110
2111         for (i = 0; i < dsi->num_lanes_supported; ++i) {
2112                 int num;
2113
2114                 if (lanes[i] == DSI_LANE_UNUSED)
2115                         break;
2116
2117                 num = lanes[i] - 1;
2118
2119                 if (num >= dsi->num_lanes_supported)
2120                         return -EINVAL;
2121
2122                 if (dsi->lanes[num].function != DSI_LANE_UNUSED)
2123                         return -EINVAL;
2124
2125                 dsi->lanes[num].function = functions[i];
2126                 dsi->lanes[num].polarity = polarities[i];
2127                 num_lanes++;
2128         }
2129
2130         if (num_lanes < 2 || num_lanes > dsi->num_lanes_supported)
2131                 return -EINVAL;
2132
2133         dsi->num_lanes_used = num_lanes;
2134
2135         return 0;
2136 }
2137
2138 static int dsi_set_lane_config(struct omap_dss_device *dssdev)
2139 {
2140         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2141         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2142         static const u8 offsets[] = { 0, 4, 8, 12, 16 };
2143         static const enum dsi_lane_function functions[] = {
2144                 DSI_LANE_CLK,
2145                 DSI_LANE_DATA1,
2146                 DSI_LANE_DATA2,
2147                 DSI_LANE_DATA3,
2148                 DSI_LANE_DATA4,
2149         };
2150         u32 r;
2151         int i;
2152
2153         r = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1);
2154
2155         for (i = 0; i < dsi->num_lanes_used; ++i) {
2156                 unsigned offset = offsets[i];
2157                 unsigned polarity, lane_number;
2158                 unsigned t;
2159
2160                 for (t = 0; t < dsi->num_lanes_supported; ++t)
2161                         if (dsi->lanes[t].function == functions[i])
2162                                 break;
2163
2164                 if (t == dsi->num_lanes_supported)
2165                         return -EINVAL;
2166
2167                 lane_number = t;
2168                 polarity = dsi->lanes[t].polarity;
2169
2170                 r = FLD_MOD(r, lane_number + 1, offset + 2, offset);
2171                 r = FLD_MOD(r, polarity, offset + 3, offset + 3);
2172         }
2173
2174         /* clear the unused lanes */
2175         for (; i < dsi->num_lanes_supported; ++i) {
2176                 unsigned offset = offsets[i];
2177
2178                 r = FLD_MOD(r, 0, offset + 2, offset);
2179                 r = FLD_MOD(r, 0, offset + 3, offset + 3);
2180         }
2181
2182         dsi_write_reg(dsidev, DSI_COMPLEXIO_CFG1, r);
2183
2184         return 0;
2185 }
2186
2187 static inline unsigned ns2ddr(struct platform_device *dsidev, unsigned ns)
2188 {
2189         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2190
2191         /* convert time in ns to ddr ticks, rounding up */
2192         unsigned long ddr_clk = dsi->current_cinfo.clkin4ddr / 4;
2193         return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000;
2194 }
2195
2196 static inline unsigned ddr2ns(struct platform_device *dsidev, unsigned ddr)
2197 {
2198         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2199
2200         unsigned long ddr_clk = dsi->current_cinfo.clkin4ddr / 4;
2201         return ddr * 1000 * 1000 / (ddr_clk / 1000);
2202 }
2203
2204 static void dsi_cio_timings(struct platform_device *dsidev)
2205 {
2206         u32 r;
2207         u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit;
2208         u32 tlpx_half, tclk_trail, tclk_zero;
2209         u32 tclk_prepare;
2210
2211         /* calculate timings */
2212
2213         /* 1 * DDR_CLK = 2 * UI */
2214
2215         /* min 40ns + 4*UI      max 85ns + 6*UI */
2216         ths_prepare = ns2ddr(dsidev, 70) + 2;
2217
2218         /* min 145ns + 10*UI */
2219         ths_prepare_ths_zero = ns2ddr(dsidev, 175) + 2;
2220
2221         /* min max(8*UI, 60ns+4*UI) */
2222         ths_trail = ns2ddr(dsidev, 60) + 5;
2223
2224         /* min 100ns */
2225         ths_exit = ns2ddr(dsidev, 145);
2226
2227         /* tlpx min 50n */
2228         tlpx_half = ns2ddr(dsidev, 25);
2229
2230         /* min 60ns */
2231         tclk_trail = ns2ddr(dsidev, 60) + 2;
2232
2233         /* min 38ns, max 95ns */
2234         tclk_prepare = ns2ddr(dsidev, 65);
2235
2236         /* min tclk-prepare + tclk-zero = 300ns */
2237         tclk_zero = ns2ddr(dsidev, 260);
2238
2239         DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
2240                 ths_prepare, ddr2ns(dsidev, ths_prepare),
2241                 ths_prepare_ths_zero, ddr2ns(dsidev, ths_prepare_ths_zero));
2242         DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n",
2243                         ths_trail, ddr2ns(dsidev, ths_trail),
2244                         ths_exit, ddr2ns(dsidev, ths_exit));
2245
2246         DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), "
2247                         "tclk_zero %u (%uns)\n",
2248                         tlpx_half, ddr2ns(dsidev, tlpx_half),
2249                         tclk_trail, ddr2ns(dsidev, tclk_trail),
2250                         tclk_zero, ddr2ns(dsidev, tclk_zero));
2251         DSSDBG("tclk_prepare %u (%uns)\n",
2252                         tclk_prepare, ddr2ns(dsidev, tclk_prepare));
2253
2254         /* program timings */
2255
2256         r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
2257         r = FLD_MOD(r, ths_prepare, 31, 24);
2258         r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16);
2259         r = FLD_MOD(r, ths_trail, 15, 8);
2260         r = FLD_MOD(r, ths_exit, 7, 0);
2261         dsi_write_reg(dsidev, DSI_DSIPHY_CFG0, r);
2262
2263         r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
2264         r = FLD_MOD(r, tlpx_half, 22, 16);
2265         r = FLD_MOD(r, tclk_trail, 15, 8);
2266         r = FLD_MOD(r, tclk_zero, 7, 0);
2267         dsi_write_reg(dsidev, DSI_DSIPHY_CFG1, r);
2268
2269         r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
2270         r = FLD_MOD(r, tclk_prepare, 7, 0);
2271         dsi_write_reg(dsidev, DSI_DSIPHY_CFG2, r);
2272 }
2273
2274 /* lane masks have lane 0 at lsb. mask_p for positive lines, n for negative */
2275 static void dsi_cio_enable_lane_override(struct omap_dss_device *dssdev,
2276                 unsigned mask_p, unsigned mask_n)
2277 {
2278         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2279         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2280         int i;
2281         u32 l;
2282         u8 lptxscp_start = dsi->num_lanes_supported == 3 ? 22 : 26;
2283
2284         l = 0;
2285
2286         for (i = 0; i < dsi->num_lanes_supported; ++i) {
2287                 unsigned p = dsi->lanes[i].polarity;
2288
2289                 if (mask_p & (1 << i))
2290                         l |= 1 << (i * 2 + (p ? 0 : 1));
2291
2292                 if (mask_n & (1 << i))
2293                         l |= 1 << (i * 2 + (p ? 1 : 0));
2294         }
2295
2296         /*
2297          * Bits in REGLPTXSCPDAT4TO0DXDY:
2298          * 17: DY0 18: DX0
2299          * 19: DY1 20: DX1
2300          * 21: DY2 22: DX2
2301          * 23: DY3 24: DX3
2302          * 25: DY4 26: DX4
2303          */
2304
2305         /* Set the lane override configuration */
2306
2307         /* REGLPTXSCPDAT4TO0DXDY */
2308         REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, l, lptxscp_start, 17);
2309
2310         /* Enable lane override */
2311
2312         /* ENLPTXSCPDAT */
2313         REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 1, 27, 27);
2314 }
2315
2316 static void dsi_cio_disable_lane_override(struct platform_device *dsidev)
2317 {
2318         /* Disable lane override */
2319         REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 27, 27); /* ENLPTXSCPDAT */
2320         /* Reset the lane override configuration */
2321         /* REGLPTXSCPDAT4TO0DXDY */
2322         REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 22, 17);
2323 }
2324
2325 static int dsi_cio_wait_tx_clk_esc_reset(struct omap_dss_device *dssdev)
2326 {
2327         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2328         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2329         int t, i;
2330         bool in_use[DSI_MAX_NR_LANES];
2331         static const u8 offsets_old[] = { 28, 27, 26 };
2332         static const u8 offsets_new[] = { 24, 25, 26, 27, 28 };
2333         const u8 *offsets;
2334
2335         if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC))
2336                 offsets = offsets_old;
2337         else
2338                 offsets = offsets_new;
2339
2340         for (i = 0; i < dsi->num_lanes_supported; ++i)
2341                 in_use[i] = dsi->lanes[i].function != DSI_LANE_UNUSED;
2342
2343         t = 100000;
2344         while (true) {
2345                 u32 l;
2346                 int ok;
2347
2348                 l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
2349
2350                 ok = 0;
2351                 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2352                         if (!in_use[i] || (l & (1 << offsets[i])))
2353                                 ok++;
2354                 }
2355
2356                 if (ok == dsi->num_lanes_supported)
2357                         break;
2358
2359                 if (--t == 0) {
2360                         for (i = 0; i < dsi->num_lanes_supported; ++i) {
2361                                 if (!in_use[i] || (l & (1 << offsets[i])))
2362                                         continue;
2363
2364                                 DSSERR("CIO TXCLKESC%d domain not coming " \
2365                                                 "out of reset\n", i);
2366                         }
2367                         return -EIO;
2368                 }
2369         }
2370
2371         return 0;
2372 }
2373
2374 /* return bitmask of enabled lanes, lane0 being the lsb */
2375 static unsigned dsi_get_lane_mask(struct omap_dss_device *dssdev)
2376 {
2377         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2378         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2379         unsigned mask = 0;
2380         int i;
2381
2382         for (i = 0; i < dsi->num_lanes_supported; ++i) {
2383                 if (dsi->lanes[i].function != DSI_LANE_UNUSED)
2384                         mask |= 1 << i;
2385         }
2386
2387         return mask;
2388 }
2389
2390 static int dsi_cio_init(struct omap_dss_device *dssdev)
2391 {
2392         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2393         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2394         int r;
2395         u32 l;
2396
2397         DSSDBGF();
2398
2399         r = dsi->enable_pads(dsidev->id, dsi_get_lane_mask(dssdev));
2400         if (r)
2401                 return r;
2402
2403         dsi_enable_scp_clk(dsidev);
2404
2405         /* A dummy read using the SCP interface to any DSIPHY register is
2406          * required after DSIPHY reset to complete the reset of the DSI complex
2407          * I/O. */
2408         dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
2409
2410         if (wait_for_bit_change(dsidev, DSI_DSIPHY_CFG5, 30, 1) != 1) {
2411                 DSSERR("CIO SCP Clock domain not coming out of reset.\n");
2412                 r = -EIO;
2413                 goto err_scp_clk_dom;
2414         }
2415
2416         r = dsi_set_lane_config(dssdev);
2417         if (r)
2418                 goto err_scp_clk_dom;
2419
2420         /* set TX STOP MODE timer to maximum for this operation */
2421         l = dsi_read_reg(dsidev, DSI_TIMING1);
2422         l = FLD_MOD(l, 1, 15, 15);      /* FORCE_TX_STOP_MODE_IO */
2423         l = FLD_MOD(l, 1, 14, 14);      /* STOP_STATE_X16_IO */
2424         l = FLD_MOD(l, 1, 13, 13);      /* STOP_STATE_X4_IO */
2425         l = FLD_MOD(l, 0x1fff, 12, 0);  /* STOP_STATE_COUNTER_IO */
2426         dsi_write_reg(dsidev, DSI_TIMING1, l);
2427
2428         if (dsi->ulps_enabled) {
2429                 unsigned mask_p;
2430                 int i;
2431
2432                 DSSDBG("manual ulps exit\n");
2433
2434                 /* ULPS is exited by Mark-1 state for 1ms, followed by
2435                  * stop state. DSS HW cannot do this via the normal
2436                  * ULPS exit sequence, as after reset the DSS HW thinks
2437                  * that we are not in ULPS mode, and refuses to send the
2438                  * sequence. So we need to send the ULPS exit sequence
2439                  * manually by setting positive lines high and negative lines
2440                  * low for 1ms.
2441                  */
2442
2443                 mask_p = 0;
2444
2445                 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2446                         if (dsi->lanes[i].function == DSI_LANE_UNUSED)
2447                                 continue;
2448                         mask_p |= 1 << i;
2449                 }
2450
2451                 dsi_cio_enable_lane_override(dssdev, mask_p, 0);
2452         }
2453
2454         r = dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ON);
2455         if (r)
2456                 goto err_cio_pwr;
2457
2458         if (wait_for_bit_change(dsidev, DSI_COMPLEXIO_CFG1, 29, 1) != 1) {
2459                 DSSERR("CIO PWR clock domain not coming out of reset.\n");
2460                 r = -ENODEV;
2461                 goto err_cio_pwr_dom;
2462         }
2463
2464         dsi_if_enable(dsidev, true);
2465         dsi_if_enable(dsidev, false);
2466         REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */
2467
2468         r = dsi_cio_wait_tx_clk_esc_reset(dssdev);
2469         if (r)
2470                 goto err_tx_clk_esc_rst;
2471
2472         if (dsi->ulps_enabled) {
2473                 /* Keep Mark-1 state for 1ms (as per DSI spec) */
2474                 ktime_t wait = ns_to_ktime(1000 * 1000);
2475                 set_current_state(TASK_UNINTERRUPTIBLE);
2476                 schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
2477
2478                 /* Disable the override. The lanes should be set to Mark-11
2479                  * state by the HW */
2480                 dsi_cio_disable_lane_override(dsidev);
2481         }
2482
2483         /* FORCE_TX_STOP_MODE_IO */
2484         REG_FLD_MOD(dsidev, DSI_TIMING1, 0, 15, 15);
2485
2486         dsi_cio_timings(dsidev);
2487
2488         if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) {
2489                 /* DDR_CLK_ALWAYS_ON */
2490                 REG_FLD_MOD(dsidev, DSI_CLK_CTRL,
2491                         dssdev->panel.dsi_vm_data.ddr_clk_always_on, 13, 13);
2492         }
2493
2494         dsi->ulps_enabled = false;
2495
2496         DSSDBG("CIO init done\n");
2497
2498         return 0;
2499
2500 err_tx_clk_esc_rst:
2501         REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 20, 20); /* LP_CLK_ENABLE */
2502 err_cio_pwr_dom:
2503         dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
2504 err_cio_pwr:
2505         if (dsi->ulps_enabled)
2506                 dsi_cio_disable_lane_override(dsidev);
2507 err_scp_clk_dom:
2508         dsi_disable_scp_clk(dsidev);
2509         dsi->disable_pads(dsidev->id, dsi_get_lane_mask(dssdev));
2510         return r;
2511 }
2512
2513 static void dsi_cio_uninit(struct omap_dss_device *dssdev)
2514 {
2515         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2516         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2517
2518         /* DDR_CLK_ALWAYS_ON */
2519         REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13);
2520
2521         dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
2522         dsi_disable_scp_clk(dsidev);
2523         dsi->disable_pads(dsidev->id, dsi_get_lane_mask(dssdev));
2524 }
2525
2526 static void dsi_config_tx_fifo(struct platform_device *dsidev,
2527                 enum fifo_size size1, enum fifo_size size2,
2528                 enum fifo_size size3, enum fifo_size size4)
2529 {
2530         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2531         u32 r = 0;
2532         int add = 0;
2533         int i;
2534
2535         dsi->vc[0].fifo_size = size1;
2536         dsi->vc[1].fifo_size = size2;
2537         dsi->vc[2].fifo_size = size3;
2538         dsi->vc[3].fifo_size = size4;
2539
2540         for (i = 0; i < 4; i++) {
2541                 u8 v;
2542                 int size = dsi->vc[i].fifo_size;
2543
2544                 if (add + size > 4) {
2545                         DSSERR("Illegal FIFO configuration\n");
2546                         BUG();
2547                 }
2548
2549                 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2550                 r |= v << (8 * i);
2551                 /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */
2552                 add += size;
2553         }
2554
2555         dsi_write_reg(dsidev, DSI_TX_FIFO_VC_SIZE, r);
2556 }
2557
2558 static void dsi_config_rx_fifo(struct platform_device *dsidev,
2559                 enum fifo_size size1, enum fifo_size size2,
2560                 enum fifo_size size3, enum fifo_size size4)
2561 {
2562         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2563         u32 r = 0;
2564         int add = 0;
2565         int i;
2566
2567         dsi->vc[0].fifo_size = size1;
2568         dsi->vc[1].fifo_size = size2;
2569         dsi->vc[2].fifo_size = size3;
2570         dsi->vc[3].fifo_size = size4;
2571
2572         for (i = 0; i < 4; i++) {
2573                 u8 v;
2574                 int size = dsi->vc[i].fifo_size;
2575
2576                 if (add + size > 4) {
2577                         DSSERR("Illegal FIFO configuration\n");
2578                         BUG();
2579                 }
2580
2581                 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2582                 r |= v << (8 * i);
2583                 /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */
2584                 add += size;
2585         }
2586
2587         dsi_write_reg(dsidev, DSI_RX_FIFO_VC_SIZE, r);
2588 }
2589
2590 static int dsi_force_tx_stop_mode_io(struct platform_device *dsidev)
2591 {
2592         u32 r;
2593
2594         r = dsi_read_reg(dsidev, DSI_TIMING1);
2595         r = FLD_MOD(r, 1, 15, 15);      /* FORCE_TX_STOP_MODE_IO */
2596         dsi_write_reg(dsidev, DSI_TIMING1, r);
2597
2598         if (wait_for_bit_change(dsidev, DSI_TIMING1, 15, 0) != 0) {
2599                 DSSERR("TX_STOP bit not going down\n");
2600                 return -EIO;
2601         }
2602
2603         return 0;
2604 }
2605
2606 static bool dsi_vc_is_enabled(struct platform_device *dsidev, int channel)
2607 {
2608         return REG_GET(dsidev, DSI_VC_CTRL(channel), 0, 0);
2609 }
2610
2611 static void dsi_packet_sent_handler_vp(void *data, u32 mask)
2612 {
2613         struct dsi_packet_sent_handler_data *vp_data =
2614                 (struct dsi_packet_sent_handler_data *) data;
2615         struct dsi_data *dsi = dsi_get_dsidrv_data(vp_data->dsidev);
2616         const int channel = dsi->update_channel;
2617         u8 bit = dsi->te_enabled ? 30 : 31;
2618
2619         if (REG_GET(vp_data->dsidev, DSI_VC_TE(channel), bit, bit) == 0)
2620                 complete(vp_data->completion);
2621 }
2622
2623 static int dsi_sync_vc_vp(struct platform_device *dsidev, int channel)
2624 {
2625         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2626         DECLARE_COMPLETION_ONSTACK(completion);
2627         struct dsi_packet_sent_handler_data vp_data = { dsidev, &completion };
2628         int r = 0;
2629         u8 bit;
2630
2631         bit = dsi->te_enabled ? 30 : 31;
2632
2633         r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2634                 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2635         if (r)
2636                 goto err0;
2637
2638         /* Wait for completion only if TE_EN/TE_START is still set */
2639         if (REG_GET(dsidev, DSI_VC_TE(channel), bit, bit)) {
2640                 if (wait_for_completion_timeout(&completion,
2641                                 msecs_to_jiffies(10)) == 0) {
2642                         DSSERR("Failed to complete previous frame transfer\n");
2643                         r = -EIO;
2644                         goto err1;
2645                 }
2646         }
2647
2648         dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2649                 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2650
2651         return 0;
2652 err1:
2653         dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2654                 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2655 err0:
2656         return r;
2657 }
2658
2659 static void dsi_packet_sent_handler_l4(void *data, u32 mask)
2660 {
2661         struct dsi_packet_sent_handler_data *l4_data =
2662                 (struct dsi_packet_sent_handler_data *) data;
2663         struct dsi_data *dsi = dsi_get_dsidrv_data(l4_data->dsidev);
2664         const int channel = dsi->update_channel;
2665
2666         if (REG_GET(l4_data->dsidev, DSI_VC_CTRL(channel), 5, 5) == 0)
2667                 complete(l4_data->completion);
2668 }
2669
2670 static int dsi_sync_vc_l4(struct platform_device *dsidev, int channel)
2671 {
2672         DECLARE_COMPLETION_ONSTACK(completion);
2673         struct dsi_packet_sent_handler_data l4_data = { dsidev, &completion };
2674         int r = 0;
2675
2676         r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2677                 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2678         if (r)
2679                 goto err0;
2680
2681         /* Wait for completion only if TX_FIFO_NOT_EMPTY is still set */
2682         if (REG_GET(dsidev, DSI_VC_CTRL(channel), 5, 5)) {
2683                 if (wait_for_completion_timeout(&completion,
2684                                 msecs_to_jiffies(10)) == 0) {
2685                         DSSERR("Failed to complete previous l4 transfer\n");
2686                         r = -EIO;
2687                         goto err1;
2688                 }
2689         }
2690
2691         dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2692                 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2693
2694         return 0;
2695 err1:
2696         dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2697                 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2698 err0:
2699         return r;
2700 }
2701
2702 static int dsi_sync_vc(struct platform_device *dsidev, int channel)
2703 {
2704         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2705
2706         WARN_ON(!dsi_bus_is_locked(dsidev));
2707
2708         WARN_ON(in_interrupt());
2709
2710         if (!dsi_vc_is_enabled(dsidev, channel))
2711                 return 0;
2712
2713         switch (dsi->vc[channel].source) {
2714         case DSI_VC_SOURCE_VP:
2715                 return dsi_sync_vc_vp(dsidev, channel);
2716         case DSI_VC_SOURCE_L4:
2717                 return dsi_sync_vc_l4(dsidev, channel);
2718         default:
2719                 BUG();
2720         }
2721 }
2722
2723 static int dsi_vc_enable(struct platform_device *dsidev, int channel,
2724                 bool enable)
2725 {
2726         DSSDBG("dsi_vc_enable channel %d, enable %d\n",
2727                         channel, enable);
2728
2729         enable = enable ? 1 : 0;
2730
2731         REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 0, 0);
2732
2733         if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel),
2734                 0, enable) != enable) {
2735                         DSSERR("Failed to set dsi_vc_enable to %d\n", enable);
2736                         return -EIO;
2737         }
2738
2739         return 0;
2740 }
2741
2742 static void dsi_vc_initial_config(struct platform_device *dsidev, int channel)
2743 {
2744         u32 r;
2745
2746         DSSDBGF("%d", channel);
2747
2748         r = dsi_read_reg(dsidev, DSI_VC_CTRL(channel));
2749
2750         if (FLD_GET(r, 15, 15)) /* VC_BUSY */
2751                 DSSERR("VC(%d) busy when trying to configure it!\n",
2752                                 channel);
2753
2754         r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */
2755         r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN  */
2756         r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
2757         r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
2758         r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
2759         r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
2760         r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */
2761         if (dss_has_feature(FEAT_DSI_VC_OCP_WIDTH))
2762                 r = FLD_MOD(r, 3, 11, 10);      /* OCP_WIDTH = 32 bit */
2763
2764         r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
2765         r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
2766
2767         dsi_write_reg(dsidev, DSI_VC_CTRL(channel), r);
2768 }
2769
2770 static int dsi_vc_config_source(struct platform_device *dsidev, int channel,
2771                 enum dsi_vc_source source)
2772 {
2773         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2774
2775         if (dsi->vc[channel].source == source)
2776                 return 0;
2777
2778         DSSDBGF("%d", channel);
2779
2780         dsi_sync_vc(dsidev, channel);
2781
2782         dsi_vc_enable(dsidev, channel, 0);
2783
2784         /* VC_BUSY */
2785         if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel), 15, 0) != 0) {
2786                 DSSERR("vc(%d) busy when trying to config for VP\n", channel);
2787                 return -EIO;
2788         }
2789
2790         /* SOURCE, 0 = L4, 1 = video port */
2791         REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), source, 1, 1);
2792
2793         /* DCS_CMD_ENABLE */
2794         if (dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) {
2795                 bool enable = source == DSI_VC_SOURCE_VP;
2796                 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 30, 30);
2797         }
2798
2799         dsi_vc_enable(dsidev, channel, 1);
2800
2801         dsi->vc[channel].source = source;
2802
2803         return 0;
2804 }
2805
2806 void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
2807                 bool enable)
2808 {
2809         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2810
2811         DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable);
2812
2813         WARN_ON(!dsi_bus_is_locked(dsidev));
2814
2815         dsi_vc_enable(dsidev, channel, 0);
2816         dsi_if_enable(dsidev, 0);
2817
2818         REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 9, 9);
2819
2820         dsi_vc_enable(dsidev, channel, 1);
2821         dsi_if_enable(dsidev, 1);
2822
2823         dsi_force_tx_stop_mode_io(dsidev);
2824
2825         /* start the DDR clock by sending a NULL packet */
2826         if (dssdev->panel.dsi_vm_data.ddr_clk_always_on && enable)
2827                 dsi_vc_send_null(dssdev, channel);
2828 }
2829 EXPORT_SYMBOL(omapdss_dsi_vc_enable_hs);
2830
2831 static void dsi_vc_flush_long_data(struct platform_device *dsidev, int channel)
2832 {
2833         while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2834                 u32 val;
2835                 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
2836                 DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
2837                                 (val >> 0) & 0xff,
2838                                 (val >> 8) & 0xff,
2839                                 (val >> 16) & 0xff,
2840                                 (val >> 24) & 0xff);
2841         }
2842 }
2843
2844 static void dsi_show_rx_ack_with_err(u16 err)
2845 {
2846         DSSERR("\tACK with ERROR (%#x):\n", err);
2847         if (err & (1 << 0))
2848                 DSSERR("\t\tSoT Error\n");
2849         if (err & (1 << 1))
2850                 DSSERR("\t\tSoT Sync Error\n");
2851         if (err & (1 << 2))
2852                 DSSERR("\t\tEoT Sync Error\n");
2853         if (err & (1 << 3))
2854                 DSSERR("\t\tEscape Mode Entry Command Error\n");
2855         if (err & (1 << 4))
2856                 DSSERR("\t\tLP Transmit Sync Error\n");
2857         if (err & (1 << 5))
2858                 DSSERR("\t\tHS Receive Timeout Error\n");
2859         if (err & (1 << 6))
2860                 DSSERR("\t\tFalse Control Error\n");
2861         if (err & (1 << 7))
2862                 DSSERR("\t\t(reserved7)\n");
2863         if (err & (1 << 8))
2864                 DSSERR("\t\tECC Error, single-bit (corrected)\n");
2865         if (err & (1 << 9))
2866                 DSSERR("\t\tECC Error, multi-bit (not corrected)\n");
2867         if (err & (1 << 10))
2868                 DSSERR("\t\tChecksum Error\n");
2869         if (err & (1 << 11))
2870                 DSSERR("\t\tData type not recognized\n");
2871         if (err & (1 << 12))
2872                 DSSERR("\t\tInvalid VC ID\n");
2873         if (err & (1 << 13))
2874                 DSSERR("\t\tInvalid Transmission Length\n");
2875         if (err & (1 << 14))
2876                 DSSERR("\t\t(reserved14)\n");
2877         if (err & (1 << 15))
2878                 DSSERR("\t\tDSI Protocol Violation\n");
2879 }
2880
2881 static u16 dsi_vc_flush_receive_data(struct platform_device *dsidev,
2882                 int channel)
2883 {
2884         /* RX_FIFO_NOT_EMPTY */
2885         while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2886                 u32 val;
2887                 u8 dt;
2888                 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
2889                 DSSERR("\trawval %#08x\n", val);
2890                 dt = FLD_GET(val, 5, 0);
2891                 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
2892                         u16 err = FLD_GET(val, 23, 8);
2893                         dsi_show_rx_ack_with_err(err);
2894                 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE) {
2895                         DSSERR("\tDCS short response, 1 byte: %#x\n",
2896                                         FLD_GET(val, 23, 8));
2897                 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE) {
2898                         DSSERR("\tDCS short response, 2 byte: %#x\n",
2899                                         FLD_GET(val, 23, 8));
2900                 } else if (dt == MIPI_DSI_RX_DCS_LONG_READ_RESPONSE) {
2901                         DSSERR("\tDCS long response, len %d\n",
2902                                         FLD_GET(val, 23, 8));
2903                         dsi_vc_flush_long_data(dsidev, channel);
2904                 } else {
2905                         DSSERR("\tunknown datatype 0x%02x\n", dt);
2906                 }
2907         }
2908         return 0;
2909 }
2910
2911 static int dsi_vc_send_bta(struct platform_device *dsidev, int channel)
2912 {
2913         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2914
2915         if (dsi->debug_write || dsi->debug_read)
2916                 DSSDBG("dsi_vc_send_bta %d\n", channel);
2917
2918         WARN_ON(!dsi_bus_is_locked(dsidev));
2919
2920         /* RX_FIFO_NOT_EMPTY */
2921         if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2922                 DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
2923                 dsi_vc_flush_receive_data(dsidev, channel);
2924         }
2925
2926         REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */
2927
2928         /* flush posted write */
2929         dsi_read_reg(dsidev, DSI_VC_CTRL(channel));
2930
2931         return 0;
2932 }
2933
2934 int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel)
2935 {
2936         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2937         DECLARE_COMPLETION_ONSTACK(completion);
2938         int r = 0;
2939         u32 err;
2940
2941         r = dsi_register_isr_vc(dsidev, channel, dsi_completion_handler,
2942                         &completion, DSI_VC_IRQ_BTA);
2943         if (r)
2944                 goto err0;
2945
2946         r = dsi_register_isr(dsidev, dsi_completion_handler, &completion,
2947                         DSI_IRQ_ERROR_MASK);
2948         if (r)
2949                 goto err1;
2950
2951         r = dsi_vc_send_bta(dsidev, channel);
2952         if (r)
2953                 goto err2;
2954
2955         if (wait_for_completion_timeout(&completion,
2956                                 msecs_to_jiffies(500)) == 0) {
2957                 DSSERR("Failed to receive BTA\n");
2958                 r = -EIO;
2959                 goto err2;
2960         }
2961
2962         err = dsi_get_errors(dsidev);
2963         if (err) {
2964                 DSSERR("Error while sending BTA: %x\n", err);
2965                 r = -EIO;
2966                 goto err2;
2967         }
2968 err2:
2969         dsi_unregister_isr(dsidev, dsi_completion_handler, &completion,
2970                         DSI_IRQ_ERROR_MASK);
2971 err1:
2972         dsi_unregister_isr_vc(dsidev, channel, dsi_completion_handler,
2973                         &completion, DSI_VC_IRQ_BTA);
2974 err0:
2975         return r;
2976 }
2977 EXPORT_SYMBOL(dsi_vc_send_bta_sync);
2978
2979 static inline void dsi_vc_write_long_header(struct platform_device *dsidev,
2980                 int channel, u8 data_type, u16 len, u8 ecc)
2981 {
2982         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2983         u32 val;
2984         u8 data_id;
2985
2986         WARN_ON(!dsi_bus_is_locked(dsidev));
2987
2988         data_id = data_type | dsi->vc[channel].vc_id << 6;
2989
2990         val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) |
2991                 FLD_VAL(ecc, 31, 24);
2992
2993         dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_HEADER(channel), val);
2994 }
2995
2996 static inline void dsi_vc_write_long_payload(struct platform_device *dsidev,
2997                 int channel, u8 b1, u8 b2, u8 b3, u8 b4)
2998 {
2999         u32 val;
3000
3001         val = b4 << 24 | b3 << 16 | b2 << 8  | b1 << 0;
3002
3003 /*      DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
3004                         b1, b2, b3, b4, val); */
3005
3006         dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_PAYLOAD(channel), val);
3007 }
3008
3009 static int dsi_vc_send_long(struct platform_device *dsidev, int channel,
3010                 u8 data_type, u8 *data, u16 len, u8 ecc)
3011 {
3012         /*u32 val; */
3013         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3014         int i;
3015         u8 *p;
3016         int r = 0;
3017         u8 b1, b2, b3, b4;
3018
3019         if (dsi->debug_write)
3020                 DSSDBG("dsi_vc_send_long, %d bytes\n", len);
3021
3022         /* len + header */
3023         if (dsi->vc[channel].fifo_size * 32 * 4 < len + 4) {
3024                 DSSERR("unable to send long packet: packet too long.\n");
3025                 return -EINVAL;
3026         }
3027
3028         dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4);
3029
3030         dsi_vc_write_long_header(dsidev, channel, data_type, len, ecc);
3031
3032         p = data;
3033         for (i = 0; i < len >> 2; i++) {
3034                 if (dsi->debug_write)
3035                         DSSDBG("\tsending full packet %d\n", i);
3036
3037                 b1 = *p++;
3038                 b2 = *p++;
3039                 b3 = *p++;
3040                 b4 = *p++;
3041
3042                 dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, b4);
3043         }
3044
3045         i = len % 4;
3046         if (i) {
3047                 b1 = 0; b2 = 0; b3 = 0;
3048
3049                 if (dsi->debug_write)
3050                         DSSDBG("\tsending remainder bytes %d\n", i);
3051
3052                 switch (i) {
3053                 case 3:
3054                         b1 = *p++;
3055                         b2 = *p++;
3056                         b3 = *p++;
3057                         break;
3058                 case 2:
3059                         b1 = *p++;
3060                         b2 = *p++;
3061                         break;
3062                 case 1:
3063                         b1 = *p++;
3064                         break;
3065                 }
3066
3067                 dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, 0);
3068         }
3069
3070         return r;
3071 }
3072
3073 static int dsi_vc_send_short(struct platform_device *dsidev, int channel,
3074                 u8 data_type, u16 data, u8 ecc)
3075 {
3076         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3077         u32 r;
3078         u8 data_id;
3079
3080         WARN_ON(!dsi_bus_is_locked(dsidev));
3081
3082         if (dsi->debug_write)
3083                 DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
3084                                 channel,
3085                                 data_type, data & 0xff, (data >> 8) & 0xff);
3086
3087         dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4);
3088
3089         if (FLD_GET(dsi_read_reg(dsidev, DSI_VC_CTRL(channel)), 16, 16)) {
3090                 DSSERR("ERROR FIFO FULL, aborting transfer\n");
3091                 return -EINVAL;
3092         }
3093
3094         data_id = data_type | dsi->vc[channel].vc_id << 6;
3095
3096         r = (data_id << 0) | (data << 8) | (ecc << 24);
3097
3098         dsi_write_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel), r);
3099
3100         return 0;
3101 }
3102
3103 int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel)
3104 {
3105         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3106
3107         return dsi_vc_send_long(dsidev, channel, MIPI_DSI_NULL_PACKET, NULL,
3108                 0, 0);
3109 }
3110 EXPORT_SYMBOL(dsi_vc_send_null);
3111
3112 static int dsi_vc_write_nosync_common(struct omap_dss_device *dssdev,
3113                 int channel, u8 *data, int len, enum dss_dsi_content_type type)
3114 {
3115         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3116         int r;
3117
3118         if (len == 0) {
3119                 BUG_ON(type == DSS_DSI_CONTENT_DCS);
3120                 r = dsi_vc_send_short(dsidev, channel,
3121                                 MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM, 0, 0);
3122         } else if (len == 1) {
3123                 r = dsi_vc_send_short(dsidev, channel,
3124                                 type == DSS_DSI_CONTENT_GENERIC ?
3125                                 MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM :
3126                                 MIPI_DSI_DCS_SHORT_WRITE, data[0], 0);
3127         } else if (len == 2) {
3128                 r = dsi_vc_send_short(dsidev, channel,
3129                                 type == DSS_DSI_CONTENT_GENERIC ?
3130                                 MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM :
3131                                 MIPI_DSI_DCS_SHORT_WRITE_PARAM,
3132                                 data[0] | (data[1] << 8), 0);
3133         } else {
3134                 r = dsi_vc_send_long(dsidev, channel,
3135                                 type == DSS_DSI_CONTENT_GENERIC ?
3136                                 MIPI_DSI_GENERIC_LONG_WRITE :
3137                                 MIPI_DSI_DCS_LONG_WRITE, data, len, 0);
3138         }
3139
3140         return r;
3141 }
3142
3143 int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
3144                 u8 *data, int len)
3145 {
3146         return dsi_vc_write_nosync_common(dssdev, channel, data, len,
3147                         DSS_DSI_CONTENT_DCS);
3148 }
3149 EXPORT_SYMBOL(dsi_vc_dcs_write_nosync);
3150
3151 int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel,
3152                 u8 *data, int len)
3153 {
3154         return dsi_vc_write_nosync_common(dssdev, channel, data, len,
3155                         DSS_DSI_CONTENT_GENERIC);
3156 }
3157 EXPORT_SYMBOL(dsi_vc_generic_write_nosync);
3158
3159 static int dsi_vc_write_common(struct omap_dss_device *dssdev, int channel,
3160                 u8 *data, int len, enum dss_dsi_content_type type)
3161 {
3162         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3163         int r;
3164
3165         r = dsi_vc_write_nosync_common(dssdev, channel, data, len, type);
3166         if (r)
3167                 goto err;
3168
3169         r = dsi_vc_send_bta_sync(dssdev, channel);
3170         if (r)
3171                 goto err;
3172
3173         /* RX_FIFO_NOT_EMPTY */
3174         if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
3175                 DSSERR("rx fifo not empty after write, dumping data:\n");
3176                 dsi_vc_flush_receive_data(dsidev, channel);
3177                 r = -EIO;
3178                 goto err;
3179         }
3180
3181         return 0;
3182 err:
3183         DSSERR("dsi_vc_write_common(ch %d, cmd 0x%02x, len %d) failed\n",
3184                         channel, data[0], len);
3185         return r;
3186 }
3187
3188 int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data,
3189                 int len)
3190 {
3191         return dsi_vc_write_common(dssdev, channel, data, len,
3192                         DSS_DSI_CONTENT_DCS);
3193 }
3194 EXPORT_SYMBOL(dsi_vc_dcs_write);
3195
3196 int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data,
3197                 int len)
3198 {
3199         return dsi_vc_write_common(dssdev, channel, data, len,
3200                         DSS_DSI_CONTENT_GENERIC);
3201 }
3202 EXPORT_SYMBOL(dsi_vc_generic_write);
3203
3204 int dsi_vc_dcs_write_0(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd)
3205 {
3206         return dsi_vc_dcs_write(dssdev, channel, &dcs_cmd, 1);
3207 }
3208 EXPORT_SYMBOL(dsi_vc_dcs_write_0);
3209
3210 int dsi_vc_generic_write_0(struct omap_dss_device *dssdev, int channel)
3211 {
3212         return dsi_vc_generic_write(dssdev, channel, NULL, 0);
3213 }
3214 EXPORT_SYMBOL(dsi_vc_generic_write_0);
3215
3216 int dsi_vc_dcs_write_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
3217                 u8 param)
3218 {
3219         u8 buf[2];
3220         buf[0] = dcs_cmd;
3221         buf[1] = param;
3222         return dsi_vc_dcs_write(dssdev, channel, buf, 2);
3223 }
3224 EXPORT_SYMBOL(dsi_vc_dcs_write_1);
3225
3226 int dsi_vc_generic_write_1(struct omap_dss_device *dssdev, int channel,
3227                 u8 param)
3228 {
3229         return dsi_vc_generic_write(dssdev, channel, &param, 1);
3230 }
3231 EXPORT_SYMBOL(dsi_vc_generic_write_1);
3232
3233 int dsi_vc_generic_write_2(struct omap_dss_device *dssdev, int channel,
3234                 u8 param1, u8 param2)
3235 {
3236         u8 buf[2];
3237         buf[0] = param1;
3238         buf[1] = param2;
3239         return dsi_vc_generic_write(dssdev, channel, buf, 2);
3240 }
3241 EXPORT_SYMBOL(dsi_vc_generic_write_2);
3242
3243 static int dsi_vc_dcs_send_read_request(struct omap_dss_device *dssdev,
3244                 int channel, u8 dcs_cmd)
3245 {
3246         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3247         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3248         int r;
3249
3250         if (dsi->debug_read)
3251                 DSSDBG("dsi_vc_dcs_send_read_request(ch%d, dcs_cmd %x)\n",
3252                         channel, dcs_cmd);
3253
3254         r = dsi_vc_send_short(dsidev, channel, MIPI_DSI_DCS_READ, dcs_cmd, 0);
3255         if (r) {
3256                 DSSERR("dsi_vc_dcs_send_read_request(ch %d, cmd 0x%02x)"
3257                         " failed\n", channel, dcs_cmd);
3258                 return r;
3259         }
3260
3261         return 0;
3262 }
3263
3264 static int dsi_vc_generic_send_read_request(struct omap_dss_device *dssdev,
3265                 int channel, u8 *reqdata, int reqlen)
3266 {
3267         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3268         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3269         u16 data;
3270         u8 data_type;
3271         int r;
3272
3273         if (dsi->debug_read)
3274                 DSSDBG("dsi_vc_generic_send_read_request(ch %d, reqlen %d)\n",
3275                         channel, reqlen);
3276
3277         if (reqlen == 0) {
3278                 data_type = MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM;
3279                 data = 0;
3280         } else if (reqlen == 1) {
3281                 data_type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM;
3282                 data = reqdata[0];
3283         } else if (reqlen == 2) {
3284                 data_type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM;
3285                 data = reqdata[0] | (reqdata[1] << 8);
3286         } else {
3287                 BUG();
3288         }
3289
3290         r = dsi_vc_send_short(dsidev, channel, data_type, data, 0);
3291         if (r) {
3292                 DSSERR("dsi_vc_generic_send_read_request(ch %d, reqlen %d)"
3293                         " failed\n", channel, reqlen);
3294                 return r;
3295         }
3296
3297         return 0;
3298 }
3299
3300 static int dsi_vc_read_rx_fifo(struct platform_device *dsidev, int channel,
3301                 u8 *buf, int buflen, enum dss_dsi_content_type type)
3302 {
3303         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3304         u32 val;
3305         u8 dt;
3306         int r;
3307
3308         /* RX_FIFO_NOT_EMPTY */
3309         if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20) == 0) {
3310                 DSSERR("RX fifo empty when trying to read.\n");
3311                 r = -EIO;
3312                 goto err;
3313         }
3314
3315         val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
3316         if (dsi->debug_read)
3317                 DSSDBG("\theader: %08x\n", val);
3318         dt = FLD_GET(val, 5, 0);
3319         if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
3320                 u16 err = FLD_GET(val, 23, 8);
3321                 dsi_show_rx_ack_with_err(err);
3322                 r = -EIO;
3323                 goto err;
3324
3325         } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3326                         MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE :
3327                         MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE)) {
3328                 u8 data = FLD_GET(val, 15, 8);
3329                 if (dsi->debug_read)
3330                         DSSDBG("\t%s short response, 1 byte: %02x\n",
3331                                 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3332                                 "DCS", data);
3333
3334                 if (buflen < 1) {
3335                         r = -EIO;
3336                         goto err;
3337                 }
3338
3339                 buf[0] = data;
3340
3341                 return 1;
3342         } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3343                         MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE :
3344                         MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE)) {
3345                 u16 data = FLD_GET(val, 23, 8);
3346                 if (dsi->debug_read)
3347                         DSSDBG("\t%s short response, 2 byte: %04x\n",
3348                                 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3349                                 "DCS", data);
3350
3351                 if (buflen < 2) {
3352                         r = -EIO;
3353                         goto err;
3354                 }
3355
3356                 buf[0] = data & 0xff;
3357                 buf[1] = (data >> 8) & 0xff;
3358
3359                 return 2;
3360         } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3361                         MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE :
3362                         MIPI_DSI_RX_DCS_LONG_READ_RESPONSE)) {
3363                 int w;
3364                 int len = FLD_GET(val, 23, 8);
3365                 if (dsi->debug_read)
3366                         DSSDBG("\t%s long response, len %d\n",
3367                                 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3368                                 "DCS", len);
3369
3370                 if (len > buflen) {
3371                         r = -EIO;
3372                         goto err;
3373                 }
3374
3375                 /* two byte checksum ends the packet, not included in len */
3376                 for (w = 0; w < len + 2;) {
3377                         int b;
3378                         val = dsi_read_reg(dsidev,
3379                                 DSI_VC_SHORT_PACKET_HEADER(channel));
3380                         if (dsi->debug_read)
3381                                 DSSDBG("\t\t%02x %02x %02x %02x\n",
3382                                                 (val >> 0) & 0xff,
3383                                                 (val >> 8) & 0xff,
3384                                                 (val >> 16) & 0xff,
3385                                                 (val >> 24) & 0xff);
3386
3387                         for (b = 0; b < 4; ++b) {
3388                                 if (w < len)
3389                                         buf[w] = (val >> (b * 8)) & 0xff;
3390                                 /* we discard the 2 byte checksum */
3391                                 ++w;
3392                         }
3393                 }
3394
3395                 return len;
3396         } else {
3397                 DSSERR("\tunknown datatype 0x%02x\n", dt);
3398                 r = -EIO;
3399                 goto err;
3400         }
3401
3402         BUG();
3403 err:
3404         DSSERR("dsi_vc_read_rx_fifo(ch %d type %s) failed\n", channel,
3405                 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : "DCS");
3406
3407         return r;
3408 }
3409
3410 int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
3411                 u8 *buf, int buflen)
3412 {
3413         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3414         int r;
3415
3416         r = dsi_vc_dcs_send_read_request(dssdev, channel, dcs_cmd);
3417         if (r)
3418                 goto err;
3419
3420         r = dsi_vc_send_bta_sync(dssdev, channel);
3421         if (r)
3422                 goto err;
3423
3424         r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen,
3425                 DSS_DSI_CONTENT_DCS);
3426         if (r < 0)
3427                 goto err;
3428
3429         if (r != buflen) {
3430                 r = -EIO;
3431                 goto err;
3432         }
3433
3434         return 0;
3435 err:
3436         DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n", channel, dcs_cmd);
3437         return r;
3438 }
3439 EXPORT_SYMBOL(dsi_vc_dcs_read);
3440
3441 static int dsi_vc_generic_read(struct omap_dss_device *dssdev, int channel,
3442                 u8 *reqdata, int reqlen, u8 *buf, int buflen)
3443 {
3444         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3445         int r;
3446
3447         r = dsi_vc_generic_send_read_request(dssdev, channel, reqdata, reqlen);
3448         if (r)
3449                 return r;
3450
3451         r = dsi_vc_send_bta_sync(dssdev, channel);
3452         if (r)
3453                 return r;
3454
3455         r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen,
3456                 DSS_DSI_CONTENT_GENERIC);
3457         if (r < 0)
3458                 return r;
3459
3460         if (r != buflen) {
3461                 r = -EIO;
3462                 return r;
3463         }
3464
3465         return 0;
3466 }
3467
3468 int dsi_vc_generic_read_0(struct omap_dss_device *dssdev, int channel, u8 *buf,
3469                 int buflen)
3470 {
3471         int r;
3472
3473         r = dsi_vc_generic_read(dssdev, channel, NULL, 0, buf, buflen);
3474         if (r) {
3475                 DSSERR("dsi_vc_generic_read_0(ch %d) failed\n", channel);
3476                 return r;
3477         }
3478
3479         return 0;
3480 }
3481 EXPORT_SYMBOL(dsi_vc_generic_read_0);
3482
3483 int dsi_vc_generic_read_1(struct omap_dss_device *dssdev, int channel, u8 param,
3484                 u8 *buf, int buflen)
3485 {
3486         int r;
3487
3488         r = dsi_vc_generic_read(dssdev, channel, &param, 1, buf, buflen);
3489         if (r) {
3490                 DSSERR("dsi_vc_generic_read_1(ch %d) failed\n", channel);
3491                 return r;
3492         }
3493
3494         return 0;
3495 }
3496 EXPORT_SYMBOL(dsi_vc_generic_read_1);
3497
3498 int dsi_vc_generic_read_2(struct omap_dss_device *dssdev, int channel,
3499                 u8 param1, u8 param2, u8 *buf, int buflen)
3500 {
3501         int r;
3502         u8 reqdata[2];
3503
3504         reqdata[0] = param1;
3505         reqdata[1] = param2;
3506
3507         r = dsi_vc_generic_read(dssdev, channel, reqdata, 2, buf, buflen);
3508         if (r) {
3509                 DSSERR("dsi_vc_generic_read_2(ch %d) failed\n", channel);
3510                 return r;
3511         }
3512
3513         return 0;
3514 }
3515 EXPORT_SYMBOL(dsi_vc_generic_read_2);
3516
3517 int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
3518                 u16 len)
3519 {
3520         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3521
3522         return dsi_vc_send_short(dsidev, channel,
3523                         MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, len, 0);
3524 }
3525 EXPORT_SYMBOL(dsi_vc_set_max_rx_packet_size);
3526
3527 static int dsi_enter_ulps(struct platform_device *dsidev)
3528 {
3529         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3530         DECLARE_COMPLETION_ONSTACK(completion);
3531         int r, i;
3532         unsigned mask;
3533
3534         DSSDBGF();
3535
3536         WARN_ON(!dsi_bus_is_locked(dsidev));
3537
3538         WARN_ON(dsi->ulps_enabled);
3539
3540         if (dsi->ulps_enabled)
3541                 return 0;
3542
3543         /* DDR_CLK_ALWAYS_ON */
3544         if (REG_GET(dsidev, DSI_CLK_CTRL, 13, 13)) {
3545                 dsi_if_enable(dsidev, 0);
3546                 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13);
3547                 dsi_if_enable(dsidev, 1);
3548         }
3549
3550         dsi_sync_vc(dsidev, 0);
3551         dsi_sync_vc(dsidev, 1);
3552         dsi_sync_vc(dsidev, 2);
3553         dsi_sync_vc(dsidev, 3);
3554
3555         dsi_force_tx_stop_mode_io(dsidev);
3556
3557         dsi_vc_enable(dsidev, 0, false);
3558         dsi_vc_enable(dsidev, 1, false);
3559         dsi_vc_enable(dsidev, 2, false);
3560         dsi_vc_enable(dsidev, 3, false);
3561
3562         if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 16, 16)) {      /* HS_BUSY */
3563                 DSSERR("HS busy when enabling ULPS\n");
3564                 return -EIO;
3565         }
3566
3567         if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 17, 17)) {      /* LP_BUSY */
3568                 DSSERR("LP busy when enabling ULPS\n");
3569                 return -EIO;
3570         }
3571
3572         r = dsi_register_isr_cio(dsidev, dsi_completion_handler, &completion,
3573                         DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3574         if (r)
3575                 return r;
3576
3577         mask = 0;
3578
3579         for (i = 0; i < dsi->num_lanes_supported; ++i) {
3580                 if (dsi->lanes[i].function == DSI_LANE_UNUSED)
3581                         continue;
3582                 mask |= 1 << i;
3583         }
3584         /* Assert TxRequestEsc for data lanes and TxUlpsClk for clk lane */
3585         /* LANEx_ULPS_SIG2 */
3586         REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, mask, 9, 5);
3587
3588         /* flush posted write and wait for SCP interface to finish the write */
3589         dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2);
3590
3591         if (wait_for_completion_timeout(&completion,
3592                                 msecs_to_jiffies(1000)) == 0) {
3593                 DSSERR("ULPS enable timeout\n");
3594                 r = -EIO;
3595                 goto err;
3596         }
3597
3598         dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
3599                         DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3600
3601         /* Reset LANEx_ULPS_SIG2 */
3602         REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, 0, 9, 5);
3603
3604         /* flush posted write and wait for SCP interface to finish the write */
3605         dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2);
3606
3607         dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ULPS);
3608
3609         dsi_if_enable(dsidev, false);
3610
3611         dsi->ulps_enabled = true;
3612
3613         return 0;
3614
3615 err:
3616         dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
3617                         DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3618         return r;
3619 }
3620
3621 static void dsi_set_lp_rx_timeout(struct platform_device *dsidev,
3622                 unsigned ticks, bool x4, bool x16)
3623 {
3624         unsigned long fck;
3625         unsigned long total_ticks;
3626         u32 r;
3627
3628         BUG_ON(ticks > 0x1fff);
3629
3630         /* ticks in DSI_FCK */
3631         fck = dsi_fclk_rate(dsidev);
3632
3633         r = dsi_read_reg(dsidev, DSI_TIMING2);
3634         r = FLD_MOD(r, 1, 15, 15);      /* LP_RX_TO */
3635         r = FLD_MOD(r, x16 ? 1 : 0, 14, 14);    /* LP_RX_TO_X16 */
3636         r = FLD_MOD(r, x4 ? 1 : 0, 13, 13);     /* LP_RX_TO_X4 */
3637         r = FLD_MOD(r, ticks, 12, 0);   /* LP_RX_COUNTER */
3638         dsi_write_reg(dsidev, DSI_TIMING2, r);
3639
3640         total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3641
3642         DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3643                         total_ticks,
3644                         ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3645                         (total_ticks * 1000) / (fck / 1000 / 1000));
3646 }
3647
3648 static void dsi_set_ta_timeout(struct platform_device *dsidev, unsigned ticks,
3649                 bool x8, bool x16)
3650 {
3651         unsigned long fck;
3652         unsigned long total_ticks;
3653         u32 r;
3654
3655         BUG_ON(ticks > 0x1fff);
3656
3657         /* ticks in DSI_FCK */
3658         fck = dsi_fclk_rate(dsidev);
3659
3660         r = dsi_read_reg(dsidev, DSI_TIMING1);
3661         r = FLD_MOD(r, 1, 31, 31);      /* TA_TO */
3662         r = FLD_MOD(r, x16 ? 1 : 0, 30, 30);    /* TA_TO_X16 */
3663         r = FLD_MOD(r, x8 ? 1 : 0, 29, 29);     /* TA_TO_X8 */
3664         r = FLD_MOD(r, ticks, 28, 16);  /* TA_TO_COUNTER */
3665         dsi_write_reg(dsidev, DSI_TIMING1, r);
3666
3667         total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1);
3668
3669         DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n",
3670                         total_ticks,
3671                         ticks, x8 ? " x8" : "", x16 ? " x16" : "",
3672                         (total_ticks * 1000) / (fck / 1000 / 1000));
3673 }
3674
3675 static void dsi_set_stop_state_counter(struct platform_device *dsidev,
3676                 unsigned ticks, bool x4, bool x16)
3677 {
3678         unsigned long fck;
3679         unsigned long total_ticks;
3680         u32 r;
3681
3682         BUG_ON(ticks > 0x1fff);
3683
3684         /* ticks in DSI_FCK */
3685         fck = dsi_fclk_rate(dsidev);
3686
3687         r = dsi_read_reg(dsidev, DSI_TIMING1);
3688         r = FLD_MOD(r, 1, 15, 15);      /* FORCE_TX_STOP_MODE_IO */
3689         r = FLD_MOD(r, x16 ? 1 : 0, 14, 14);    /* STOP_STATE_X16_IO */
3690         r = FLD_MOD(r, x4 ? 1 : 0, 13, 13);     /* STOP_STATE_X4_IO */
3691         r = FLD_MOD(r, ticks, 12, 0);   /* STOP_STATE_COUNTER_IO */
3692         dsi_write_reg(dsidev, DSI_TIMING1, r);
3693
3694         total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3695
3696         DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n",
3697                         total_ticks,
3698                         ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3699                         (total_ticks * 1000) / (fck / 1000 / 1000));
3700 }
3701
3702 static void dsi_set_hs_tx_timeout(struct platform_device *dsidev,
3703                 unsigned ticks, bool x4, bool x16)
3704 {
3705         unsigned long fck;
3706         unsigned long total_ticks;
3707         u32 r;
3708
3709         BUG_ON(ticks > 0x1fff);
3710
3711         /* ticks in TxByteClkHS */
3712         fck = dsi_get_txbyteclkhs(dsidev);
3713
3714         r = dsi_read_reg(dsidev, DSI_TIMING2);
3715         r = FLD_MOD(r, 1, 31, 31);      /* HS_TX_TO */
3716         r = FLD_MOD(r, x16 ? 1 : 0, 30, 30);    /* HS_TX_TO_X16 */
3717         r = FLD_MOD(r, x4 ? 1 : 0, 29, 29);     /* HS_TX_TO_X8 (4 really) */
3718         r = FLD_MOD(r, ticks, 28, 16);  /* HS_TX_TO_COUNTER */
3719         dsi_write_reg(dsidev, DSI_TIMING2, r);
3720
3721         total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3722
3723         DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3724                         total_ticks,
3725                         ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3726                         (total_ticks * 1000) / (fck / 1000 / 1000));
3727 }
3728
3729 static void dsi_config_vp_num_line_buffers(struct omap_dss_device *dssdev)
3730 {
3731         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3732         int num_line_buffers;
3733
3734         if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) {
3735                 int bpp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt);
3736                 unsigned line_buf_size = dsi_get_line_buf_size(dsidev);
3737                 struct omap_video_timings *timings = &dssdev->panel.timings;
3738                 /*
3739                  * Don't use line buffers if width is greater than the video
3740                  * port's line buffer size
3741                  */
3742                 if (line_buf_size <= timings->x_res * bpp / 8)
3743                         num_line_buffers = 0;
3744                 else
3745                         num_line_buffers = 2;
3746         } else {
3747                 /* Use maximum number of line buffers in command mode */
3748                 num_line_buffers = 2;
3749         }
3750
3751         /* LINE_BUFFER */
3752         REG_FLD_MOD(dsidev, DSI_CTRL, num_line_buffers, 13, 12);
3753 }
3754
3755 static void dsi_config_vp_sync_events(struct omap_dss_device *dssdev)
3756 {
3757         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3758         int de_pol = dssdev->panel.dsi_vm_data.vp_de_pol;
3759         int hsync_pol = dssdev->panel.dsi_vm_data.vp_hsync_pol;
3760         int vsync_pol = dssdev->panel.dsi_vm_data.vp_vsync_pol;
3761         bool vsync_end = dssdev->panel.dsi_vm_data.vp_vsync_end;
3762         bool hsync_end = dssdev->panel.dsi_vm_data.vp_hsync_end;
3763         u32 r;
3764
3765         r = dsi_read_reg(dsidev, DSI_CTRL);
3766         r = FLD_MOD(r, de_pol, 9, 9);           /* VP_DE_POL */
3767         r = FLD_MOD(r, hsync_pol, 10, 10);      /* VP_HSYNC_POL */
3768         r = FLD_MOD(r, vsync_pol, 11, 11);      /* VP_VSYNC_POL */
3769         r = FLD_MOD(r, 1, 15, 15);              /* VP_VSYNC_START */
3770         r = FLD_MOD(r, vsync_end, 16, 16);      /* VP_VSYNC_END */
3771         r = FLD_MOD(r, 1, 17, 17);              /* VP_HSYNC_START */
3772         r = FLD_MOD(r, hsync_end, 18, 18);      /* VP_HSYNC_END */
3773         dsi_write_reg(dsidev, DSI_CTRL, r);
3774 }
3775
3776 static void dsi_config_blanking_modes(struct omap_dss_device *dssdev)
3777 {
3778         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3779         int blanking_mode = dssdev->panel.dsi_vm_data.blanking_mode;
3780         int hfp_blanking_mode = dssdev->panel.dsi_vm_data.hfp_blanking_mode;
3781         int hbp_blanking_mode = dssdev->panel.dsi_vm_data.hbp_blanking_mode;
3782         int hsa_blanking_mode = dssdev->panel.dsi_vm_data.hsa_blanking_mode;
3783         u32 r;
3784
3785         /*
3786          * 0 = TX FIFO packets sent or LPS in corresponding blanking periods
3787          * 1 = Long blanking packets are sent in corresponding blanking periods
3788          */
3789         r = dsi_read_reg(dsidev, DSI_CTRL);
3790         r = FLD_MOD(r, blanking_mode, 20, 20);          /* BLANKING_MODE */
3791         r = FLD_MOD(r, hfp_blanking_mode, 21, 21);      /* HFP_BLANKING */
3792         r = FLD_MOD(r, hbp_blanking_mode, 22, 22);      /* HBP_BLANKING */
3793         r = FLD_MOD(r, hsa_blanking_mode, 23, 23);      /* HSA_BLANKING */
3794         dsi_write_reg(dsidev, DSI_CTRL, r);
3795 }
3796
3797 static int dsi_proto_config(struct omap_dss_device *dssdev)
3798 {
3799         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3800         u32 r;
3801         int buswidth = 0;
3802
3803         dsi_config_tx_fifo(dsidev, DSI_FIFO_SIZE_32,
3804                         DSI_FIFO_SIZE_32,
3805                         DSI_FIFO_SIZE_32,
3806                         DSI_FIFO_SIZE_32);
3807
3808         dsi_config_rx_fifo(dsidev, DSI_FIFO_SIZE_32,
3809                         DSI_FIFO_SIZE_32,
3810                         DSI_FIFO_SIZE_32,
3811                         DSI_FIFO_SIZE_32);
3812
3813         /* XXX what values for the timeouts? */
3814         dsi_set_stop_state_counter(dsidev, 0x1000, false, false);
3815         dsi_set_ta_timeout(dsidev, 0x1fff, true, true);
3816         dsi_set_lp_rx_timeout(dsidev, 0x1fff, true, true);
3817         dsi_set_hs_tx_timeout(dsidev, 0x1fff, true, true);
3818
3819         switch (dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt)) {
3820         case 16:
3821                 buswidth = 0;
3822                 break;
3823         case 18:
3824                 buswidth = 1;
3825                 break;
3826         case 24:
3827                 buswidth = 2;
3828                 break;
3829         default:
3830                 BUG();
3831         }
3832
3833         r = dsi_read_reg(dsidev, DSI_CTRL);
3834         r = FLD_MOD(r, 1, 1, 1);        /* CS_RX_EN */
3835         r = FLD_MOD(r, 1, 2, 2);        /* ECC_RX_EN */
3836         r = FLD_MOD(r, 1, 3, 3);        /* TX_FIFO_ARBITRATION */
3837         r = FLD_MOD(r, 1, 4, 4);        /* VP_CLK_RATIO, always 1, see errata*/
3838         r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */
3839         r = FLD_MOD(r, 0, 8, 8);        /* VP_CLK_POL */
3840         r = FLD_MOD(r, 1, 14, 14);      /* TRIGGER_RESET_MODE */
3841         r = FLD_MOD(r, 1, 19, 19);      /* EOT_ENABLE */
3842         if (!dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) {
3843                 r = FLD_MOD(r, 1, 24, 24);      /* DCS_CMD_ENABLE */
3844                 /* DCS_CMD_CODE, 1=start, 0=continue */
3845                 r = FLD_MOD(r, 0, 25, 25);
3846         }
3847
3848         dsi_write_reg(dsidev, DSI_CTRL, r);
3849
3850         dsi_config_vp_num_line_buffers(dssdev);
3851
3852         if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) {
3853                 dsi_config_vp_sync_events(dssdev);
3854                 dsi_config_blanking_modes(dssdev);
3855         }
3856
3857         dsi_vc_initial_config(dsidev, 0);
3858         dsi_vc_initial_config(dsidev, 1);
3859         dsi_vc_initial_config(dsidev, 2);
3860         dsi_vc_initial_config(dsidev, 3);
3861
3862         return 0;
3863 }
3864
3865 static void dsi_proto_timings(struct omap_dss_device *dssdev)
3866 {
3867         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3868         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3869         unsigned tlpx, tclk_zero, tclk_prepare, tclk_trail;
3870         unsigned tclk_pre, tclk_post;
3871         unsigned ths_prepare, ths_prepare_ths_zero, ths_zero;
3872         unsigned ths_trail, ths_exit;
3873         unsigned ddr_clk_pre, ddr_clk_post;
3874         unsigned enter_hs_mode_lat, exit_hs_mode_lat;
3875         unsigned ths_eot;
3876         int ndl = dsi->num_lanes_used - 1;
3877         u32 r;
3878
3879         r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
3880         ths_prepare = FLD_GET(r, 31, 24);
3881         ths_prepare_ths_zero = FLD_GET(r, 23, 16);
3882         ths_zero = ths_prepare_ths_zero - ths_prepare;
3883         ths_trail = FLD_GET(r, 15, 8);
3884         ths_exit = FLD_GET(r, 7, 0);
3885
3886         r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
3887         tlpx = FLD_GET(r, 22, 16) * 2;
3888         tclk_trail = FLD_GET(r, 15, 8);
3889         tclk_zero = FLD_GET(r, 7, 0);
3890
3891         r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
3892         tclk_prepare = FLD_GET(r, 7, 0);
3893
3894         /* min 8*UI */
3895         tclk_pre = 20;
3896         /* min 60ns + 52*UI */
3897         tclk_post = ns2ddr(dsidev, 60) + 26;
3898
3899         ths_eot = DIV_ROUND_UP(4, ndl);
3900
3901         ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare,
3902                         4);
3903         ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot;
3904
3905         BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255);
3906         BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255);
3907
3908         r = dsi_read_reg(dsidev, DSI_CLK_TIMING);
3909         r = FLD_MOD(r, ddr_clk_pre, 15, 8);
3910         r = FLD_MOD(r, ddr_clk_post, 7, 0);
3911         dsi_write_reg(dsidev, DSI_CLK_TIMING, r);
3912
3913         DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n",
3914                         ddr_clk_pre,
3915                         ddr_clk_post);
3916
3917         enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) +
3918                 DIV_ROUND_UP(ths_prepare, 4) +
3919                 DIV_ROUND_UP(ths_zero + 3, 4);
3920
3921         exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot;
3922
3923         r = FLD_VAL(enter_hs_mode_lat, 31, 16) |
3924                 FLD_VAL(exit_hs_mode_lat, 15, 0);
3925         dsi_write_reg(dsidev, DSI_VM_TIMING7, r);
3926
3927         DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n",
3928                         enter_hs_mode_lat, exit_hs_mode_lat);
3929
3930          if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) {
3931                 /* TODO: Implement a video mode check_timings function */
3932                 int hsa = dssdev->panel.dsi_vm_data.hsa;
3933                 int hfp = dssdev->panel.dsi_vm_data.hfp;
3934                 int hbp = dssdev->panel.dsi_vm_data.hbp;
3935                 int vsa = dssdev->panel.dsi_vm_data.vsa;
3936                 int vfp = dssdev->panel.dsi_vm_data.vfp;
3937                 int vbp = dssdev->panel.dsi_vm_data.vbp;
3938                 int window_sync = dssdev->panel.dsi_vm_data.window_sync;
3939                 bool hsync_end = dssdev->panel.dsi_vm_data.vp_hsync_end;
3940                 struct omap_video_timings *timings = &dssdev->panel.timings;
3941                 int bpp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt);
3942                 int tl, t_he, width_bytes;
3943
3944                 t_he = hsync_end ?
3945                         ((hsa == 0 && ndl == 3) ? 1 : DIV_ROUND_UP(4, ndl)) : 0;
3946
3947                 width_bytes = DIV_ROUND_UP(timings->x_res * bpp, 8);
3948
3949                 /* TL = t_HS + HSA + t_HE + HFP + ceil((WC + 6) / NDL) + HBP */
3950                 tl = DIV_ROUND_UP(4, ndl) + (hsync_end ? hsa : 0) + t_he + hfp +
3951                         DIV_ROUND_UP(width_bytes + 6, ndl) + hbp;
3952
3953                 DSSDBG("HBP: %d, HFP: %d, HSA: %d, TL: %d TXBYTECLKHS\n", hbp,
3954                         hfp, hsync_end ? hsa : 0, tl);
3955                 DSSDBG("VBP: %d, VFP: %d, VSA: %d, VACT: %d lines\n", vbp, vfp,
3956                         vsa, timings->y_res);
3957
3958                 r = dsi_read_reg(dsidev, DSI_VM_TIMING1);
3959                 r = FLD_MOD(r, hbp, 11, 0);     /* HBP */
3960                 r = FLD_MOD(r, hfp, 23, 12);    /* HFP */
3961                 r = FLD_MOD(r, hsync_end ? hsa : 0, 31, 24);    /* HSA */
3962                 dsi_write_reg(dsidev, DSI_VM_TIMING1, r);
3963
3964                 r = dsi_read_reg(dsidev, DSI_VM_TIMING2);
3965                 r = FLD_MOD(r, vbp, 7, 0);      /* VBP */
3966                 r = FLD_MOD(r, vfp, 15, 8);     /* VFP */
3967                 r = FLD_MOD(r, vsa, 23, 16);    /* VSA */
3968                 r = FLD_MOD(r, window_sync, 27, 24);    /* WINDOW_SYNC */
3969                 dsi_write_reg(dsidev, DSI_VM_TIMING2, r);
3970
3971                 r = dsi_read_reg(dsidev, DSI_VM_TIMING3);
3972                 r = FLD_MOD(r, timings->y_res, 14, 0);  /* VACT */
3973                 r = FLD_MOD(r, tl, 31, 16);             /* TL */
3974                 dsi_write_reg(dsidev, DSI_VM_TIMING3, r);
3975         }
3976 }
3977
3978 int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel)
3979 {
3980         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3981         int bpp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt);
3982         u8 data_type;
3983         u16 word_count;
3984         int r;
3985
3986         if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) {
3987                 switch (dssdev->panel.dsi_pix_fmt) {
3988                 case OMAP_DSS_DSI_FMT_RGB888:
3989                         data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24;
3990                         break;
3991                 case OMAP_DSS_DSI_FMT_RGB666:
3992                         data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
3993                         break;
3994                 case OMAP_DSS_DSI_FMT_RGB666_PACKED:
3995                         data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18;
3996                         break;
3997                 case OMAP_DSS_DSI_FMT_RGB565:
3998                         data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16;
3999                         break;
4000                 default:
4001                         BUG();
4002                 };
4003
4004                 dsi_if_enable(dsidev, false);
4005                 dsi_vc_enable(dsidev, channel, false);
4006
4007                 /* MODE, 1 = video mode */
4008                 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 4, 4);
4009
4010                 word_count = DIV_ROUND_UP(dssdev->panel.timings.x_res * bpp, 8);
4011
4012                 dsi_vc_write_long_header(dsidev, channel, data_type,
4013                                 word_count, 0);
4014
4015                 dsi_vc_enable(dsidev, channel, true);
4016                 dsi_if_enable(dsidev, true);
4017         }
4018
4019         r = dss_mgr_enable(dssdev->manager);
4020         if (r) {
4021                 if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) {
4022                         dsi_if_enable(dsidev, false);
4023                         dsi_vc_enable(dsidev, channel, false);
4024                 }
4025
4026                 return r;
4027         }
4028
4029         return 0;
4030 }
4031 EXPORT_SYMBOL(dsi_enable_video_output);
4032
4033 void dsi_disable_video_output(struct omap_dss_device *dssdev, int channel)
4034 {
4035         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4036
4037         if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) {
4038                 dsi_if_enable(dsidev, false);
4039                 dsi_vc_enable(dsidev, channel, false);
4040
4041                 /* MODE, 0 = command mode */
4042                 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 0, 4, 4);
4043
4044                 dsi_vc_enable(dsidev, channel, true);
4045                 dsi_if_enable(dsidev, true);
4046         }
4047
4048         dss_mgr_disable(dssdev->manager);
4049 }
4050 EXPORT_SYMBOL(dsi_disable_video_output);
4051
4052 static void dsi_update_screen_dispc(struct omap_dss_device *dssdev,
4053                 u16 w, u16 h)
4054 {
4055         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4056         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4057         unsigned bytespp;
4058         unsigned bytespl;
4059         unsigned bytespf;
4060         unsigned total_len;
4061         unsigned packet_payload;
4062         unsigned packet_len;
4063         u32 l;
4064         int r;
4065         const unsigned channel = dsi->update_channel;
4066         const unsigned line_buf_size = dsi_get_line_buf_size(dsidev);
4067
4068         DSSDBG("dsi_update_screen_dispc(%dx%d)\n", w, h);
4069
4070         dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_VP);
4071
4072         bytespp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt) / 8;
4073         bytespl = w * bytespp;
4074         bytespf = bytespl * h;
4075
4076         /* NOTE: packet_payload has to be equal to N * bytespl, where N is
4077          * number of lines in a packet.  See errata about VP_CLK_RATIO */
4078
4079         if (bytespf < line_buf_size)
4080                 packet_payload = bytespf;
4081         else
4082                 packet_payload = (line_buf_size) / bytespl * bytespl;
4083
4084         packet_len = packet_payload + 1;        /* 1 byte for DCS cmd */
4085         total_len = (bytespf / packet_payload) * packet_len;
4086
4087         if (bytespf % packet_payload)
4088                 total_len += (bytespf % packet_payload) + 1;
4089
4090         l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */
4091         dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
4092
4093         dsi_vc_write_long_header(dsidev, channel, MIPI_DSI_DCS_LONG_WRITE,
4094                 packet_len, 0);
4095
4096         if (dsi->te_enabled)
4097                 l = FLD_MOD(l, 1, 30, 30); /* TE_EN */
4098         else
4099                 l = FLD_MOD(l, 1, 31, 31); /* TE_START */
4100         dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
4101
4102         /* We put SIDLEMODE to no-idle for the duration of the transfer,
4103          * because DSS interrupts are not capable of waking up the CPU and the
4104          * framedone interrupt could be delayed for quite a long time. I think
4105          * the same goes for any DSS interrupts, but for some reason I have not
4106          * seen the problem anywhere else than here.
4107          */
4108         dispc_disable_sidle();
4109
4110         dsi_perf_mark_start(dsidev);
4111
4112         r = schedule_delayed_work(&dsi->framedone_timeout_work,
4113                 msecs_to_jiffies(250));
4114         BUG_ON(r == 0);
4115
4116         dss_mgr_start_update(dssdev->manager);
4117
4118         if (dsi->te_enabled) {
4119                 /* disable LP_RX_TO, so that we can receive TE.  Time to wait
4120                  * for TE is longer than the timer allows */
4121                 REG_FLD_MOD(dsidev, DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */
4122
4123                 dsi_vc_send_bta(dsidev, channel);
4124
4125 #ifdef DSI_CATCH_MISSING_TE
4126                 mod_timer(&dsi->te_timer, jiffies + msecs_to_jiffies(250));
4127 #endif
4128         }
4129 }
4130
4131 #ifdef DSI_CATCH_MISSING_TE
4132 static void dsi_te_timeout(unsigned long arg)
4133 {
4134         DSSERR("TE not received for 250ms!\n");
4135 }
4136 #endif
4137
4138 static void dsi_handle_framedone(struct platform_device *dsidev, int error)
4139 {
4140         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4141
4142         /* SIDLEMODE back to smart-idle */
4143         dispc_enable_sidle();
4144
4145         if (dsi->te_enabled) {
4146                 /* enable LP_RX_TO again after the TE */
4147                 REG_FLD_MOD(dsidev, DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
4148         }
4149
4150         dsi->framedone_callback(error, dsi->framedone_data);
4151
4152         if (!error)
4153                 dsi_perf_show(dsidev, "DISPC");
4154 }
4155
4156 static void dsi_framedone_timeout_work_callback(struct work_struct *work)
4157 {
4158         struct dsi_data *dsi = container_of(work, struct dsi_data,
4159                         framedone_timeout_work.work);
4160         /* XXX While extremely unlikely, we could get FRAMEDONE interrupt after
4161          * 250ms which would conflict with this timeout work. What should be
4162          * done is first cancel the transfer on the HW, and then cancel the
4163          * possibly scheduled framedone work. However, cancelling the transfer
4164          * on the HW is buggy, and would probably require resetting the whole
4165          * DSI */
4166
4167         DSSERR("Framedone not received for 250ms!\n");
4168
4169         dsi_handle_framedone(dsi->pdev, -ETIMEDOUT);
4170 }
4171
4172 static void dsi_framedone_irq_callback(void *data, u32 mask)
4173 {
4174         struct omap_dss_device *dssdev = (struct omap_dss_device *) data;
4175         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4176         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4177
4178         /* Note: We get FRAMEDONE when DISPC has finished sending pixels and
4179          * turns itself off. However, DSI still has the pixels in its buffers,
4180          * and is sending the data.
4181          */
4182
4183         __cancel_delayed_work(&dsi->framedone_timeout_work);
4184
4185         dsi_handle_framedone(dsidev, 0);
4186
4187 #ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
4188         dispc_fake_vsync_irq();
4189 #endif
4190 }
4191
4192 int omap_dsi_update(struct omap_dss_device *dssdev, int channel,
4193                 void (*callback)(int, void *), void *data)
4194 {
4195         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4196         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4197         u16 dw, dh;
4198
4199         dsi_perf_mark_setup(dsidev);
4200
4201         dsi->update_channel = channel;
4202
4203         dsi->framedone_callback = callback;
4204         dsi->framedone_data = data;
4205
4206         dssdev->driver->get_resolution(dssdev, &dw, &dh);
4207
4208 #ifdef DEBUG
4209         dsi->update_bytes = dw * dh *
4210                 dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt) / 8;
4211 #endif
4212         dsi_update_screen_dispc(dssdev, dw, dh);
4213
4214         return 0;
4215 }
4216 EXPORT_SYMBOL(omap_dsi_update);
4217
4218 /* Display funcs */
4219
4220 static int dsi_display_init_dispc(struct omap_dss_device *dssdev)
4221 {
4222         int r;
4223
4224         if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_CMD_MODE) {
4225                 u16 dw, dh;
4226                 u32 irq;
4227                 struct omap_video_timings timings = {
4228                         .hsw            = 1,
4229                         .hfp            = 1,
4230                         .hbp            = 1,
4231                         .vsw            = 1,
4232                         .vfp            = 0,
4233                         .vbp            = 0,
4234                 };
4235
4236                 dssdev->driver->get_resolution(dssdev, &dw, &dh);
4237                 timings.x_res = dw;
4238                 timings.y_res = dh;
4239
4240                 irq = dssdev->manager->id == OMAP_DSS_CHANNEL_LCD ?
4241                         DISPC_IRQ_FRAMEDONE : DISPC_IRQ_FRAMEDONE2;
4242
4243                 r = omap_dispc_register_isr(dsi_framedone_irq_callback,
4244                         (void *) dssdev, irq);
4245                 if (r) {
4246                         DSSERR("can't get FRAMEDONE irq\n");
4247                         return r;
4248                 }
4249
4250                 dispc_mgr_enable_stallmode(dssdev->manager->id, true);
4251                 dispc_mgr_enable_fifohandcheck(dssdev->manager->id, 1);
4252
4253                 dispc_mgr_set_lcd_timings(dssdev->manager->id, &timings);
4254         } else {
4255                 dispc_mgr_enable_stallmode(dssdev->manager->id, false);
4256                 dispc_mgr_enable_fifohandcheck(dssdev->manager->id, 0);
4257
4258                 dispc_mgr_set_lcd_timings(dssdev->manager->id,
4259                         &dssdev->panel.timings);
4260         }
4261
4262                 dispc_mgr_set_lcd_display_type(dssdev->manager->id,
4263                         OMAP_DSS_LCD_DISPLAY_TFT);
4264                 dispc_mgr_set_tft_data_lines(dssdev->manager->id,
4265                         dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt));
4266         return 0;
4267 }
4268
4269 static void dsi_display_uninit_dispc(struct omap_dss_device *dssdev)
4270 {
4271         if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_CMD_MODE) {
4272                 u32 irq;
4273
4274                 irq = dssdev->manager->id == OMAP_DSS_CHANNEL_LCD ?
4275                         DISPC_IRQ_FRAMEDONE : DISPC_IRQ_FRAMEDONE2;
4276
4277                 omap_dispc_unregister_isr(dsi_framedone_irq_callback,
4278                         (void *) dssdev, irq);
4279         }
4280 }
4281
4282 static int dsi_configure_dsi_clocks(struct omap_dss_device *dssdev)
4283 {
4284         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4285         struct dsi_clock_info cinfo;
4286         int r;
4287
4288         /* we always use DSS_CLK_SYSCK as input clock */
4289         cinfo.use_sys_clk = true;
4290         cinfo.regn  = dssdev->clocks.dsi.regn;
4291         cinfo.regm  = dssdev->clocks.dsi.regm;
4292         cinfo.regm_dispc = dssdev->clocks.dsi.regm_dispc;
4293         cinfo.regm_dsi = dssdev->clocks.dsi.regm_dsi;
4294         r = dsi_calc_clock_rates(dssdev, &cinfo);
4295         if (r) {
4296                 DSSERR("Failed to calc dsi clocks\n");
4297                 return r;
4298         }
4299
4300         r = dsi_pll_set_clock_div(dsidev, &cinfo);
4301         if (r) {
4302                 DSSERR("Failed to set dsi clocks\n");
4303                 return r;
4304         }
4305
4306         return 0;
4307 }
4308
4309 static int dsi_configure_dispc_clocks(struct omap_dss_device *dssdev)
4310 {
4311         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4312         struct dispc_clock_info dispc_cinfo;
4313         int r;
4314         unsigned long long fck;
4315
4316         fck = dsi_get_pll_hsdiv_dispc_rate(dsidev);
4317
4318         dispc_cinfo.lck_div = dssdev->clocks.dispc.channel.lck_div;
4319         dispc_cinfo.pck_div = dssdev->clocks.dispc.channel.pck_div;
4320
4321         r = dispc_calc_clock_rates(fck, &dispc_cinfo);
4322         if (r) {
4323                 DSSERR("Failed to calc dispc clocks\n");
4324                 return r;
4325         }
4326
4327         r = dispc_mgr_set_clock_div(dssdev->manager->id, &dispc_cinfo);
4328         if (r) {
4329                 DSSERR("Failed to set dispc clocks\n");
4330                 return r;
4331         }
4332
4333         return 0;
4334 }
4335
4336 static int dsi_display_init_dsi(struct omap_dss_device *dssdev)
4337 {
4338         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4339         int dsi_module = dsi_get_dsidev_id(dsidev);
4340         int r;
4341
4342         r = dsi_parse_lane_config(dssdev);
4343         if (r) {
4344                 DSSERR("illegal lane config");
4345                 goto err0;
4346         }
4347
4348         r = dsi_pll_init(dsidev, true, true);
4349         if (r)
4350                 goto err0;
4351
4352         r = dsi_configure_dsi_clocks(dssdev);
4353         if (r)
4354                 goto err1;
4355
4356         dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src);
4357         dss_select_dsi_clk_source(dsi_module, dssdev->clocks.dsi.dsi_fclk_src);
4358         dss_select_lcd_clk_source(dssdev->manager->id,
4359                         dssdev->clocks.dispc.channel.lcd_clk_src);
4360
4361         DSSDBG("PLL OK\n");
4362
4363         r = dsi_configure_dispc_clocks(dssdev);
4364         if (r)
4365                 goto err2;
4366
4367         r = dsi_cio_init(dssdev);
4368         if (r)
4369                 goto err2;
4370
4371         _dsi_print_reset_status(dsidev);
4372
4373         dsi_proto_timings(dssdev);
4374         dsi_set_lp_clk_divisor(dssdev);
4375
4376         if (1)
4377                 _dsi_print_reset_status(dsidev);
4378
4379         r = dsi_proto_config(dssdev);
4380         if (r)
4381                 goto err3;
4382
4383         /* enable interface */
4384         dsi_vc_enable(dsidev, 0, 1);
4385         dsi_vc_enable(dsidev, 1, 1);
4386         dsi_vc_enable(dsidev, 2, 1);
4387         dsi_vc_enable(dsidev, 3, 1);
4388         dsi_if_enable(dsidev, 1);
4389         dsi_force_tx_stop_mode_io(dsidev);
4390
4391         return 0;
4392 err3:
4393         dsi_cio_uninit(dssdev);
4394 err2:
4395         dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
4396         dss_select_dsi_clk_source(dsi_module, OMAP_DSS_CLK_SRC_FCK);
4397         dss_select_lcd_clk_source(dssdev->manager->id, OMAP_DSS_CLK_SRC_FCK);
4398
4399 err1:
4400         dsi_pll_uninit(dsidev, true);
4401 err0:
4402         return r;
4403 }
4404
4405 static void dsi_display_uninit_dsi(struct omap_dss_device *dssdev,
4406                 bool disconnect_lanes, bool enter_ulps)
4407 {
4408         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4409         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4410         int dsi_module = dsi_get_dsidev_id(dsidev);
4411
4412         if (enter_ulps && !dsi->ulps_enabled)
4413                 dsi_enter_ulps(dsidev);
4414
4415         /* disable interface */
4416         dsi_if_enable(dsidev, 0);
4417         dsi_vc_enable(dsidev, 0, 0);
4418         dsi_vc_enable(dsidev, 1, 0);
4419         dsi_vc_enable(dsidev, 2, 0);
4420         dsi_vc_enable(dsidev, 3, 0);
4421
4422         dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
4423         dss_select_dsi_clk_source(dsi_module, OMAP_DSS_CLK_SRC_FCK);
4424         dss_select_lcd_clk_source(dssdev->manager->id, OMAP_DSS_CLK_SRC_FCK);
4425         dsi_cio_uninit(dssdev);
4426         dsi_pll_uninit(dsidev, disconnect_lanes);
4427 }
4428
4429 int omapdss_dsi_display_enable(struct omap_dss_device *dssdev)
4430 {
4431         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4432         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4433         int r = 0;
4434
4435         DSSDBG("dsi_display_enable\n");
4436
4437         WARN_ON(!dsi_bus_is_locked(dsidev));
4438
4439         mutex_lock(&dsi->lock);
4440
4441         if (dssdev->manager == NULL) {
4442                 DSSERR("failed to enable display: no manager\n");
4443                 r = -ENODEV;
4444                 goto err_start_dev;
4445         }
4446
4447         r = omap_dss_start_device(dssdev);
4448         if (r) {
4449                 DSSERR("failed to start device\n");
4450                 goto err_start_dev;
4451         }
4452
4453         r = dsi_runtime_get(dsidev);
4454         if (r)
4455                 goto err_get_dsi;
4456
4457         dsi_enable_pll_clock(dsidev, 1);
4458
4459         _dsi_initialize_irq(dsidev);
4460
4461         r = dsi_display_init_dispc(dssdev);
4462         if (r)
4463                 goto err_init_dispc;
4464
4465         r = dsi_display_init_dsi(dssdev);
4466         if (r)
4467                 goto err_init_dsi;
4468
4469         mutex_unlock(&dsi->lock);
4470
4471         return 0;
4472
4473 err_init_dsi:
4474         dsi_display_uninit_dispc(dssdev);
4475 err_init_dispc:
4476         dsi_enable_pll_clock(dsidev, 0);
4477         dsi_runtime_put(dsidev);
4478 err_get_dsi:
4479         omap_dss_stop_device(dssdev);
4480 err_start_dev:
4481         mutex_unlock(&dsi->lock);
4482         DSSDBG("dsi_display_enable FAILED\n");
4483         return r;
4484 }
4485 EXPORT_SYMBOL(omapdss_dsi_display_enable);
4486
4487 void omapdss_dsi_display_disable(struct omap_dss_device *dssdev,
4488                 bool disconnect_lanes, bool enter_ulps)
4489 {
4490         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4491         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4492
4493         DSSDBG("dsi_display_disable\n");
4494
4495         WARN_ON(!dsi_bus_is_locked(dsidev));
4496
4497         mutex_lock(&dsi->lock);
4498
4499         dsi_sync_vc(dsidev, 0);
4500         dsi_sync_vc(dsidev, 1);
4501         dsi_sync_vc(dsidev, 2);
4502         dsi_sync_vc(dsidev, 3);
4503
4504         dsi_display_uninit_dispc(dssdev);
4505
4506         dsi_display_uninit_dsi(dssdev, disconnect_lanes, enter_ulps);
4507
4508         dsi_runtime_put(dsidev);
4509         dsi_enable_pll_clock(dsidev, 0);
4510
4511         omap_dss_stop_device(dssdev);
4512
4513         mutex_unlock(&dsi->lock);
4514 }
4515 EXPORT_SYMBOL(omapdss_dsi_display_disable);
4516
4517 int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable)
4518 {
4519         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4520         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4521
4522         dsi->te_enabled = enable;
4523         return 0;
4524 }
4525 EXPORT_SYMBOL(omapdss_dsi_enable_te);
4526
4527 void dsi_get_overlay_fifo_thresholds(enum omap_plane plane,
4528                 u32 fifo_size, u32 burst_size,
4529                 u32 *fifo_low, u32 *fifo_high)
4530 {
4531         *fifo_high = fifo_size - burst_size;
4532         *fifo_low = fifo_size - burst_size * 2;
4533 }
4534
4535 int dsi_init_display(struct omap_dss_device *dssdev)
4536 {
4537         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4538         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4539
4540         DSSDBG("DSI init\n");
4541
4542         if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_CMD_MODE) {
4543                 dssdev->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE |
4544                         OMAP_DSS_DISPLAY_CAP_TEAR_ELIM;
4545         }
4546
4547         if (dsi->vdds_dsi_reg == NULL) {
4548                 struct regulator *vdds_dsi;
4549
4550                 vdds_dsi = regulator_get(&dsi->pdev->dev, "vdds_dsi");
4551
4552                 if (IS_ERR(vdds_dsi)) {
4553                         DSSERR("can't get VDDS_DSI regulator\n");
4554                         return PTR_ERR(vdds_dsi);
4555                 }
4556
4557                 dsi->vdds_dsi_reg = vdds_dsi;
4558         }
4559
4560         return 0;
4561 }
4562
4563 int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel)
4564 {
4565         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4566         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4567         int i;
4568
4569         for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
4570                 if (!dsi->vc[i].dssdev) {
4571                         dsi->vc[i].dssdev = dssdev;
4572                         *channel = i;
4573                         return 0;
4574                 }
4575         }
4576
4577         DSSERR("cannot get VC for display %s", dssdev->name);
4578         return -ENOSPC;
4579 }
4580 EXPORT_SYMBOL(omap_dsi_request_vc);
4581
4582 int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id)
4583 {
4584         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4585         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4586
4587         if (vc_id < 0 || vc_id > 3) {
4588                 DSSERR("VC ID out of range\n");
4589                 return -EINVAL;
4590         }
4591
4592         if (channel < 0 || channel > 3) {
4593                 DSSERR("Virtual Channel out of range\n");
4594                 return -EINVAL;
4595         }
4596
4597         if (dsi->vc[channel].dssdev != dssdev) {
4598                 DSSERR("Virtual Channel not allocated to display %s\n",
4599                         dssdev->name);
4600                 return -EINVAL;
4601         }
4602
4603         dsi->vc[channel].vc_id = vc_id;
4604
4605         return 0;
4606 }
4607 EXPORT_SYMBOL(omap_dsi_set_vc_id);
4608
4609 void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel)
4610 {
4611         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4612         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4613
4614         if ((channel >= 0 && channel <= 3) &&
4615                 dsi->vc[channel].dssdev == dssdev) {
4616                 dsi->vc[channel].dssdev = NULL;
4617                 dsi->vc[channel].vc_id = 0;
4618         }
4619 }
4620 EXPORT_SYMBOL(omap_dsi_release_vc);
4621
4622 void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev)
4623 {
4624         if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 7, 1) != 1)
4625                 DSSERR("%s (%s) not active\n",
4626                         dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
4627                         dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC));
4628 }
4629
4630 void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev)
4631 {
4632         if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 8, 1) != 1)
4633                 DSSERR("%s (%s) not active\n",
4634                         dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
4635                         dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI));
4636 }
4637
4638 static void dsi_calc_clock_param_ranges(struct platform_device *dsidev)
4639 {
4640         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4641
4642         dsi->regn_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGN);
4643         dsi->regm_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM);
4644         dsi->regm_dispc_max =
4645                 dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DISPC);
4646         dsi->regm_dsi_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DSI);
4647         dsi->fint_min = dss_feat_get_param_min(FEAT_PARAM_DSIPLL_FINT);
4648         dsi->fint_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_FINT);
4649         dsi->lpdiv_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_LPDIV);
4650 }
4651
4652 static int dsi_get_clocks(struct platform_device *dsidev)
4653 {
4654         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4655         struct clk *clk;
4656
4657         clk = clk_get(&dsidev->dev, "fck");
4658         if (IS_ERR(clk)) {
4659                 DSSERR("can't get fck\n");
4660                 return PTR_ERR(clk);
4661         }
4662
4663         dsi->dss_clk = clk;
4664
4665         clk = clk_get(&dsidev->dev, "sys_clk");
4666         if (IS_ERR(clk)) {
4667                 DSSERR("can't get sys_clk\n");
4668                 clk_put(dsi->dss_clk);
4669                 dsi->dss_clk = NULL;
4670                 return PTR_ERR(clk);
4671         }
4672
4673         dsi->sys_clk = clk;
4674
4675         return 0;
4676 }
4677
4678 static void dsi_put_clocks(struct platform_device *dsidev)
4679 {
4680         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4681
4682         if (dsi->dss_clk)
4683                 clk_put(dsi->dss_clk);
4684         if (dsi->sys_clk)
4685                 clk_put(dsi->sys_clk);
4686 }
4687
4688 /* DSI1 HW IP initialisation */
4689 static int omap_dsihw_probe(struct platform_device *dsidev)
4690 {
4691         struct omap_display_platform_data *dss_plat_data;
4692         struct omap_dss_board_info *board_info;
4693         u32 rev;
4694         int r, i, dsi_module = dsi_get_dsidev_id(dsidev);
4695         struct resource *dsi_mem;
4696         struct dsi_data *dsi;
4697
4698         dsi = kzalloc(sizeof(*dsi), GFP_KERNEL);
4699         if (!dsi) {
4700                 r = -ENOMEM;
4701                 goto err_alloc;
4702         }
4703
4704         dsi->pdev = dsidev;
4705         dsi_pdev_map[dsi_module] = dsidev;
4706         dev_set_drvdata(&dsidev->dev, dsi);
4707
4708         dss_plat_data = dsidev->dev.platform_data;
4709         board_info = dss_plat_data->board_data;
4710         dsi->enable_pads = board_info->dsi_enable_pads;
4711         dsi->disable_pads = board_info->dsi_disable_pads;
4712
4713         spin_lock_init(&dsi->irq_lock);
4714         spin_lock_init(&dsi->errors_lock);
4715         dsi->errors = 0;
4716
4717 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
4718         spin_lock_init(&dsi->irq_stats_lock);
4719         dsi->irq_stats.last_reset = jiffies;
4720 #endif
4721
4722         mutex_init(&dsi->lock);
4723         sema_init(&dsi->bus_lock, 1);
4724
4725         r = dsi_get_clocks(dsidev);
4726         if (r)
4727                 goto err_get_clk;
4728
4729         pm_runtime_enable(&dsidev->dev);
4730
4731         INIT_DELAYED_WORK_DEFERRABLE(&dsi->framedone_timeout_work,
4732                         dsi_framedone_timeout_work_callback);
4733
4734 #ifdef DSI_CATCH_MISSING_TE
4735         init_timer(&dsi->te_timer);
4736         dsi->te_timer.function = dsi_te_timeout;
4737         dsi->te_timer.data = 0;
4738 #endif
4739         dsi_mem = platform_get_resource(dsi->pdev, IORESOURCE_MEM, 0);
4740         if (!dsi_mem) {
4741                 DSSERR("can't get IORESOURCE_MEM DSI\n");
4742                 r = -EINVAL;
4743                 goto err_ioremap;
4744         }
4745         dsi->base = ioremap(dsi_mem->start, resource_size(dsi_mem));
4746         if (!dsi->base) {
4747                 DSSERR("can't ioremap DSI\n");
4748                 r = -ENOMEM;
4749                 goto err_ioremap;
4750         }
4751         dsi->irq = platform_get_irq(dsi->pdev, 0);
4752         if (dsi->irq < 0) {
4753                 DSSERR("platform_get_irq failed\n");
4754                 r = -ENODEV;
4755                 goto err_get_irq;
4756         }
4757
4758         r = request_irq(dsi->irq, omap_dsi_irq_handler, IRQF_SHARED,
4759                 dev_name(&dsidev->dev), dsi->pdev);
4760         if (r < 0) {
4761                 DSSERR("request_irq failed\n");
4762                 goto err_get_irq;
4763         }
4764
4765         /* DSI VCs initialization */
4766         for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
4767                 dsi->vc[i].source = DSI_VC_SOURCE_L4;
4768                 dsi->vc[i].dssdev = NULL;
4769                 dsi->vc[i].vc_id = 0;
4770         }
4771
4772         dsi_calc_clock_param_ranges(dsidev);
4773
4774         r = dsi_runtime_get(dsidev);
4775         if (r)
4776                 goto err_get_dsi;
4777
4778         rev = dsi_read_reg(dsidev, DSI_REVISION);
4779         dev_dbg(&dsidev->dev, "OMAP DSI rev %d.%d\n",
4780                FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
4781
4782         /* DSI on OMAP3 doesn't have register DSI_GNQ, set number
4783          * of data to 3 by default */
4784         if (dss_has_feature(FEAT_DSI_GNQ))
4785                 /* NB_DATA_LANES */
4786                 dsi->num_lanes_supported = 1 + REG_GET(dsidev, DSI_GNQ, 11, 9);
4787         else
4788                 dsi->num_lanes_supported = 3;
4789
4790         dsi_runtime_put(dsidev);
4791
4792         return 0;
4793
4794 err_get_dsi:
4795         free_irq(dsi->irq, dsi->pdev);
4796 err_get_irq:
4797         iounmap(dsi->base);
4798 err_ioremap:
4799         pm_runtime_disable(&dsidev->dev);
4800 err_get_clk:
4801         kfree(dsi);
4802 err_alloc:
4803         return r;
4804 }
4805
4806 static int omap_dsihw_remove(struct platform_device *dsidev)
4807 {
4808         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4809
4810         WARN_ON(dsi->scp_clk_refcount > 0);
4811
4812         pm_runtime_disable(&dsidev->dev);
4813
4814         dsi_put_clocks(dsidev);
4815
4816         if (dsi->vdds_dsi_reg != NULL) {
4817                 if (dsi->vdds_dsi_enabled) {
4818                         regulator_disable(dsi->vdds_dsi_reg);
4819                         dsi->vdds_dsi_enabled = false;
4820                 }
4821
4822                 regulator_put(dsi->vdds_dsi_reg);
4823                 dsi->vdds_dsi_reg = NULL;
4824         }
4825
4826         free_irq(dsi->irq, dsi->pdev);
4827         iounmap(dsi->base);
4828
4829         kfree(dsi);
4830
4831         return 0;
4832 }
4833
4834 static int dsi_runtime_suspend(struct device *dev)
4835 {
4836         dispc_runtime_put();
4837         dss_runtime_put();
4838
4839         return 0;
4840 }
4841
4842 static int dsi_runtime_resume(struct device *dev)
4843 {
4844         int r;
4845
4846         r = dss_runtime_get();
4847         if (r)
4848                 goto err_get_dss;
4849
4850         r = dispc_runtime_get();
4851         if (r)
4852                 goto err_get_dispc;
4853
4854         return 0;
4855
4856 err_get_dispc:
4857         dss_runtime_put();
4858 err_get_dss:
4859         return r;
4860 }
4861
4862 static const struct dev_pm_ops dsi_pm_ops = {
4863         .runtime_suspend = dsi_runtime_suspend,
4864         .runtime_resume = dsi_runtime_resume,
4865 };
4866
4867 static struct platform_driver omap_dsihw_driver = {
4868         .probe          = omap_dsihw_probe,
4869         .remove         = omap_dsihw_remove,
4870         .driver         = {
4871                 .name   = "omapdss_dsi",
4872                 .owner  = THIS_MODULE,
4873                 .pm     = &dsi_pm_ops,
4874         },
4875 };
4876
4877 int dsi_init_platform_driver(void)
4878 {
4879         return platform_driver_register(&omap_dsihw_driver);
4880 }
4881
4882 void dsi_uninit_platform_driver(void)
4883 {
4884         return platform_driver_unregister(&omap_dsihw_driver);
4885 }